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Searched defs:PredReg (Results 1 – 21 of 21) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp73 Register PredReg; in ReplaceTailWithBranchTo() local
121 Register PredReg; in isLegalToSplitMBBAt() local
293 ARMCC::CondCodes Pred, Register PredReg, in emitT2RegPlusImmediate()
553 Register PredReg; in rewriteT2FrameIndex() local
767 Register &PredReg) { in getITInstrPredicate()
785 Register &PredReg) { in getVPTInstrPredicate()
H A DThumb2InstrInfo.h86 Register PredReg; in getVPTInstrPredicate() local
H A DARMLoadStoreOptimizer.cpp490 unsigned PredReg) { in UpdateBaseRegUses()
907 Register PredReg; in MergeOpsUpdate() local
1296 Register PredReg; in MergeBaseUpdateLSMultiple() local
1492 Register PredReg; in MergeBaseUpdateLoadStore() local
1630 Register PredReg; in MergeBaseUpdateLSDouble() local
1800 Register PredReg; in FixInvalidRegPairOp() local
1900 Register PredReg; in LoadStoreMultipleOpti() local
2256 Register &PredReg, ARMCC::CondCodes &Pred, bool &isT2) { in CanFormLdStDWord()
2415 Register BaseReg, PredReg; in RescheduleOps() local
2564 Register PredReg; in RescheduleLoadStoreInstrs() local
[all …]
H A DMVEVPTBlockPass.cpp105 Register PredReg; in StepOverPredicatedInstrs() local
250 Register PredReg; in InsertVPTBlocks() local
H A DThumb2SizeReduction.cpp469 Register PredReg = MI->getOperand(5).getReg(); in ReduceLoadStore() local
687 Register PredReg; in ReduceSpecial() local
729 Register PredReg; in ReduceSpecial() local
800 Register PredReg; in ReduceTo2Addr() local
892 Register PredReg; in ReduceToNarrow() local
H A DThumbRegisterInfo.cpp65 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool()
85 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool()
106 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool()
H A DThumb2ITBlockPass.cpp201 Register PredReg; in InsertITInstructions() local
H A DARMBaseRegisterInfo.cpp499 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool()
852 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
H A DARMConstantIslandPass.cpp1470 Register PredReg; in createNewWater() local
1516 Register PredReg; in createNewWater() local
1540 Register PredReg; in createNewWater() local
1943 Register PredReg; in optimizeThumb2Branches() local
H A DMLxExpansionPass.cpp282 Register PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
H A DARMFrameLowering.cpp538 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitRegPlusImmediate()
552 unsigned PredReg = 0) { in emitSPUpdate()
2886 unsigned PredReg = TII.getFramePred(*I); in eliminateCallFramePseudoInstr() local
H A DARMISelDAGToDAG.cpp1752 SDValue PredReg; in tryMVEIndexedLoad() local
2919 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in SelectCDE_CXxD() local
4273 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
4285 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
4296 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
H A DARMBaseInstrInfo.cpp2233 Register &PredReg) { in getInstrPredicate()
2263 Register PredReg; in commuteInstructionImpl() local
2471 ARMCC::CondCodes Pred, Register PredReg, in emitARMRegPlusImmediate()
5617 Register PredReg; in findCMPToFoldIntoCBZ() local
H A DARMExpandPseudoInsts.cpp1066 Register PredReg; in ExpandMOV32BitImm() local
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
H A DHexagonMCCompound.cpp177 unsigned PredReg = Predicate.getReg(); in getCompoundOp() local
H A DHexagonMCChecker.cpp68 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg, in initReg()
94 unsigned PredReg = Hexagon::NoRegister; in init() local
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp321 bool HexagonGenPredicate::isScalarPred(RegisterSubReg PredReg) { in isScalarPred()
H A DHexagonInstrInfo.cpp1700 Register PredReg; in PredicateInstruction() local
4521 Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const { in getPredReg()
H A DHexagonHardwareLoops.cpp651 Register PredReg; in getLoopTripCount() local
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp1357 MachineInstr *PTest, unsigned MaskReg, unsigned PredReg, in optimizePTestInstr()