| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1564 EVT PartVT = VT; in getVectorTypeBreakdown() local
1683 MVT PartVT = in GetReturnInfo() local
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 160 MVT PartVT, EVT ValueVT, const Value *V, in getCopyFromParts()
322 MVT PartVT, EVT ValueVT, const Value *V, in getCopyFromPartsVector()
470 SDValue *Parts, unsigned NumParts, MVT PartVT, in getCopyToParts()
607 const SDLoc &DL, EVT PartVT) { in widenVectorToPartType()
645 MVT PartVT, const Value *V, in getCopyToPartsVector()
1988 MVT PartVT = TLI.getRegisterTypeForCallingConv(Context, CC, VT); in visitRet() local
9854 MVT PartVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(), in LowerCallTo() local
10533 MVT PartVT = TLI->getRegisterTypeForCallingConv(*CurDAG->getContext(), in LowerArguments() local
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| H A D | LegalizeVectorTypes.cpp | 4774 EVT PartVT = EVT::getVectorVT(*DAG.getContext(), EltVT, in WidenVecRes_EXTRACT_SUBVECTOR() local
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 3991 unsigned NumParts, MVT PartVT, in splitValueIntoRegisterParts()
4000 MVT PartVT, EVT ValueVT, in joinRegisterPartsIntoValue()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 1453 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts()
1469 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue()
1729 MVT PartVT = getRegisterTypeForCallingConv(Ctx, CLI.CallConv, OrigArgVT); in LowerCall() local
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 623 MVT PartVT = MVT::getVectorVT(VecTy.getVectorElementType(), OpsPerWord); in buildHvxVectorReg() local
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 11287 EVT PartVT = PartValue.getValueType(); in LowerCall() local
12391 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts()
12445 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 4397 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts()
4415 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 17811 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 2748 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts()
2765 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue()
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