1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2000 Berkeley Software Design, Inc. 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <[email protected]>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD$ 36 */ 37 38 /* 39 * I/O map in 16-bit mode. To switch to 32-bit mode, 40 * you need to perform a 32-bit write to the RDP register 41 * (writing a 0 is recommended). 42 */ 43 #define PCN_IO16_APROM00 0x00 44 #define PCN_IO16_APROM01 0x02 45 #define PCN_IO16_APROM02 0x04 46 #define PCN_IO16_APROM03 0x06 47 #define PCN_IO16_APROM04 0x08 48 #define PCN_IO16_APROM05 0x0A 49 #define PCN_IO16_APROM06 0x0C 50 #define PCN_IO16_APROM07 0x0E 51 #define PCN_IO16_RDP 0x10 52 #define PCN_IO16_RAP 0x12 53 #define PCN_IO16_RESET 0x14 54 #define PCN_IO16_BDP 0x16 55 56 /* 57 * I/O map in 32-bit mode. 58 */ 59 #define PCN_IO32_APROM00 0x00 60 #define PCN_IO32_APROM01 0x04 61 #define PCN_IO32_APROM02 0x08 62 #define PCN_IO32_APROM03 0x0C 63 #define PCN_IO32_RDP 0x10 64 #define PCN_IO32_RAP 0x14 65 #define PCN_IO32_RESET 0x18 66 #define PCN_IO32_BDP 0x1C 67 68 /* 69 * CSR registers 70 */ 71 #define PCN_CSR_CSR 0x00 72 #define PCN_CSR_IAB0 0x01 73 #define PCN_CSR_IAB1 0x02 74 #define PCN_CSR_IMR 0x03 75 #define PCN_CSR_TFEAT 0x04 76 #define PCN_CSR_EXTCTL1 0x05 77 #define PCN_CSR_DTBLLEN 0x06 78 #define PCN_CSR_EXTCTL2 0x07 79 #define PCN_CSR_MAR0 0x08 80 #define PCN_CSR_MAR1 0x09 81 #define PCN_CSR_MAR2 0x0A 82 #define PCN_CSR_MAR3 0x0B 83 #define PCN_CSR_PAR0 0x0C 84 #define PCN_CSR_PAR1 0x0D 85 #define PCN_CSR_PAR2 0x0E 86 #define PCN_CSR_MODE 0x0F 87 #define PCN_CSR_RXADDR0 0x18 88 #define PCN_CSR_RXADDR1 0x19 89 #define PCN_CSR_TXADDR0 0x1E 90 #define PCN_CSR_TXADDR1 0x1F 91 #define PCN_CSR_TXPOLL 0x2F 92 #define PCN_CSR_RXPOLL 0x31 93 #define PCN_CSR_RXRINGLEN 0x4C 94 #define PCN_CSR_TXRINGLEN 0x4E 95 #define PCN_CSR_DMACTL 0x50 96 #define PCN_CSR_BUSTIMER 0x52 97 #define PCN_CSR_MEMERRTIMEO 0x64 98 #define PCN_CSR_ONNOWMISC 0x74 99 #define PCN_CSR_ADVFEAT 0x7A 100 #define PCN_CSR_MACCFG 0x7D 101 #define PCN_CSR_CHIPID0 0x58 102 #define PCN_CSR_CHIPID1 0x59 103 104 /* 105 * Control and status register (CSR0) 106 */ 107 #define PCN_CSR_INIT 0x0001 108 #define PCN_CSR_START 0x0002 109 #define PCN_CSR_STOP 0x0004 110 #define PCN_CSR_TX 0x0008 111 #define PCN_CSR_TXON 0x0010 112 #define PCN_CSR_RXON 0x0020 113 #define PCN_CSR_INTEN 0x0040 114 #define PCN_CSR_INTR 0x0080 115 #define PCN_CSR_IDONE 0x0100 116 #define PCN_CSR_TINT 0x0200 117 #define PCN_CSR_RINT 0x0400 118 #define PCN_CSR_MERR 0x0800 119 #define PCN_CSR_MISS 0x1000 120 #define PCN_CSR_CERR 0x2000 121 #define PCN_CSR_ERR 0x8000 122 123 /* 124 * Interrupt masks and deferral control (CSR3) 125 */ 126 #define PCN_IMR_BSWAP 0x0004 127 #define PCN_IMR_ENMBA 0x0008 /* enable modified backoff alg */ 128 #define PCN_IMR_DXMT2PD 0x0010 129 #define PCN_IMR_LAPPEN 0x0020 /* lookahead packet processing enb */ 130 #define PCN_IMR_DXSUFLO 0x0040 /* disable TX stop on underflow */ 131 #define PCN_IMR_IDONE 0x0100 132 #define PCN_IMR_TINT 0x0200 133 #define PCN_IMR_RINT 0x0400 134 #define PCN_IMR_MERR 0x0800 135 #define PCN_IMR_MISS 0x1000 136 137 /* 138 * Test and features control (CSR4) 139 */ 140 #define PCN_TFEAT_TXSTRTMASK 0x0004 141 #define PCN_TFEAT_TXSTRT 0x0008 142 #define PCN_TFEAT_RXCCOFLOWM 0x0010 /* Rx collision counter oflow */ 143 #define PCN_TFEAT_RXCCOFLOW 0x0020 144 #define PCN_TFEAT_UINT 0x0040 145 #define PCN_TFEAT_UINTREQ 0x0080 146 #define PCN_TFEAT_MISSOFLOWM 0x0100 147 #define PCN_TFEAT_MISSOFLOW 0x0200 148 #define PCN_TFEAT_STRIP_FCS 0x0400 149 #define PCN_TFEAT_PAD_TX 0x0800 150 #define PCN_TFEAT_TXDPOLL 0x1000 151 #define PCN_TFEAT_DMAPLUS 0x4000 152 153 /* 154 * Extended control and interrupt 1 (CSR5) 155 */ 156 #define PCN_EXTCTL1_SPND 0x0001 /* suspend */ 157 #define PCN_EXTCTL1_MPMODE 0x0002 /* magic packet mode */ 158 #define PCN_EXTCTL1_MPENB 0x0004 /* magic packet enable */ 159 #define PCN_EXTCTL1_MPINTEN 0x0008 /* magic packet interrupt enable */ 160 #define PCN_EXTCTL1_MPINT 0x0010 /* magic packet interrupt */ 161 #define PCN_EXTCTL1_MPPLBA 0x0020 /* magic packet phys. logical bcast */ 162 #define PCN_EXTCTL1_EXDEFEN 0x0040 /* excessive deferral interrupt enb. */ 163 #define PCN_EXTCTL1_EXDEF 0x0080 /* excessive deferral interrupt */ 164 #define PCN_EXTCTL1_SINTEN 0x0400 /* system interrupt enable */ 165 #define PCN_EXTCTL1_SINT 0x0800 /* system interrupt */ 166 #define PCN_EXTCTL1_LTINTEN 0x4000 /* last TX interrupt enb */ 167 #define PCN_EXTCTL1_TXOKINTD 0x8000 /* TX OK interrupt disable */ 168 169 /* 170 * RX/TX descriptor len (CSR6) 171 */ 172 #define PCN_DTBLLEN_RLEN 0x0F00 173 #define PCN_DTBLLEN_TLEN 0xF000 174 175 /* 176 * Extended control and interrupt 2 (CSR7) 177 */ 178 #define PCN_EXTCTL2_MIIPDTINTE 0x0001 179 #define PCN_EXTCTL2_MIIPDTINT 0x0002 180 #define PCN_EXTCTL2_MCCIINTE 0x0004 181 #define PCN_EXTCTL2_MCCIINT 0x0008 182 #define PCN_EXTCTL2_MCCINTE 0x0010 183 #define PCN_EXTCTL2_MCCINT 0x0020 184 #define PCN_EXTCTL2_MAPINTE 0x0040 185 #define PCN_EXTCTL2_MAPINT 0x0080 186 #define PCN_EXTCTL2_MREINTE 0x0100 187 #define PCN_EXTCTL2_MREINT 0x0200 188 #define PCN_EXTCTL2_STINTE 0x0400 189 #define PCN_EXTCTL2_STINT 0x0800 190 #define PCN_EXTCTL2_RXDPOLL 0x1000 191 #define PCN_EXTCTL2_RDMD 0x2000 192 #define PCN_EXTCTL2_RXFRTG 0x4000 193 #define PCN_EXTCTL2_FASTSPNDE 0x8000 194 195 196 /* 197 * Mode (CSR15) 198 */ 199 #define PCN_MODE_RXD 0x0001 /* RX disable */ 200 #define PCN_MODE_TXD 0x0002 /* TX disable */ 201 #define PCN_MODE_LOOP 0x0004 /* loopback enable */ 202 #define PCN_MODE_TXCRCD 0x0008 203 #define PCN_MODE_FORCECOLL 0x0010 204 #define PCN_MODE_RETRYD 0x0020 205 #define PCN_MODE_INTLOOP 0x0040 206 #define PCN_MODE_PORTSEL 0x0180 207 #define PCN_MODE_RXVPAD 0x2000 208 #define PCN_MODE_RXNOBROAD 0x4000 209 #define PCN_MODE_PROMISC 0x8000 210 211 /* Settings for PCN_MODE_PORTSEL when ASEL (BCR2[1]) is 0 */ 212 #define PCN_PORT_AUI 0x0000 213 #define PCN_PORT_10BASET 0x0080 214 #define PCN_PORT_GPSI 0x0100 215 #define PCN_PORT_MII 0x0180 216 217 /* 218 * Chip ID values. 219 */ 220 /* CSR88-89: Chip ID masks */ 221 #define AMD_MASK 0x003 222 #define PART_MASK 0xffff 223 #define Am79C971 0x2623 224 #define Am79C972 0x2624 225 #define Am79C973 0x2625 226 #define Am79C978 0x2626 227 #define Am79C975 0x2627 228 #define Am79C976 0x2628 229 230 /* 231 * Advanced feature control (CSR122) 232 */ 233 #define PCN_AFC_RXALIGN 0x0001 234 235 /* 236 * BCR (bus control) registers 237 */ 238 #define PCN_BCR_MMRA 0x00 /* Master Mode Read Active */ 239 #define PCN_BCR_MMW 0x01 /* Master Mode Write Active */ 240 #define PCN_BCR_MISCCFG 0x02 241 #define PCN_BCR_LED0 0x04 242 #define PCN_BCR_LED1 0x05 243 #define PCN_BCR_LED2 0x06 244 #define PCN_BCR_LED3 0x07 245 #define PCN_BCR_DUPLEX 0x09 246 #define PCN_BCR_BUSCTL 0x12 247 #define PCN_BCR_EECTL 0x13 248 #define PCN_BCR_SSTYLE 0x14 249 #define PCN_BCR_PCILAT 0x16 250 #define PCN_BCR_PCISUBVENID 0x17 251 #define PCN_BCR_PCISUBSYSID 0x18 252 #define PCN_BCR_SRAMSIZE 0x19 253 #define PCN_BCR_SRAMBOUND 0x1A 254 #define PCN_BCR_SRAMCTL 0x1B 255 #define PCN_BCR_MIICTL 0x20 256 #define PCN_BCR_MIIADDR 0x21 257 #define PCN_BCR_MIIDATA 0x22 258 #define PCN_BCR_PCIVENID 0x23 259 #define PCN_BCR_PCIPCAP 0x24 260 #define PCN_BCR_DATA0 0x25 261 #define PCN_BCR_DATA1 0x26 262 #define PCN_BCR_DATA2 0x27 263 #define PCN_BCR_DATA3 0x28 264 #define PCN_BCR_DATA4 0x29 265 #define PCN_BCR_DATA5 0x2A 266 #define PCN_BCR_DATA6 0x2B 267 #define PCN_BCR_DATA7 0x2C 268 #define PCN_BCR_ONNOWPAT0 0x2D 269 #define PCN_BCR_ONNOWPAT1 0x2E 270 #define PCN_BCR_ONNOWPAT2 0x2F 271 #define PCN_BCR_PHYSEL 0x31 272 273 /* 274 * Miscellaneous Configuration (BCR2) 275 */ 276 #define PCN_MISC_TMAULOOP 1<<14 /* T-MAU Loopback packet enable. */ 277 #define PCN_MISC_LEDPE 1<<12 /* LED Program Enable */ 278 #define PCN_MISC_APROMWE 1<<8 /* Address PROM Write Enable */ 279 #define PCN_MISC_INTLEVEL 1<<7 /* Interrupt level */ 280 #define PCN_MISC_EADISEL 1<<3 /* EADI Select */ 281 #define PCN_MISC_AWAKE 1<<2 /* Power saving mode select */ 282 #define PCN_MISC_ASEL 1<<1 /* Auto Select */ 283 #define PCN_MISC_XMAUSEL 1<<0 /* Reserved. */ 284 285 /* 286 * Full duplex control (BCR9) 287 */ 288 #define PCN_DUPLEX_FDEN 0x0001 /* Full-duplex enable */ 289 #define PCN_DUPLEX_AUI 0x0002 /* AUI full-duplex */ 290 #define PCN_DUPLEX_FDRPAD 0x0004 /* Full-duplex runt pkt accept dis. */ 291 292 /* 293 * Burst and bus control register (BCR18) 294 */ 295 #define PCN_BUSCTL_BWRITE 0x0020 296 #define PCN_BUSCTL_BREAD 0x0040 297 #define PCN_BUSCTL_DWIO 0x0080 298 #define PCN_BUSCTL_EXTREQ 0x0100 299 #define PCN_BUSCTL_MEMCMD 0x0200 300 #define PCN_BUSCTL_NOUFLOW 0x0800 301 #define PCN_BUSCTL_ROMTMG 0xF000 302 303 /* 304 * EEPROM control (BCR19) 305 */ 306 #define PCN_EECTL_EDATA 0x0001 307 #define PCN_EECTL_ECLK 0x0002 308 #define PCN_EECTL_EECS 0x0004 309 #define PCN_EECTL_EEN 0x0100 310 #define PCN_EECTL_EEDET 0x2000 311 #define PCN_EECTL_PREAD 0x4000 312 #define PCN_EECTL_PVALID 0x8000 313 314 /* 315 * Software style (BCR20) 316 */ 317 #define PCN_SSTYLE_APERREN 0x0400 /* advanced parity error checking */ 318 #define PCN_SSTYLE_SSIZE32 0x0100 319 #define PCN_SSTYLE_SWSTYLE 0x00FF 320 321 #define PCN_SWSTYLE_LANCE 0x0000 322 #define PCN_SWSTYLE_PCNETPCI 0x0102 323 #define PCN_SWSTYLE_PCNETPCI_BURST 0x0103 324 325 /* 326 * MII control and status (BCR32) 327 */ 328 #define PCN_MIICTL_MIILP 0x0002 /* MII internal loopback */ 329 #define PCN_MIICTL_XPHYSP 0x0008 /* external PHY speed */ 330 #define PCN_MIICTL_XPHYFD 0x0010 /* external PHY full duplex */ 331 #define PCN_MIICTL_XPHYANE 0x0020 /* external phy auto-neg enable */ 332 #define PCN_MIICTL_XPHYRST 0x0040 /* external PHY reset */ 333 #define PCN_MIICTL_DANAS 0x0080 /* disable auto-neg auto-setup */ 334 #define PCN_MIICTL_APDW 0x0700 /* auto-poll dwell time */ 335 #define PCN_MIICTL_APEP 0x0100 /* auto-poll external PHY */ 336 #define PCN_MIICTL_FMDC 0x3000 /* data clock speed */ 337 #define PCN_MIICTL_MIIPD 0x4000 /* PHY detect */ 338 #define PCN_MIICTL_ANTST 0x8000 /* Manufacturing test */ 339 340 /* 341 * MII address register (BCR33) 342 */ 343 #define PCN_MIIADDR_REGAD 0x001F 344 #define PCN_MIIADDR_PHYAD 0x03E0 345 346 /* addresses of internal PHYs */ 347 #define PCN_PHYAD_100BTX 30 348 #define PCN_PHYAD_10BT 31 349 350 /* 351 * MII data register (BCR34) 352 */ 353 #define PCN_MIIDATA_MIIMD 0xFFFF 354 355 /* 356 * PHY selection (BCR49) (HomePNA NIC only) 357 */ 358 #define PCN_PHYSEL_PHYSEL 0x0003 359 #define PCN_PHYSEL_DEFAULT 0x0300 360 #define PCN_PHYSEL_PCNET 0x8000 361 362 #define PCN_PHY_10BT 0x0000 363 #define PCN_PHY_HOMEPNA 0x0001 364 #define PCN_PHY_EXTERNAL 0x0002 365 366 struct pcn_rx_desc { 367 u_int16_t pcn_rxlen; 368 u_int16_t pcn_rsvd0; 369 u_int16_t pcn_bufsz; 370 u_int16_t pcn_rxstat; 371 u_int32_t pcn_rbaddr; 372 u_int32_t pcn_uspace; 373 }; 374 375 #define PCN_RXSTAT_BPE 0x0080 /* bus parity error */ 376 #define PCN_RXSTAT_ENP 0x0100 /* end of packet */ 377 #define PCN_RXSTAT_STP 0x0200 /* start of packet */ 378 #define PCN_RXSTAT_BUFF 0x0400 /* buffer error */ 379 #define PCN_RXSTAT_CRC 0x0800 /* CRC error */ 380 #define PCN_RXSTAT_OFLOW 0x1000 /* rx overrun */ 381 #define PCN_RXSTAT_FRAM 0x2000 /* framing error */ 382 #define PCN_RXSTAT_ERR 0x4000 /* error summary */ 383 #define PCN_RXSTAT_OWN 0x8000 384 385 #define PCN_RXLEN_MBO 0xF000 386 #define PCN_RXLEN_BUFSZ 0x0FFF 387 388 #define PCN_OWN_RXDESC(x) (((x)->pcn_rxstat & PCN_RXSTAT_OWN) == 0) 389 390 struct pcn_tx_desc { 391 u_int32_t pcn_txstat; 392 u_int32_t pcn_txctl; 393 u_int32_t pcn_tbaddr; 394 u_int32_t pcn_uspace; 395 }; 396 397 #define PCN_TXSTAT_TRC 0x0000000F /* transmit retries */ 398 #define PCN_TXSTAT_RTRY 0x04000000 /* retry */ 399 #define PCN_TXSTAT_LCAR 0x08000000 /* lost carrier */ 400 #define PCN_TXSTAT_LCOL 0x10000000 /* late collision */ 401 #define PCN_TXSTAT_EXDEF 0x20000000 /* excessive deferrals */ 402 #define PCN_TXSTAT_UFLOW 0x40000000 /* transmit underrun */ 403 #define PCN_TXSTAT_BUFF 0x80000000 /* buffer error */ 404 405 #define PCN_TXCTL_OWN 0x80000000 406 #define PCN_TXCTL_ERR 0x40000000 /* error summary */ 407 #define PCN_TXCTL_ADD_FCS 0x20000000 /* add FCS to pkt */ 408 #define PCN_TXCTL_MORE_LTINT 0x10000000 409 #define PCN_TXCTL_ONE 0x08000000 410 #define PCN_TXCTL_DEF 0x04000000 411 #define PCN_TXCTL_STP 0x02000000 412 #define PCN_TXCTL_ENP 0x01000000 413 #define PCN_TXCTL_BPE 0x00800000 414 #define PCN_TXCTL_MBO 0x0000F000 415 #define PCN_TXCTL_BUFSZ 0x00000FFF 416 417 #define PCN_OWN_TXDESC(x) (((x)->pcn_txctl & PCN_TXCTL_OWN) == 0) 418 419 #define PCN_RX_LIST_CNT 64 420 #define PCN_TX_LIST_CNT 256 421 422 struct pcn_list_data { 423 struct pcn_rx_desc pcn_rx_list[PCN_RX_LIST_CNT]; 424 struct pcn_tx_desc pcn_tx_list[PCN_TX_LIST_CNT]; 425 }; 426 427 struct pcn_ring_data { 428 struct mbuf *pcn_rx_chain[PCN_RX_LIST_CNT]; 429 struct mbuf *pcn_tx_chain[PCN_TX_LIST_CNT]; 430 int pcn_rx_prod; 431 int pcn_tx_prod; 432 int pcn_tx_cons; 433 int pcn_tx_cnt; 434 }; 435 436 /* 437 * AMD PCI vendor ID. 438 */ 439 #define PCN_VENDORID 0x1022 440 441 /* 442 * AMD PCnet/PCI device IDs 443 */ 444 #define PCN_DEVICEID_PCNET 0x2000 445 #define PCN_DEVICEID_HOME 0x2001 446 447 struct pcn_type { 448 u_int16_t pcn_vid; 449 u_int16_t pcn_did; 450 const char *pcn_name; 451 }; 452 453 struct pcn_softc { 454 struct ifnet *pcn_ifp; 455 bus_space_handle_t pcn_bhandle; 456 bus_space_tag_t pcn_btag; 457 struct resource *pcn_res; 458 struct resource *pcn_irq; 459 void *pcn_intrhand; 460 device_t pcn_miibus; 461 u_int8_t pcn_link; 462 int8_t pcn_extphyaddr; 463 int8_t pcn_inst_10bt; 464 int pcn_if_flags; 465 int pcn_type; 466 struct pcn_list_data *pcn_ldata; 467 struct pcn_ring_data pcn_cdata; 468 struct callout pcn_stat_callout; 469 struct mtx pcn_mtx; 470 int pcn_timer; 471 }; 472 473 #define PCN_LOCK(_sc) mtx_lock(&(_sc)->pcn_mtx) 474 #define PCN_UNLOCK(_sc) mtx_unlock(&(_sc)->pcn_mtx) 475 #define PCN_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->pcn_mtx, MA_OWNED) 476 477 /* 478 * register space access macros 479 */ 480 #define CSR_WRITE_4(sc, reg, val) \ 481 bus_space_write_4(sc->pcn_btag, sc->pcn_bhandle, reg, val) 482 483 #define CSR_READ_4(sc, reg) \ 484 bus_space_read_4(sc->pcn_btag, sc->pcn_bhandle, reg) 485 486 #define CSR_WRITE_2(sc, reg, val) \ 487 bus_space_write_2(sc->pcn_btag, sc->pcn_bhandle, reg, val) 488 489 #define CSR_READ_2(sc, reg) \ 490 bus_space_read_2(sc->pcn_btag, sc->pcn_bhandle, reg) 491 492 #define PCN_TIMEOUT 1000 493 #define ETHER_ALIGN 2 494 #define PCN_RXLEN 1536 495 #define PCN_MIN_FRAMELEN 60 496 #define PCN_INC(x, y) (x) = (x + 1) % y 497 /* 498 * PCI low memory base and low I/O base register, and 499 * other PCI registers. 500 */ 501 502 #define PCN_PCI_VENDOR_ID 0x00 503 #define PCN_PCI_DEVICE_ID 0x02 504 #define PCN_PCI_COMMAND 0x04 505 #define PCN_PCI_STATUS 0x06 506 #define PCN_PCI_REVID 0x08 507 #define PCN_PCI_CLASSCODE 0x09 508 #define PCN_PCI_CACHELEN 0x0C 509 #define PCN_PCI_LATENCY_TIMER 0x0D 510 #define PCN_PCI_HEADER_TYPE 0x0E 511 #define PCN_PCI_LOIO 0x10 512 #define PCN_PCI_LOMEM 0x14 513 #define PCN_PCI_BIOSROM 0x30 514 #define PCN_PCI_INTLINE 0x3C 515 #define PCN_PCI_INTPIN 0x3D 516 #define PCN_PCI_MINGNT 0x3E 517 #define PCN_PCI_MINLAT 0x3F 518 #define PCN_PCI_RESETOPT 0x48 519 #define PCN_PCI_EEPROM_DATA 0x4C 520 521 /* power management registers */ 522 #define PCN_PCI_CAPID 0x50 /* 8 bits */ 523 #define PCN_PCI_NEXTPTR 0x51 /* 8 bits */ 524 #define PCN_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 525 #define PCN_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 526 527 #define PCN_PSTATE_MASK 0x0003 528 #define PCN_PSTATE_D0 0x0000 529 #define PCN_PSTATE_D1 0x0001 530 #define PCN_PSTATE_D2 0x0002 531 #define PCN_PSTATE_D3 0x0003 532 #define PCN_PME_EN 0x0010 533 #define PCN_PME_STATUS 0x8000 534