1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright 1997, Stefan Esser <[email protected]>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
11 * disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 *
29 */
30
31 #ifndef _PCIVAR_H_
32 #define _PCIVAR_H_
33
34 #include <sys/queue.h>
35 #include <sys/_eventhandler.h>
36
37 /* some PCI bus constants */
38 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
39 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
40 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
41
42 typedef uint64_t pci_addr_t;
43
44 /* Config registers for PCI-PCI and PCI-Cardbus bridges. */
45 struct pcicfg_bridge {
46 uint8_t br_seclat;
47 uint8_t br_subbus;
48 uint8_t br_secbus;
49 uint8_t br_pribus;
50 uint16_t br_control;
51 };
52
53 /* Interesting values for PCI power management */
54 struct pcicfg_pp {
55 uint16_t pp_cap; /* PCI power management capabilities */
56 uint8_t pp_status; /* conf. space addr. of PM control/status reg */
57 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */
58 uint8_t pp_data; /* conf. space addr. of PM data reg */
59 };
60
61 struct pci_map {
62 pci_addr_t pm_value; /* Raw BAR value */
63 pci_addr_t pm_size;
64 uint16_t pm_reg;
65 STAILQ_ENTRY(pci_map) pm_link;
66 };
67
68 struct vpd_readonly {
69 char keyword[2];
70 char *value;
71 int len;
72 };
73
74 struct vpd_write {
75 char keyword[2];
76 char *value;
77 int start;
78 int len;
79 };
80
81 struct pcicfg_vpd {
82 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
83 char vpd_cached;
84 char *vpd_ident; /* string identifier */
85 int vpd_rocnt;
86 struct vpd_readonly *vpd_ros;
87 int vpd_wcnt;
88 struct vpd_write *vpd_w;
89 };
90
91 /* Interesting values for PCI MSI */
92 struct pcicfg_msi {
93 uint16_t msi_ctrl; /* Message Control */
94 uint8_t msi_location; /* Offset of MSI capability registers. */
95 uint8_t msi_msgnum; /* Number of messages */
96 int msi_alloc; /* Number of allocated messages. */
97 uint64_t msi_addr; /* Contents of address register. */
98 uint16_t msi_data; /* Contents of data register. */
99 u_int msi_handlers;
100 };
101
102 /* Interesting values for PCI MSI-X */
103 struct msix_vector {
104 uint64_t mv_address; /* Contents of address register. */
105 uint32_t mv_data; /* Contents of data register. */
106 int mv_irq;
107 };
108
109 struct msix_table_entry {
110 u_int mte_vector; /* 1-based index into msix_vectors array. */
111 u_int mte_handlers;
112 };
113
114 struct pcicfg_msix {
115 uint16_t msix_ctrl; /* Message Control */
116 uint16_t msix_msgnum; /* Number of messages */
117 uint8_t msix_location; /* Offset of MSI-X capability registers. */
118 uint8_t msix_table_bar; /* BAR containing vector table. */
119 uint8_t msix_pba_bar; /* BAR containing PBA. */
120 uint32_t msix_table_offset;
121 uint32_t msix_pba_offset;
122 int msix_alloc; /* Number of allocated vectors. */
123 int msix_table_len; /* Length of virtual table. */
124 struct msix_table_entry *msix_table; /* Virtual table. */
125 struct msix_vector *msix_vectors; /* Array of allocated vectors. */
126 struct resource *msix_table_res; /* Resource containing vector table. */
127 struct resource *msix_pba_res; /* Resource containing PBA. */
128 };
129
130 /* Interesting values for HyperTransport */
131 struct pcicfg_ht {
132 uint8_t ht_slave; /* Non-zero if device is an HT slave. */
133 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */
134 uint16_t ht_msictrl; /* MSI mapping control */
135 uint64_t ht_msiaddr; /* MSI mapping base address */
136 };
137
138 /* Interesting values for PCI-express */
139 struct pcicfg_pcie {
140 uint8_t pcie_location; /* Offset of PCI-e capability registers. */
141 uint8_t pcie_type; /* Device type. */
142 uint16_t pcie_flags; /* Device capabilities register. */
143 uint16_t pcie_device_ctl; /* Device control register. */
144 uint16_t pcie_link_ctl; /* Link control register. */
145 uint16_t pcie_slot_ctl; /* Slot control register. */
146 uint16_t pcie_root_ctl; /* Root control register. */
147 uint16_t pcie_device_ctl2; /* Second device control register. */
148 uint16_t pcie_link_ctl2; /* Second link control register. */
149 uint16_t pcie_slot_ctl2; /* Second slot control register. */
150 };
151
152 struct pcicfg_pcix {
153 uint16_t pcix_command;
154 uint8_t pcix_location; /* Offset of PCI-X capability registers. */
155 };
156
157 struct pcicfg_vf {
158 int index;
159 };
160
161 struct pci_ea_entry {
162 int eae_bei;
163 uint32_t eae_flags;
164 uint64_t eae_base;
165 uint64_t eae_max_offset;
166 uint32_t eae_cfg_offset;
167 STAILQ_ENTRY(pci_ea_entry) eae_link;
168 };
169
170 struct pcicfg_ea {
171 int ea_location; /* Structure offset in Configuration Header */
172 STAILQ_HEAD(, pci_ea_entry) ea_entries; /* EA entries */
173 };
174
175 #define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */
176
177 /* config header information common to all header types */
178 typedef struct pcicfg {
179 device_t dev; /* device which owns this */
180
181 STAILQ_HEAD(, pci_map) maps; /* BARs */
182
183 uint16_t subvendor; /* card vendor ID */
184 uint16_t subdevice; /* card device ID, assigned by card vendor */
185 uint16_t vendor; /* chip vendor ID */
186 uint16_t device; /* chip device ID, assigned by chip vendor */
187
188 uint16_t cmdreg; /* disable/enable chip and PCI options */
189 uint16_t statreg; /* supported PCI features and error state */
190
191 uint8_t baseclass; /* chip PCI class */
192 uint8_t subclass; /* chip PCI subclass */
193 uint8_t progif; /* chip PCI programming interface */
194 uint8_t revid; /* chip revision ID */
195
196 uint8_t hdrtype; /* chip config header type */
197 uint8_t cachelnsz; /* cache line size in 4byte units */
198 uint8_t intpin; /* PCI interrupt pin */
199 uint8_t intline; /* interrupt line (IRQ for PC arch) */
200
201 uint8_t mingnt; /* min. useful bus grant time in 250ns units */
202 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
203 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
204
205 uint8_t mfdev; /* multi-function device (from hdrtype reg) */
206 uint8_t nummaps; /* actual number of PCI maps used */
207
208 uint32_t domain; /* PCI domain */
209 uint8_t bus; /* config space bus address */
210 uint8_t slot; /* config space slot address */
211 uint8_t func; /* config space function number */
212
213 uint32_t flags; /* flags defined above */
214
215 struct pcicfg_bridge bridge; /* Bridges */
216 struct pcicfg_pp pp; /* Power management */
217 struct pcicfg_vpd vpd; /* Vital product data */
218 struct pcicfg_msi msi; /* PCI MSI */
219 struct pcicfg_msix msix; /* PCI MSI-X */
220 struct pcicfg_ht ht; /* HyperTransport */
221 struct pcicfg_pcie pcie; /* PCI Express */
222 struct pcicfg_pcix pcix; /* PCI-X */
223 struct pcicfg_iov *iov; /* SR-IOV */
224 struct pcicfg_vf vf; /* SR-IOV Virtual Function */
225 struct pcicfg_ea ea; /* Enhanced Allocation */
226 } pcicfgregs;
227
228 /* additional type 1 device config header information (PCI to PCI bridge) */
229
230 typedef struct {
231 pci_addr_t pmembase; /* base address of prefetchable memory */
232 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
233 uint32_t membase; /* base address of memory window */
234 uint32_t memlimit; /* topmost address of memory window */
235 uint32_t iobase; /* base address of port window */
236 uint32_t iolimit; /* topmost address of port window */
237 uint16_t secstat; /* secondary bus status register */
238 uint16_t bridgectl; /* bridge control register */
239 uint8_t seclat; /* CardBus latency timer */
240 } pcih1cfgregs;
241
242 /* additional type 2 device config header information (CardBus bridge) */
243
244 typedef struct {
245 uint32_t membase0; /* base address of memory window */
246 uint32_t memlimit0; /* topmost address of memory window */
247 uint32_t membase1; /* base address of memory window */
248 uint32_t memlimit1; /* topmost address of memory window */
249 uint32_t iobase0; /* base address of port window */
250 uint32_t iolimit0; /* topmost address of port window */
251 uint32_t iobase1; /* base address of port window */
252 uint32_t iolimit1; /* topmost address of port window */
253 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
254 uint16_t secstat; /* secondary bus status register */
255 uint16_t bridgectl; /* bridge control register */
256 uint8_t seclat; /* CardBus latency timer */
257 } pcih2cfgregs;
258
259 extern uint32_t pci_numdevs;
260 extern int pci_enable_aspm;
261
262 /*
263 * The bitfield has to be stable and match the fields below (so that
264 * match_flag_vendor must be bit 0) so we have to do the endian dance. We can't
265 * use enums or #define constants because then the macros for subsetting matches
266 * wouldn't work. These tables are parsed by devmatch and others to connect
267 * modules with devices on the PCI bus.
268 */
269 struct pci_device_table {
270 #if BYTE_ORDER == LITTLE_ENDIAN
271 uint16_t
272 match_flag_vendor:1,
273 match_flag_device:1,
274 match_flag_subvendor:1,
275 match_flag_subdevice:1,
276 match_flag_class:1,
277 match_flag_subclass:1,
278 match_flag_revid:1,
279 match_flag_unused:9;
280 #else
281 uint16_t
282 match_flag_unused:9,
283 match_flag_revid:1,
284 match_flag_subclass:1,
285 match_flag_class:1,
286 match_flag_subdevice:1,
287 match_flag_subvendor:1,
288 match_flag_device:1,
289 match_flag_vendor:1;
290 #endif
291 uint16_t vendor;
292 uint16_t device;
293 uint16_t subvendor;
294 uint16_t subdevice;
295 uint16_t class_id;
296 uint16_t subclass;
297 uint16_t revid;
298 uint16_t unused;
299 uintptr_t driver_data;
300 char *descr;
301 };
302
303 #define PCI_DEV(v, d) \
304 .match_flag_vendor = 1, .vendor = (v), \
305 .match_flag_device = 1, .device = (d)
306 #define PCI_SUBDEV(sv, sd) \
307 .match_flag_subvendor = 1, .subvendor = (sv), \
308 .match_flag_subdevice = 1, .subdevice = (sd)
309 #define PCI_CLASS(x) \
310 .match_flag_class = 1, .class_id = (x)
311 #define PCI_SUBCLASS(x) \
312 .match_flag_subclass = 1, .subclass = (x)
313 #define PCI_REVID(x) \
314 .match_flag_revid = 1, .revid = (x)
315 #define PCI_DESCR(x) \
316 .descr = (x)
317 #define PCI_PNP_STR \
318 "M16:mask;U16:vendor;U16:device;U16:subvendor;U16:subdevice;" \
319 "U16:class;U16:subclass;U16:revid;"
320 #define PCI_PNP_INFO(table) \
321 MODULE_PNP_INFO(PCI_PNP_STR, pci, table, table, \
322 sizeof(table) / sizeof(table[0]))
323
324 const struct pci_device_table *pci_match_device(device_t child,
325 const struct pci_device_table *id, size_t nelt);
326 #define PCI_MATCH(child, table) \
327 pci_match_device(child, (table), nitems(table));
328
329 /* Only if the prerequisites are present */
330 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
331 struct pci_devinfo {
332 STAILQ_ENTRY(pci_devinfo) pci_links;
333 struct resource_list resources;
334 pcicfgregs cfg;
335 struct pci_conf conf;
336 };
337 #endif
338
339 #ifdef _SYS_BUS_H_
340
341 #include "pci_if.h"
342
343 enum pci_device_ivars {
344 PCI_IVAR_SUBVENDOR,
345 PCI_IVAR_SUBDEVICE,
346 PCI_IVAR_VENDOR,
347 PCI_IVAR_DEVICE,
348 PCI_IVAR_DEVID,
349 PCI_IVAR_CLASS,
350 PCI_IVAR_SUBCLASS,
351 PCI_IVAR_PROGIF,
352 PCI_IVAR_REVID,
353 PCI_IVAR_INTPIN,
354 PCI_IVAR_IRQ,
355 PCI_IVAR_DOMAIN,
356 PCI_IVAR_BUS,
357 PCI_IVAR_SLOT,
358 PCI_IVAR_FUNCTION,
359 PCI_IVAR_ETHADDR,
360 PCI_IVAR_CMDREG,
361 PCI_IVAR_CACHELNSZ,
362 PCI_IVAR_MINGNT,
363 PCI_IVAR_MAXLAT,
364 PCI_IVAR_LATTIMER
365 };
366
367 /*
368 * Simplified accessors for pci devices
369 */
370 #define PCI_ACCESSOR(var, ivar, type) \
371 __BUS_ACCESSOR(pci, var, PCI, ivar, type)
372
PCI_ACCESSOR(subvendor,SUBVENDOR,uint16_t)373 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
374 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
375 PCI_ACCESSOR(vendor, VENDOR, uint16_t)
376 PCI_ACCESSOR(device, DEVICE, uint16_t)
377 PCI_ACCESSOR(devid, DEVID, uint32_t)
378 PCI_ACCESSOR(class, CLASS, uint8_t)
379 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
380 PCI_ACCESSOR(progif, PROGIF, uint8_t)
381 PCI_ACCESSOR(revid, REVID, uint8_t)
382 PCI_ACCESSOR(intpin, INTPIN, uint8_t)
383 PCI_ACCESSOR(irq, IRQ, uint8_t)
384 PCI_ACCESSOR(domain, DOMAIN, uint32_t)
385 PCI_ACCESSOR(bus, BUS, uint8_t)
386 PCI_ACCESSOR(slot, SLOT, uint8_t)
387 PCI_ACCESSOR(function, FUNCTION, uint8_t)
388 PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
389 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t)
390 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t)
391 PCI_ACCESSOR(mingnt, MINGNT, uint8_t)
392 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t)
393 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t)
394
395 #undef PCI_ACCESSOR
396
397 /*
398 * Operations on configuration space.
399 */
400 static __inline uint32_t
401 pci_read_config(device_t dev, int reg, int width)
402 {
403 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
404 }
405
406 static __inline void
pci_write_config(device_t dev,int reg,uint32_t val,int width)407 pci_write_config(device_t dev, int reg, uint32_t val, int width)
408 {
409 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
410 }
411
412 /*
413 * Ivars for pci bridges.
414 */
415
416 /*typedef enum pci_device_ivars pcib_device_ivars;*/
417 enum pcib_device_ivars {
418 PCIB_IVAR_DOMAIN,
419 PCIB_IVAR_BUS
420 };
421
422 #define PCIB_ACCESSOR(var, ivar, type) \
423 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
424
PCIB_ACCESSOR(domain,DOMAIN,uint32_t)425 PCIB_ACCESSOR(domain, DOMAIN, uint32_t)
426 PCIB_ACCESSOR(bus, BUS, uint32_t)
427
428 #undef PCIB_ACCESSOR
429
430 /*
431 * PCI interrupt validation. Invalid interrupt values such as 0 or 128
432 * on i386 or other platforms should be mapped out in the MD pcireadconf
433 * code and not here, since the only MI invalid IRQ is 255.
434 */
435 #define PCI_INVALID_IRQ 255
436 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
437
438 /*
439 * Convenience functions.
440 *
441 * These should be used in preference to manually manipulating
442 * configuration space.
443 */
444 static __inline int
445 pci_enable_busmaster(device_t dev)
446 {
447 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
448 }
449
450 static __inline int
pci_disable_busmaster(device_t dev)451 pci_disable_busmaster(device_t dev)
452 {
453 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
454 }
455
456 static __inline int
pci_enable_io(device_t dev,int space)457 pci_enable_io(device_t dev, int space)
458 {
459 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
460 }
461
462 static __inline int
pci_disable_io(device_t dev,int space)463 pci_disable_io(device_t dev, int space)
464 {
465 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
466 }
467
468 static __inline int
pci_get_vpd_ident(device_t dev,const char ** identptr)469 pci_get_vpd_ident(device_t dev, const char **identptr)
470 {
471 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
472 }
473
474 static __inline int
pci_get_vpd_readonly(device_t dev,const char * kw,const char ** vptr)475 pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr)
476 {
477 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr));
478 }
479
480 /*
481 * Check if the address range falls within the VGA defined address range(s)
482 */
483 static __inline int
pci_is_vga_ioport_range(rman_res_t start,rman_res_t end)484 pci_is_vga_ioport_range(rman_res_t start, rman_res_t end)
485 {
486
487 return (((start >= 0x3b0 && end <= 0x3bb) ||
488 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
489 }
490
491 static __inline int
pci_is_vga_memory_range(rman_res_t start,rman_res_t end)492 pci_is_vga_memory_range(rman_res_t start, rman_res_t end)
493 {
494
495 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
496 }
497
498 /*
499 * PCI power states are as defined by ACPI:
500 *
501 * D0 State in which device is on and running. It is receiving full
502 * power from the system and delivering full functionality to the user.
503 * D1 Class-specific low-power state in which device context may or may not
504 * be lost. Buses in D1 cannot do anything to the bus that would force
505 * devices on that bus to lose context.
506 * D2 Class-specific low-power state in which device context may or may
507 * not be lost. Attains greater power savings than D1. Buses in D2
508 * can cause devices on that bus to lose some context. Devices in D2
509 * must be prepared for the bus to be in D2 or higher.
510 * D3 State in which the device is off and not running. Device context is
511 * lost. Power can be removed from the device.
512 */
513 #define PCI_POWERSTATE_D0 0
514 #define PCI_POWERSTATE_D1 1
515 #define PCI_POWERSTATE_D2 2
516 #define PCI_POWERSTATE_D3 3
517 #define PCI_POWERSTATE_UNKNOWN -1
518
519 static __inline int
pci_set_powerstate(device_t dev,int state)520 pci_set_powerstate(device_t dev, int state)
521 {
522 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
523 }
524
525 static __inline int
pci_get_powerstate(device_t dev)526 pci_get_powerstate(device_t dev)
527 {
528 return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
529 }
530
531 static __inline int
pci_find_cap(device_t dev,int capability,int * capreg)532 pci_find_cap(device_t dev, int capability, int *capreg)
533 {
534 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg));
535 }
536
537 static __inline int
pci_find_next_cap(device_t dev,int capability,int start,int * capreg)538 pci_find_next_cap(device_t dev, int capability, int start, int *capreg)
539 {
540 return (PCI_FIND_NEXT_CAP(device_get_parent(dev), dev, capability, start,
541 capreg));
542 }
543
544 static __inline int
pci_find_extcap(device_t dev,int capability,int * capreg)545 pci_find_extcap(device_t dev, int capability, int *capreg)
546 {
547 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg));
548 }
549
550 static __inline int
pci_find_next_extcap(device_t dev,int capability,int start,int * capreg)551 pci_find_next_extcap(device_t dev, int capability, int start, int *capreg)
552 {
553 return (PCI_FIND_NEXT_EXTCAP(device_get_parent(dev), dev, capability,
554 start, capreg));
555 }
556
557 static __inline int
pci_find_htcap(device_t dev,int capability,int * capreg)558 pci_find_htcap(device_t dev, int capability, int *capreg)
559 {
560 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg));
561 }
562
563 static __inline int
pci_find_next_htcap(device_t dev,int capability,int start,int * capreg)564 pci_find_next_htcap(device_t dev, int capability, int start, int *capreg)
565 {
566 return (PCI_FIND_NEXT_HTCAP(device_get_parent(dev), dev, capability,
567 start, capreg));
568 }
569
570 static __inline int
pci_alloc_msi(device_t dev,int * count)571 pci_alloc_msi(device_t dev, int *count)
572 {
573 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
574 }
575
576 static __inline int
pci_alloc_msix(device_t dev,int * count)577 pci_alloc_msix(device_t dev, int *count)
578 {
579 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
580 }
581
582 static __inline void
pci_enable_msi(device_t dev,uint64_t address,uint16_t data)583 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
584 {
585 PCI_ENABLE_MSI(device_get_parent(dev), dev, address, data);
586 }
587
588 static __inline void
pci_enable_msix(device_t dev,u_int index,uint64_t address,uint32_t data)589 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
590 {
591 PCI_ENABLE_MSIX(device_get_parent(dev), dev, index, address, data);
592 }
593
594 static __inline void
pci_disable_msi(device_t dev)595 pci_disable_msi(device_t dev)
596 {
597 PCI_DISABLE_MSI(device_get_parent(dev), dev);
598 }
599
600 static __inline int
pci_remap_msix(device_t dev,int count,const u_int * vectors)601 pci_remap_msix(device_t dev, int count, const u_int *vectors)
602 {
603 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
604 }
605
606 static __inline int
pci_release_msi(device_t dev)607 pci_release_msi(device_t dev)
608 {
609 return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
610 }
611
612 static __inline int
pci_msi_count(device_t dev)613 pci_msi_count(device_t dev)
614 {
615 return (PCI_MSI_COUNT(device_get_parent(dev), dev));
616 }
617
618 static __inline int
pci_msix_count(device_t dev)619 pci_msix_count(device_t dev)
620 {
621 return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
622 }
623
624 static __inline int
pci_msix_pba_bar(device_t dev)625 pci_msix_pba_bar(device_t dev)
626 {
627 return (PCI_MSIX_PBA_BAR(device_get_parent(dev), dev));
628 }
629
630 static __inline int
pci_msix_table_bar(device_t dev)631 pci_msix_table_bar(device_t dev)
632 {
633 return (PCI_MSIX_TABLE_BAR(device_get_parent(dev), dev));
634 }
635
636 static __inline int
pci_get_id(device_t dev,enum pci_id_type type,uintptr_t * id)637 pci_get_id(device_t dev, enum pci_id_type type, uintptr_t *id)
638 {
639 return (PCI_GET_ID(device_get_parent(dev), dev, type, id));
640 }
641
642 /*
643 * This is the deprecated interface, there is no way to tell the difference
644 * between a failure and a valid value that happens to be the same as the
645 * failure value.
646 */
647 static __inline uint16_t
pci_get_rid(device_t dev)648 pci_get_rid(device_t dev)
649 {
650 uintptr_t rid;
651
652 if (pci_get_id(dev, PCI_ID_RID, &rid) != 0)
653 return (0);
654
655 return (rid);
656 }
657
658 static __inline void
pci_child_added(device_t dev)659 pci_child_added(device_t dev)
660 {
661
662 return (PCI_CHILD_ADDED(device_get_parent(dev), dev));
663 }
664
665 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
666 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
667 device_t pci_find_device(uint16_t, uint16_t);
668 device_t pci_find_class(uint8_t class, uint8_t subclass);
669 device_t pci_find_class_from(uint8_t class, uint8_t subclass, device_t devfrom);
670
671 /* Can be used by drivers to manage the MSI-X table. */
672 int pci_pending_msix(device_t dev, u_int index);
673
674 int pci_msi_device_blacklisted(device_t dev);
675 int pci_msix_device_blacklisted(device_t dev);
676
677 void pci_ht_map_msi(device_t dev, uint64_t addr);
678
679 device_t pci_find_pcie_root_port(device_t dev);
680 int pci_get_relaxed_ordering_enabled(device_t dev);
681 int pci_get_max_payload(device_t dev);
682 int pci_get_max_read_req(device_t dev);
683 void pci_restore_state(device_t dev);
684 void pci_save_state(device_t dev);
685 int pci_set_max_read_req(device_t dev, int size);
686 int pci_power_reset(device_t dev);
687 uint32_t pcie_read_config(device_t dev, int reg, int width);
688 void pcie_write_config(device_t dev, int reg, uint32_t value, int width);
689 uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask,
690 uint32_t value, int width);
691 void pcie_apei_error(device_t dev, int sev, uint8_t *aer);
692 bool pcie_flr(device_t dev, u_int max_delay, bool force);
693 int pcie_get_max_completion_timeout(device_t dev);
694 bool pcie_wait_for_pending_transactions(device_t dev, u_int max_delay);
695 int pcie_link_reset(device_t port, int pcie_location);
696
697 void pci_print_faulted_dev(void);
698
699 #endif /* _SYS_BUS_H_ */
700
701 /*
702 * cdev switch for control device, initialised in generic PCI code
703 */
704 extern struct cdevsw pcicdev;
705
706 /*
707 * List of all PCI devices, generation count for the list.
708 */
709 STAILQ_HEAD(devlist, pci_devinfo);
710
711 extern struct devlist pci_devq;
712 extern uint32_t pci_generation;
713
714 struct pci_map *pci_find_bar(device_t dev, int reg);
715 int pci_bar_enabled(device_t dev, struct pci_map *pm);
716 struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev);
717
718 #define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000
719 #define VGA_PCI_BIOS_SHADOW_SIZE 131072
720
721 int vga_pci_is_boot_display(device_t dev);
722 void * vga_pci_map_bios(device_t dev, size_t *size);
723 void vga_pci_unmap_bios(device_t dev, void *bios);
724 int vga_pci_repost(device_t dev);
725
726 /**
727 * Global eventhandlers invoked when PCI devices are added or removed
728 * from the system.
729 */
730 typedef void (*pci_event_fn)(void *arg, device_t dev);
731 EVENTHANDLER_DECLARE(pci_add_device, pci_event_fn);
732 EVENTHANDLER_DECLARE(pci_delete_device, pci_event_fn);
733
734 #endif /* _PCIVAR_H_ */
735