1 /*-
2 * Copyright (c) 2010 Isilon Systems, Inc.
3 * Copyright (c) 2010 iX Systems, Inc.
4 * Copyright (c) 2010 Panasas, Inc.
5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
6 * All rights reserved.
7 * Copyright (c) 2020-2021 The FreeBSD Foundation
8 *
9 * Portions of this software were developed by Björn Zeeb
10 * under sponsorship from the FreeBSD Foundation.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice unmodified, this list of conditions, and the following
17 * disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD$
34 */
35 #ifndef _LINUXKPI_LINUX_PCI_H_
36 #define _LINUXKPI_LINUX_PCI_H_
37
38 #define CONFIG_PCI_MSI
39
40 #include <linux/types.h>
41
42 #include <sys/param.h>
43 #include <sys/bus.h>
44 #include <sys/module.h>
45 #include <sys/nv.h>
46 #include <sys/pciio.h>
47 #include <sys/rman.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pci_private.h>
51
52 #include <machine/resource.h>
53
54 #include <linux/list.h>
55 #include <linux/dmapool.h>
56 #include <linux/dma-mapping.h>
57 #include <linux/compiler.h>
58 #include <linux/errno.h>
59 #include <asm/atomic.h>
60 #include <linux/device.h>
61 #include <linux/pci_ids.h>
62
63 struct pci_device_id {
64 uint32_t vendor;
65 uint32_t device;
66 uint32_t subvendor;
67 uint32_t subdevice;
68 uint32_t class;
69 uint32_t class_mask;
70 uintptr_t driver_data;
71 };
72
73 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */
74 #define MODULE_DEVICE_TABLE(_bus, _table) \
75 \
76 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \
77 DEVMETHOD_END \
78 }; \
79 \
80 static driver_t _ ## _bus ## _ ## _table ## _driver = { \
81 "lkpi_" #_bus #_table, \
82 _ ## _bus ## _ ## _table ## _methods, \
83 0 \
84 }; \
85 \
86 static devclass_t _ ## _bus ## _ ## _table ## _devclass; \
87 \
88 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\
89 _ ## _bus ## _ ## _table ## _devclass, 0, 0); \
90 \
91 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \
92 _bus, lkpi_ ## _table, _table, nitems(_table) - 1)
93
94 #define PCI_ANY_ID -1U
95
96 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
97 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
98 #define PCI_FUNC(devfn) ((devfn) & 0x07)
99 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff)
100
101 #define PCI_VDEVICE(_vendor, _device) \
102 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \
103 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
104 #define PCI_DEVICE(_vendor, _device) \
105 .vendor = (_vendor), .device = (_device), \
106 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
107
108 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
109
110 #define PCI_VENDOR_ID PCIR_DEVVENDOR
111 #define PCI_COMMAND PCIR_COMMAND
112 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS
113 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */
114 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */
115 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S
116 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1
117 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC
118 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */
119 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD
120 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */
121 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */
122 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */
123 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */
124 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */
125 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */
126 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */
127 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */
128 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */
129 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */
130 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */
131 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */
132 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */
133 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE
134 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */
135 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */
136 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */
137 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */
138 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */
139 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */
140 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */
141 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */
142 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */
143 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */
144 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */
145 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */
146 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */
147 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */
148 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */
149 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */
150 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */
151 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */
152 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */
153 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */
154 #define PCI_EXP_LNKCTL2_TLS 0x000f
155 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
156 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
157 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
158 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
159 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
160 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
161 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
162
163 #define PCI_EXP_LNKCAP_CLKPM 0x00040000
164 #define PCI_EXP_DEVSTA_TRPND 0x0020
165
166 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY)
167 #define IORESOURCE_IO (1 << SYS_RES_IOPORT)
168 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ)
169
170 enum pci_bus_speed {
171 PCI_SPEED_UNKNOWN = -1,
172 PCIE_SPEED_2_5GT,
173 PCIE_SPEED_5_0GT,
174 PCIE_SPEED_8_0GT,
175 PCIE_SPEED_16_0GT,
176 };
177
178 enum pcie_link_width {
179 PCIE_LNK_WIDTH_RESRV = 0x00,
180 PCIE_LNK_X1 = 0x01,
181 PCIE_LNK_X2 = 0x02,
182 PCIE_LNK_X4 = 0x04,
183 PCIE_LNK_X8 = 0x08,
184 PCIE_LNK_X12 = 0x0c,
185 PCIE_LNK_X16 = 0x10,
186 PCIE_LNK_X32 = 0x20,
187 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
188 };
189
190 #define PCIE_LINK_STATE_L0S 0x00000001
191 #define PCIE_LINK_STATE_L1 0x00000002
192 #define PCIE_LINK_STATE_CLKPM 0x00000004
193
194 typedef int pci_power_t;
195
196 #define PCI_D0 PCI_POWERSTATE_D0
197 #define PCI_D1 PCI_POWERSTATE_D1
198 #define PCI_D2 PCI_POWERSTATE_D2
199 #define PCI_D3hot PCI_POWERSTATE_D3
200 #define PCI_D3cold 4
201
202 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN
203
204 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD
205 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID
206
207 #define PCI_EXT_CAP_ID_ERR PCIZ_AER
208 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM
209
210 #define PCI_L1SS_CTL1 0x8
211 #define PCI_L1SS_CTL1_L1SS_MASK 0xf
212
213 #define PCI_IRQ_LEGACY 0x01
214 #define PCI_IRQ_MSI 0x02
215 #define PCI_IRQ_MSIX 0x04
216
217 struct pci_dev;
218
219 struct pci_driver {
220 struct list_head node;
221 char *name;
222 const struct pci_device_id *id_table;
223 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
224 void (*remove)(struct pci_dev *dev);
225 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
226 int (*resume) (struct pci_dev *dev); /* Device woken up */
227 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */
228 driver_t bsddriver;
229 devclass_t bsdclass;
230 struct device_driver driver;
231 const struct pci_error_handlers *err_handler;
232 int bsd_probe_return;
233 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs,
234 const nvlist_t *pf_config);
235 void (*bsd_iov_uninit)(device_t dev);
236 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum,
237 const nvlist_t *vf_config);
238 uintptr_t _spare[8];
239 };
240
241 /*
242 * Pseudo-stable KPI. In 13.0 we neglected to include any spare fields to allow
243 * for growth in struct pci_driver. Those were added in 13.1, but can't be used
244 * until 13.1 is the oldest supported release so that packages built in 13.0
245 * will continue to work on stable/13 and 13.1 release. The 13.0 driver was 92
246 * or 182 bytes on 32 or 64 bit systems (respectively). We added 64 or 32 bytes
247 * of padding, hence the math below (which shouldn't be changed as spare fields
248 * are used up).
249 */
250 #ifdef __LP64__
251 #define __PCI_DRIVER_SIZE (184 + 64)
252 #else
253 #define __PCI_DRIVER_SIZE (92 + 32)
254 #endif
255 _Static_assert(sizeof(struct pci_driver) == __PCI_DRIVER_SIZE,
256 "linuxkpi struct pci_driver: Bad size");
257 #undef __PCI_DRIVER_SIZE
258
259 struct pci_bus {
260 struct pci_dev *self;
261 int domain;
262 int number;
263 };
264
265 extern struct list_head pci_drivers;
266 extern struct list_head pci_devices;
267 extern spinlock_t pci_lock;
268
269 #define __devexit_p(x) x
270
271 #define module_pci_driver(_driver) \
272 \
273 static inline int \
274 _pci_init(void) \
275 { \
276 \
277 return (linux_pci_register_driver(&_driver)); \
278 } \
279 \
280 static inline void \
281 _pci_exit(void) \
282 { \
283 \
284 linux_pci_unregister_driver(&_driver); \
285 } \
286 \
287 module_init(_pci_init); \
288 module_exit(_pci_exit)
289
290 /*
291 * If we find drivers accessing this from multiple KPIs we may have to
292 * refcount objects of this structure.
293 */
294 struct pci_mmio_region {
295 TAILQ_ENTRY(pci_mmio_region) next;
296 struct resource *res;
297 int rid;
298 int type;
299 };
300
301 struct pci_dev {
302 struct device dev;
303 struct list_head links;
304 struct pci_driver *pdrv;
305 struct pci_bus *bus;
306 uint16_t device;
307 uint16_t vendor;
308 uint16_t subsystem_vendor;
309 uint16_t subsystem_device;
310 unsigned int irq;
311 unsigned int devfn;
312 uint32_t class;
313 uint8_t revision;
314 bool msi_enabled;
315
316 TAILQ_HEAD(, pci_mmio_region) mmio;
317
318 /* Add all new items at the end of the list in 13 */
319 struct pci_dev *root;
320 phys_addr_t rom;
321 size_t romlen;
322 bool managed; /* devres "pcim_*(). */
323 bool want_iomap_res;
324 bool msix_enabled;
325 };
326
327 /* XXX add kassert here on the mmio offset */
328
329 /* We need some meta-struct to keep track of these for devres. */
330 struct pci_devres {
331 bool enable_io;
332 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */
333 uint8_t region_mask;
334 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */
335 };
336 struct pcim_iomap_devres {
337 void *mmio_table[PCIR_MAX_BAR_0 + 1];
338 struct resource *res_table[PCIR_MAX_BAR_0 + 1];
339 };
340
341 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name);
342 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv,
343 unsigned int flags);
344
345 /* Internal helper function(s). */
346 struct pci_dev *lkpinew_pci_dev(device_t);
347 struct pci_devres *lkpi_pci_devres_get_alloc(struct pci_dev *pdev);
348 void lkpi_pci_devres_release(struct device *, void *);
349 struct resource *_lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size);
350 struct pcim_iomap_devres *lkpi_pcim_iomap_devres_find(struct pci_dev *pdev);
351 void lkpi_pcim_iomap_table_release(struct device *, void *);
352
353 static inline int
pci_resource_type(struct pci_dev * pdev,int bar)354 pci_resource_type(struct pci_dev *pdev, int bar)
355 {
356 struct pci_map *pm;
357
358 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar));
359 if (!pm)
360 return (-1);
361
362 if (PCI_BAR_IO(pm->pm_value))
363 return (SYS_RES_IOPORT);
364 else
365 return (SYS_RES_MEMORY);
366 }
367
368 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev,
369 struct resource_list *rl, int type, int rid);
370
371 static inline struct resource_list_entry *
linux_pci_get_rle(struct pci_dev * pdev,int type,int rid,bool reserve_bar)372 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar)
373 {
374 struct pci_devinfo *dinfo;
375 struct resource_list *rl;
376 struct resource_list_entry *rle;
377
378 dinfo = device_get_ivars(pdev->dev.bsddev);
379 rl = &dinfo->resources;
380 rle = resource_list_find(rl, type, rid);
381 /* Reserve resources for this BAR if needed. */
382 if (rle == NULL && reserve_bar)
383 rle = linux_pci_reserve_bar(pdev, rl, type, rid);
384 return (rle);
385 }
386
387 static inline struct resource_list_entry *
linux_pci_get_bar(struct pci_dev * pdev,int bar,bool reserve)388 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve)
389 {
390 int type;
391
392 type = pci_resource_type(pdev, bar);
393 if (type < 0)
394 return (NULL);
395 bar = PCIR_BAR(bar);
396 return (linux_pci_get_rle(pdev, type, bar, reserve));
397 }
398
399 static inline struct device *
linux_pci_find_irq_dev(unsigned int irq)400 linux_pci_find_irq_dev(unsigned int irq)
401 {
402 struct pci_dev *pdev;
403 struct device *found;
404
405 found = NULL;
406 spin_lock(&pci_lock);
407 list_for_each_entry(pdev, &pci_devices, links) {
408 if (irq == pdev->dev.irq ||
409 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) {
410 found = &pdev->dev;
411 break;
412 }
413 }
414 spin_unlock(&pci_lock);
415 return (found);
416 }
417
418 /*
419 * All drivers just seem to want to inspect the type not flags.
420 */
421 static inline int
pci_resource_flags(struct pci_dev * pdev,int bar)422 pci_resource_flags(struct pci_dev *pdev, int bar)
423 {
424 int type;
425
426 type = pci_resource_type(pdev, bar);
427 if (type < 0)
428 return (0);
429 return (1 << type);
430 }
431
432 static inline const char *
pci_name(struct pci_dev * d)433 pci_name(struct pci_dev *d)
434 {
435
436 return device_get_desc(d->dev.bsddev);
437 }
438
439 static inline void *
pci_get_drvdata(struct pci_dev * pdev)440 pci_get_drvdata(struct pci_dev *pdev)
441 {
442
443 return dev_get_drvdata(&pdev->dev);
444 }
445
446 static inline void
pci_set_drvdata(struct pci_dev * pdev,void * data)447 pci_set_drvdata(struct pci_dev *pdev, void *data)
448 {
449
450 dev_set_drvdata(&pdev->dev, data);
451 }
452
453 static inline struct pci_dev *
pci_dev_get(struct pci_dev * pdev)454 pci_dev_get(struct pci_dev *pdev)
455 {
456
457 if (pdev != NULL)
458 get_device(&pdev->dev);
459 return (pdev);
460 }
461
462 static __inline void
pci_dev_put(struct pci_dev * pdev)463 pci_dev_put(struct pci_dev *pdev)
464 {
465
466 if (pdev != NULL)
467 put_device(&pdev->dev);
468 }
469
470 static inline int
pci_enable_device(struct pci_dev * pdev)471 pci_enable_device(struct pci_dev *pdev)
472 {
473
474 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT);
475 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY);
476 return (0);
477 }
478
479 static inline void
pci_disable_device(struct pci_dev * pdev)480 pci_disable_device(struct pci_dev *pdev)
481 {
482
483 pci_disable_busmaster(pdev->dev.bsddev);
484 }
485
486 static inline int
pci_set_master(struct pci_dev * pdev)487 pci_set_master(struct pci_dev *pdev)
488 {
489
490 pci_enable_busmaster(pdev->dev.bsddev);
491 return (0);
492 }
493
494 static inline int
pci_set_power_state(struct pci_dev * pdev,int state)495 pci_set_power_state(struct pci_dev *pdev, int state)
496 {
497
498 pci_set_powerstate(pdev->dev.bsddev, state);
499 return (0);
500 }
501
502 static inline int
pci_clear_master(struct pci_dev * pdev)503 pci_clear_master(struct pci_dev *pdev)
504 {
505
506 pci_disable_busmaster(pdev->dev.bsddev);
507 return (0);
508 }
509
510 static inline bool
pci_is_root_bus(struct pci_bus * pbus)511 pci_is_root_bus(struct pci_bus *pbus)
512 {
513
514 return (pbus->self == NULL);
515 }
516
517 static inline struct pci_dev *
pci_upstream_bridge(struct pci_dev * pdev)518 pci_upstream_bridge(struct pci_dev *pdev)
519 {
520
521 if (pci_is_root_bus(pdev->bus))
522 return (NULL);
523
524 /*
525 * If we do not have a (proper) "upstream bridge" set, e.g., we point
526 * to ourselves, try to handle this case on the fly like we do
527 * for pcie_find_root_port().
528 */
529 if (pdev == pdev->bus->self) {
530 device_t bridge;
531
532 bridge = device_get_parent(pdev->dev.bsddev);
533 if (bridge == NULL)
534 goto done;
535 bridge = device_get_parent(bridge);
536 if (bridge == NULL)
537 goto done;
538 if (device_get_devclass(device_get_parent(bridge)) !=
539 devclass_find("pci"))
540 goto done;
541
542 /*
543 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev
544 * for it so it can be returned.
545 */
546 pdev->bus->self = lkpinew_pci_dev(bridge);
547 }
548 done:
549 return (pdev->bus->self);
550 }
551
552 static inline struct pci_devres *
lkpi_pci_devres_find(struct pci_dev * pdev)553 lkpi_pci_devres_find(struct pci_dev *pdev)
554 {
555
556 if (!pdev->managed)
557 return (NULL);
558
559 return (lkpi_pci_devres_get_alloc(pdev));
560 }
561
562 static inline void
pci_release_region(struct pci_dev * pdev,int bar)563 pci_release_region(struct pci_dev *pdev, int bar)
564 {
565 struct resource_list_entry *rle;
566 struct pci_devres *dr;
567 struct pci_mmio_region *mmio, *p;
568
569 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL)
570 return;
571
572 /*
573 * As we implicitly track the requests we also need to clear them on
574 * release. Do clear before resource release.
575 */
576 dr = lkpi_pci_devres_find(pdev);
577 if (dr != NULL) {
578 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d"
579 " region_table res %p != rel->res %p\n", __func__, pdev,
580 bar, dr->region_table[bar], rle->res));
581 dr->region_table[bar] = NULL;
582 dr->region_mask &= ~(1 << bar);
583 }
584
585 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) {
586 if (rle->res != (void *)rman_get_bushandle(mmio->res))
587 continue;
588 TAILQ_REMOVE(&pdev->mmio, mmio, next);
589 free(mmio, M_DEVBUF);
590 }
591
592 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res);
593 }
594
595 static inline void
pci_release_regions(struct pci_dev * pdev)596 pci_release_regions(struct pci_dev *pdev)
597 {
598 int i;
599
600 for (i = 0; i <= PCIR_MAX_BAR_0; i++)
601 pci_release_region(pdev, i);
602 }
603
604 static inline int
pci_request_regions(struct pci_dev * pdev,const char * res_name)605 pci_request_regions(struct pci_dev *pdev, const char *res_name)
606 {
607 int error;
608 int i;
609
610 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
611 error = pci_request_region(pdev, i, res_name);
612 if (error && error != -ENODEV) {
613 pci_release_regions(pdev);
614 return (error);
615 }
616 }
617 return (0);
618 }
619
620 static inline void
lkpi_pci_disable_msix(struct pci_dev * pdev)621 lkpi_pci_disable_msix(struct pci_dev *pdev)
622 {
623
624 pci_release_msi(pdev->dev.bsddev);
625
626 /*
627 * The MSIX IRQ numbers associated with this PCI device are no
628 * longer valid and might be re-assigned. Make sure
629 * linux_pci_find_irq_dev() does no longer see them by
630 * resetting their references to zero:
631 */
632 pdev->dev.irq_start = 0;
633 pdev->dev.irq_end = 0;
634 pdev->msix_enabled = false;
635 }
636 /* Only for consistency. No conflict on that one. */
637 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev)
638
639 static inline void
lkpi_pci_disable_msi(struct pci_dev * pdev)640 lkpi_pci_disable_msi(struct pci_dev *pdev)
641 {
642
643 pci_release_msi(pdev->dev.bsddev);
644
645 pdev->dev.irq_start = 0;
646 pdev->dev.irq_end = 0;
647 pdev->irq = pdev->dev.irq;
648 pdev->msi_enabled = false;
649 }
650 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev)
651 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev)
652
653 unsigned long pci_resource_start(struct pci_dev *pdev, int bar);
654 unsigned long pci_resource_len(struct pci_dev *pdev, int bar);
655
656 static inline bus_addr_t
pci_bus_address(struct pci_dev * pdev,int bar)657 pci_bus_address(struct pci_dev *pdev, int bar)
658 {
659
660 return (pci_resource_start(pdev, bar));
661 }
662
663 #define PCI_CAP_ID_EXP PCIY_EXPRESS
664 #define PCI_CAP_ID_PCIX PCIY_PCIX
665 #define PCI_CAP_ID_AGP PCIY_AGP
666 #define PCI_CAP_ID_PM PCIY_PMG
667
668 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL
669 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
670 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST
671 #define PCI_EXP_LNKCTL PCIER_LINK_CTL
672 #define PCI_EXP_LNKSTA PCIER_LINK_STA
673
674 static inline int
pci_find_capability(struct pci_dev * pdev,int capid)675 pci_find_capability(struct pci_dev *pdev, int capid)
676 {
677 int reg;
678
679 if (pci_find_cap(pdev->dev.bsddev, capid, ®))
680 return (0);
681 return (reg);
682 }
683
pci_pcie_cap(struct pci_dev * dev)684 static inline int pci_pcie_cap(struct pci_dev *dev)
685 {
686 return pci_find_capability(dev, PCI_CAP_ID_EXP);
687 }
688
689 static inline int
pci_find_ext_capability(struct pci_dev * pdev,int capid)690 pci_find_ext_capability(struct pci_dev *pdev, int capid)
691 {
692 int reg;
693
694 if (pci_find_extcap(pdev->dev.bsddev, capid, ®))
695 return (0);
696 return (reg);
697 }
698
699 #define PCIM_PCAP_PME_SHIFT 11
700 static __inline bool
pci_pme_capable(struct pci_dev * pdev,uint32_t flag)701 pci_pme_capable(struct pci_dev *pdev, uint32_t flag)
702 {
703 struct pci_devinfo *dinfo;
704 pcicfgregs *cfg;
705
706 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT))
707 return (false);
708
709 dinfo = device_get_ivars(pdev->dev.bsddev);
710 cfg = &dinfo->cfg;
711
712 if (cfg->pp.pp_cap == 0)
713 return (false);
714
715 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0)
716 return (true);
717
718 return (false);
719 }
720
721 static inline int
pci_disable_link_state(struct pci_dev * pdev,uint32_t flags)722 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags)
723 {
724
725 if (!pci_enable_aspm)
726 return (-EPERM);
727
728 return (-ENXIO);
729 }
730
731 static inline int
pci_read_config_byte(const struct pci_dev * pdev,int where,u8 * val)732 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val)
733 {
734
735 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1);
736 return (0);
737 }
738
739 static inline int
pci_read_config_word(const struct pci_dev * pdev,int where,u16 * val)740 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val)
741 {
742
743 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2);
744 return (0);
745 }
746
747 static inline int
pci_read_config_dword(const struct pci_dev * pdev,int where,u32 * val)748 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val)
749 {
750
751 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4);
752 return (0);
753 }
754
755 static inline int
pci_write_config_byte(const struct pci_dev * pdev,int where,u8 val)756 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val)
757 {
758
759 pci_write_config(pdev->dev.bsddev, where, val, 1);
760 return (0);
761 }
762
763 static inline int
pci_write_config_word(const struct pci_dev * pdev,int where,u16 val)764 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val)
765 {
766
767 pci_write_config(pdev->dev.bsddev, where, val, 2);
768 return (0);
769 }
770
771 static inline int
pci_write_config_dword(const struct pci_dev * pdev,int where,u32 val)772 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val)
773 {
774
775 pci_write_config(pdev->dev.bsddev, where, val, 4);
776 return (0);
777 }
778
779 int linux_pci_register_driver(struct pci_driver *pdrv);
780 int linux_pci_register_drm_driver(struct pci_driver *pdrv);
781 void linux_pci_unregister_driver(struct pci_driver *pdrv);
782 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv);
783
784 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv)
785 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv)
786
787 struct msix_entry {
788 int entry;
789 int vector;
790 };
791
792 /*
793 * Enable msix, positive errors indicate actual number of available
794 * vectors. Negative errors are failures.
795 *
796 * NB: define added to prevent this definition of pci_enable_msix from
797 * clashing with the native FreeBSD version.
798 */
799 #define pci_enable_msix(...) \
800 linux_pci_enable_msix(__VA_ARGS__)
801
802 static inline int
pci_enable_msix(struct pci_dev * pdev,struct msix_entry * entries,int nreq)803 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq)
804 {
805 struct resource_list_entry *rle;
806 int error;
807 int avail;
808 int i;
809
810 avail = pci_msix_count(pdev->dev.bsddev);
811 if (avail < nreq) {
812 if (avail == 0)
813 return -EINVAL;
814 return avail;
815 }
816 avail = nreq;
817 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0)
818 return error;
819 /*
820 * Handle case where "pci_alloc_msix()" may allocate less
821 * interrupts than available and return with no error:
822 */
823 if (avail < nreq) {
824 pci_release_msi(pdev->dev.bsddev);
825 return avail;
826 }
827 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false);
828 pdev->dev.irq_start = rle->start;
829 pdev->dev.irq_end = rle->start + avail;
830 for (i = 0; i < nreq; i++)
831 entries[i].vector = pdev->dev.irq_start + i;
832 pdev->msix_enabled = true;
833 return (0);
834 }
835
836 #define pci_enable_msix_range(...) \
837 linux_pci_enable_msix_range(__VA_ARGS__)
838
839 static inline int
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)840 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
841 int minvec, int maxvec)
842 {
843 int nvec = maxvec;
844 int rc;
845
846 if (maxvec < minvec)
847 return (-ERANGE);
848
849 do {
850 rc = pci_enable_msix(dev, entries, nvec);
851 if (rc < 0) {
852 return (rc);
853 } else if (rc > 0) {
854 if (rc < minvec)
855 return (-ENOSPC);
856 nvec = rc;
857 }
858 } while (rc);
859 return (nvec);
860 }
861
862 #define pci_enable_msi(pdev) \
863 linux_pci_enable_msi(pdev)
864
865 static inline int
pci_enable_msi(struct pci_dev * pdev)866 pci_enable_msi(struct pci_dev *pdev)
867 {
868 struct resource_list_entry *rle;
869 int error;
870 int avail;
871
872 avail = pci_msi_count(pdev->dev.bsddev);
873 if (avail < 1)
874 return -EINVAL;
875
876 avail = 1; /* this function only enable one MSI IRQ */
877 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0)
878 return error;
879
880 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false);
881 pdev->dev.irq_start = rle->start;
882 pdev->dev.irq_end = rle->start + avail;
883 pdev->irq = rle->start;
884 pdev->msi_enabled = true;
885 return (0);
886 }
887
888 static inline int
pci_channel_offline(struct pci_dev * pdev)889 pci_channel_offline(struct pci_dev *pdev)
890 {
891
892 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID);
893 }
894
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)895 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
896 {
897 return -ENODEV;
898 }
899
pci_disable_sriov(struct pci_dev * dev)900 static inline void pci_disable_sriov(struct pci_dev *dev)
901 {
902 }
903
904 static inline void *
pci_iomap(struct pci_dev * pdev,int mmio_bar,int mmio_size)905 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size)
906 {
907 struct resource *res;
908
909 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size);
910 if (res == NULL)
911 return (NULL);
912 /* This is a FreeBSD extension so we can use bus_*(). */
913 if (pdev->want_iomap_res)
914 return (res);
915 return ((void *)rman_get_bushandle(res));
916 }
917
918 static inline void
pci_iounmap(struct pci_dev * pdev,void * res)919 pci_iounmap(struct pci_dev *pdev, void *res)
920 {
921 struct pci_mmio_region *mmio, *p;
922
923 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) {
924 if (res != (void *)rman_get_bushandle(mmio->res))
925 continue;
926 bus_release_resource(pdev->dev.bsddev,
927 mmio->type, mmio->rid, mmio->res);
928 TAILQ_REMOVE(&pdev->mmio, mmio, next);
929 free(mmio, M_DEVBUF);
930 return;
931 }
932 }
933
934 static inline void
lkpi_pci_save_state(struct pci_dev * pdev)935 lkpi_pci_save_state(struct pci_dev *pdev)
936 {
937
938 pci_save_state(pdev->dev.bsddev);
939 }
940
941 static inline void
lkpi_pci_restore_state(struct pci_dev * pdev)942 lkpi_pci_restore_state(struct pci_dev *pdev)
943 {
944
945 pci_restore_state(pdev->dev.bsddev);
946 }
947
948 #define pci_save_state(dev) lkpi_pci_save_state(dev)
949 #define pci_restore_state(dev) lkpi_pci_restore_state(dev)
950
951 #define DEFINE_PCI_DEVICE_TABLE(_table) \
952 const struct pci_device_id _table[] __devinitdata
953
954 /* XXX This should not be necessary. */
955 #define pcix_set_mmrbc(d, v) 0
956 #define pcix_get_max_mmrbc(d) 0
957 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v))
958
959 #define PCI_DMA_BIDIRECTIONAL 0
960 #define PCI_DMA_TODEVICE 1
961 #define PCI_DMA_FROMDEVICE 2
962 #define PCI_DMA_NONE 3
963
964 #define pci_pool dma_pool
965 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__)
966 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__)
967 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__)
968 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \
969 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc)
970 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \
971 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
972 _size, _vaddr, _dma_handle)
973 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \
974 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
975 _sg, _nents, (enum dma_data_direction)_dir)
976 #define pci_map_single(_hwdev, _ptr, _size, _dir) \
977 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
978 (_ptr), (_size), (enum dma_data_direction)_dir)
979 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \
980 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
981 _addr, _size, (enum dma_data_direction)_dir)
982 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \
983 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
984 _sg, _nents, (enum dma_data_direction)_dir)
985 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \
986 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\
987 _offset, _size, (enum dma_data_direction)_dir)
988 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \
989 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
990 _dma_address, _size, (enum dma_data_direction)_dir)
991 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask))
992 #define pci_dma_mapping_error(_pdev, _dma_addr) \
993 dma_mapping_error(&(_pdev)->dev, _dma_addr)
994 #define pci_set_consistent_dma_mask(_pdev, _mask) \
995 dma_set_coherent_mask(&(_pdev)->dev, (_mask))
996 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x);
997 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x);
998 #define pci_unmap_addr dma_unmap_addr
999 #define pci_unmap_addr_set dma_unmap_addr_set
1000 #define pci_unmap_len dma_unmap_len
1001 #define pci_unmap_len_set dma_unmap_len_set
1002
1003 typedef unsigned int __bitwise pci_channel_state_t;
1004 typedef unsigned int __bitwise pci_ers_result_t;
1005
1006 enum pci_channel_state {
1007 pci_channel_io_normal = 1,
1008 pci_channel_io_frozen = 2,
1009 pci_channel_io_perm_failure = 3,
1010 };
1011
1012 enum pci_ers_result {
1013 PCI_ERS_RESULT_NONE = 1,
1014 PCI_ERS_RESULT_CAN_RECOVER = 2,
1015 PCI_ERS_RESULT_NEED_RESET = 3,
1016 PCI_ERS_RESULT_DISCONNECT = 4,
1017 PCI_ERS_RESULT_RECOVERED = 5,
1018 };
1019
1020 /* PCI bus error event callbacks */
1021 struct pci_error_handlers {
1022 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
1023 enum pci_channel_state error);
1024 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
1025 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
1026 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
1027 void (*resume)(struct pci_dev *dev);
1028 };
1029
1030 /* FreeBSD does not support SRIOV - yet */
pci_physfn(struct pci_dev * dev)1031 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
1032 {
1033 return dev;
1034 }
1035
pci_is_pcie(struct pci_dev * dev)1036 static inline bool pci_is_pcie(struct pci_dev *dev)
1037 {
1038 return !!pci_pcie_cap(dev);
1039 }
1040
pcie_flags_reg(struct pci_dev * dev)1041 static inline u16 pcie_flags_reg(struct pci_dev *dev)
1042 {
1043 int pos;
1044 u16 reg16;
1045
1046 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
1047 if (!pos)
1048 return 0;
1049
1050 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16);
1051
1052 return reg16;
1053 }
1054
pci_pcie_type(struct pci_dev * dev)1055 static inline int pci_pcie_type(struct pci_dev *dev)
1056 {
1057 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1058 }
1059
pcie_cap_version(struct pci_dev * dev)1060 static inline int pcie_cap_version(struct pci_dev *dev)
1061 {
1062 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS;
1063 }
1064
pcie_cap_has_lnkctl(struct pci_dev * dev)1065 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev)
1066 {
1067 int type = pci_pcie_type(dev);
1068
1069 return pcie_cap_version(dev) > 1 ||
1070 type == PCI_EXP_TYPE_ROOT_PORT ||
1071 type == PCI_EXP_TYPE_ENDPOINT ||
1072 type == PCI_EXP_TYPE_LEG_END;
1073 }
1074
pcie_cap_has_devctl(const struct pci_dev * dev)1075 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
1076 {
1077 return true;
1078 }
1079
pcie_cap_has_sltctl(struct pci_dev * dev)1080 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev)
1081 {
1082 int type = pci_pcie_type(dev);
1083
1084 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
1085 (type == PCI_EXP_TYPE_DOWNSTREAM &&
1086 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT);
1087 }
1088
pcie_cap_has_rtctl(struct pci_dev * dev)1089 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev)
1090 {
1091 int type = pci_pcie_type(dev);
1092
1093 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
1094 type == PCI_EXP_TYPE_RC_EC;
1095 }
1096
pcie_capability_reg_implemented(struct pci_dev * dev,int pos)1097 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
1098 {
1099 if (!pci_is_pcie(dev))
1100 return false;
1101
1102 switch (pos) {
1103 case PCI_EXP_FLAGS_TYPE:
1104 return true;
1105 case PCI_EXP_DEVCAP:
1106 case PCI_EXP_DEVCTL:
1107 case PCI_EXP_DEVSTA:
1108 return pcie_cap_has_devctl(dev);
1109 case PCI_EXP_LNKCAP:
1110 case PCI_EXP_LNKCTL:
1111 case PCI_EXP_LNKSTA:
1112 return pcie_cap_has_lnkctl(dev);
1113 case PCI_EXP_SLTCAP:
1114 case PCI_EXP_SLTCTL:
1115 case PCI_EXP_SLTSTA:
1116 return pcie_cap_has_sltctl(dev);
1117 case PCI_EXP_RTCTL:
1118 case PCI_EXP_RTCAP:
1119 case PCI_EXP_RTSTA:
1120 return pcie_cap_has_rtctl(dev);
1121 case PCI_EXP_DEVCAP2:
1122 case PCI_EXP_DEVCTL2:
1123 case PCI_EXP_LNKCAP2:
1124 case PCI_EXP_LNKCTL2:
1125 case PCI_EXP_LNKSTA2:
1126 return pcie_cap_version(dev) > 1;
1127 default:
1128 return false;
1129 }
1130 }
1131
1132 static inline int
pcie_capability_read_dword(struct pci_dev * dev,int pos,u32 * dst)1133 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst)
1134 {
1135 if (pos & 3)
1136 return -EINVAL;
1137
1138 if (!pcie_capability_reg_implemented(dev, pos))
1139 return -EINVAL;
1140
1141 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst);
1142 }
1143
1144 static inline int
pcie_capability_read_word(struct pci_dev * dev,int pos,u16 * dst)1145 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst)
1146 {
1147 if (pos & 3)
1148 return -EINVAL;
1149
1150 if (!pcie_capability_reg_implemented(dev, pos))
1151 return -EINVAL;
1152
1153 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst);
1154 }
1155
1156 static inline int
pcie_capability_write_word(struct pci_dev * dev,int pos,u16 val)1157 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
1158 {
1159 if (pos & 1)
1160 return -EINVAL;
1161
1162 if (!pcie_capability_reg_implemented(dev, pos))
1163 return 0;
1164
1165 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
1166 }
1167
pcie_get_minimum_link(struct pci_dev * dev,enum pci_bus_speed * speed,enum pcie_link_width * width)1168 static inline int pcie_get_minimum_link(struct pci_dev *dev,
1169 enum pci_bus_speed *speed, enum pcie_link_width *width)
1170 {
1171 *speed = PCI_SPEED_UNKNOWN;
1172 *width = PCIE_LNK_WIDTH_UNKNOWN;
1173 return (0);
1174 }
1175
1176 static inline int
pci_num_vf(struct pci_dev * dev)1177 pci_num_vf(struct pci_dev *dev)
1178 {
1179 return (0);
1180 }
1181
1182 static inline enum pci_bus_speed
pcie_get_speed_cap(struct pci_dev * dev)1183 pcie_get_speed_cap(struct pci_dev *dev)
1184 {
1185 device_t root;
1186 uint32_t lnkcap, lnkcap2;
1187 int error, pos;
1188
1189 root = device_get_parent(dev->dev.bsddev);
1190 if (root == NULL)
1191 return (PCI_SPEED_UNKNOWN);
1192 root = device_get_parent(root);
1193 if (root == NULL)
1194 return (PCI_SPEED_UNKNOWN);
1195 root = device_get_parent(root);
1196 if (root == NULL)
1197 return (PCI_SPEED_UNKNOWN);
1198
1199 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA ||
1200 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS)
1201 return (PCI_SPEED_UNKNOWN);
1202
1203 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0)
1204 return (PCI_SPEED_UNKNOWN);
1205
1206 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4);
1207
1208 if (lnkcap2) { /* PCIe r3.0-compliant */
1209 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
1210 return (PCIE_SPEED_2_5GT);
1211 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
1212 return (PCIE_SPEED_5_0GT);
1213 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
1214 return (PCIE_SPEED_8_0GT);
1215 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
1216 return (PCIE_SPEED_16_0GT);
1217 } else { /* pre-r3.0 */
1218 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4);
1219 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
1220 return (PCIE_SPEED_2_5GT);
1221 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
1222 return (PCIE_SPEED_5_0GT);
1223 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
1224 return (PCIE_SPEED_8_0GT);
1225 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
1226 return (PCIE_SPEED_16_0GT);
1227 }
1228 return (PCI_SPEED_UNKNOWN);
1229 }
1230
1231 static inline enum pcie_link_width
pcie_get_width_cap(struct pci_dev * dev)1232 pcie_get_width_cap(struct pci_dev *dev)
1233 {
1234 uint32_t lnkcap;
1235
1236 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
1237 if (lnkcap)
1238 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4);
1239
1240 return (PCIE_LNK_WIDTH_UNKNOWN);
1241 }
1242
1243 static inline int
pcie_get_mps(struct pci_dev * dev)1244 pcie_get_mps(struct pci_dev *dev)
1245 {
1246 return (pci_get_max_payload(dev->dev.bsddev));
1247 }
1248
1249 static inline uint32_t
PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd)1250 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd)
1251 {
1252
1253 switch(spd) {
1254 case PCIE_SPEED_16_0GT:
1255 return (16000 * 128 / 130);
1256 case PCIE_SPEED_8_0GT:
1257 return (8000 * 128 / 130);
1258 case PCIE_SPEED_5_0GT:
1259 return (5000 * 8 / 10);
1260 case PCIE_SPEED_2_5GT:
1261 return (2500 * 8 / 10);
1262 default:
1263 return (0);
1264 }
1265 }
1266
1267 static inline uint32_t
pcie_bandwidth_available(struct pci_dev * pdev,struct pci_dev ** limiting,enum pci_bus_speed * speed,enum pcie_link_width * width)1268 pcie_bandwidth_available(struct pci_dev *pdev,
1269 struct pci_dev **limiting,
1270 enum pci_bus_speed *speed,
1271 enum pcie_link_width *width)
1272 {
1273 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev);
1274 enum pcie_link_width nwidth = pcie_get_width_cap(pdev);
1275
1276 if (speed)
1277 *speed = nspeed;
1278 if (width)
1279 *width = nwidth;
1280
1281 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed));
1282 }
1283
1284 static inline struct pci_dev *
pcie_find_root_port(struct pci_dev * pdev)1285 pcie_find_root_port(struct pci_dev *pdev)
1286 {
1287 device_t root;
1288
1289 if (pdev->root != NULL)
1290 return (pdev->root);
1291
1292 root = pci_find_pcie_root_port(pdev->dev.bsddev);
1293 if (root == NULL)
1294 return (NULL);
1295
1296 pdev->root = lkpinew_pci_dev(root);
1297 return (pdev->root);
1298 }
1299
1300 /* This is needed when people rip out the device "HotPlug". */
1301 static inline void
pci_lock_rescan_remove(void)1302 pci_lock_rescan_remove(void)
1303 {
1304 }
1305
1306 static inline void
pci_unlock_rescan_remove(void)1307 pci_unlock_rescan_remove(void)
1308 {
1309 }
1310
1311 static __inline void
pci_stop_and_remove_bus_device(struct pci_dev * pdev)1312 pci_stop_and_remove_bus_device(struct pci_dev *pdev)
1313 {
1314 }
1315
1316 /*
1317 * The following functions can be used to attach/detach the LinuxKPI's
1318 * PCI device runtime. The pci_driver and pci_device_id pointer is
1319 * allowed to be NULL. Other pointers must be all valid.
1320 * The pci_dev structure should be zero-initialized before passed
1321 * to the linux_pci_attach_device function.
1322 */
1323 extern int linux_pci_attach_device(device_t, struct pci_driver *,
1324 const struct pci_device_id *, struct pci_dev *);
1325 extern int linux_pci_detach_device(struct pci_dev *);
1326
1327 static inline int
pci_dev_present(const struct pci_device_id * cur)1328 pci_dev_present(const struct pci_device_id *cur)
1329 {
1330 while (cur != NULL && (cur->vendor || cur->device)) {
1331 if (pci_find_device(cur->vendor, cur->device) != NULL) {
1332 return (1);
1333 }
1334 cur++;
1335 }
1336 return (0);
1337 }
1338
1339 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain,
1340 unsigned int bus, unsigned int devfn);
1341 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \
1342 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn)
1343
1344 static inline int
pci_domain_nr(struct pci_bus * pbus)1345 pci_domain_nr(struct pci_bus *pbus)
1346 {
1347
1348 return (pbus->domain);
1349 }
1350
1351 static inline int
pci_bus_read_config(struct pci_bus * bus,unsigned int devfn,int pos,uint32_t * val,int len)1352 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn,
1353 int pos, uint32_t *val, int len)
1354 {
1355
1356 *val = pci_read_config(bus->self->dev.bsddev, pos, len);
1357 return (0);
1358 }
1359
1360 static inline int
pci_bus_read_config_word(struct pci_bus * bus,unsigned int devfn,int pos,u16 * val)1361 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val)
1362 {
1363 uint32_t tmp;
1364 int ret;
1365
1366 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2);
1367 *val = (u16)tmp;
1368 return (ret);
1369 }
1370
1371 static inline int
pci_bus_read_config_byte(struct pci_bus * bus,unsigned int devfn,int pos,u8 * val)1372 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val)
1373 {
1374 uint32_t tmp;
1375 int ret;
1376
1377 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1);
1378 *val = (u8)tmp;
1379 return (ret);
1380 }
1381
1382 static inline int
pci_bus_write_config(struct pci_bus * bus,unsigned int devfn,int pos,uint32_t val,int size)1383 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos,
1384 uint32_t val, int size)
1385 {
1386
1387 pci_write_config(bus->self->dev.bsddev, pos, val, size);
1388 return (0);
1389 }
1390
1391 static inline int
pci_bus_write_config_byte(struct pci_bus * bus,unsigned int devfn,int pos,uint8_t val)1392 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos,
1393 uint8_t val)
1394 {
1395 return (pci_bus_write_config(bus, devfn, pos, val, 1));
1396 }
1397
1398 static inline int
pci_bus_write_config_word(struct pci_bus * bus,unsigned int devfn,int pos,uint16_t val)1399 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos,
1400 uint16_t val)
1401 {
1402 return (pci_bus_write_config(bus, devfn, pos, val, 2));
1403 }
1404
1405 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from);
1406 #define pci_get_class(class, from) lkpi_pci_get_class(class, from)
1407
1408 /* -------------------------------------------------------------------------- */
1409
1410 static inline int
pcim_enable_device(struct pci_dev * pdev)1411 pcim_enable_device(struct pci_dev *pdev)
1412 {
1413 struct pci_devres *dr;
1414 int error;
1415
1416 /* Here we cannot run through the pdev->managed check. */
1417 dr = lkpi_pci_devres_get_alloc(pdev);
1418 if (dr == NULL)
1419 return (-ENOMEM);
1420
1421 /* If resources were enabled before do not do it again. */
1422 if (dr->enable_io)
1423 return (0);
1424
1425 error = pci_enable_device(pdev);
1426 if (error == 0)
1427 dr->enable_io = true;
1428
1429 /* This device is not managed. */
1430 pdev->managed = true;
1431
1432 return (error);
1433 }
1434
1435 static inline void __iomem **
pcim_iomap_table(struct pci_dev * pdev)1436 pcim_iomap_table(struct pci_dev *pdev)
1437 {
1438 struct pcim_iomap_devres *dr;
1439
1440 dr = lkpi_pcim_iomap_devres_find(pdev);
1441 if (dr == NULL)
1442 return (NULL);
1443
1444 /*
1445 * If the driver has manually set a flag to be able to request the
1446 * resource to use bus_read/write_<n>, return the shadow table.
1447 */
1448 if (pdev->want_iomap_res)
1449 return ((void **)dr->res_table);
1450
1451 /* This is the Linux default. */
1452 return (dr->mmio_table);
1453 }
1454
1455 static inline int
pcim_iomap_regions_request_all(struct pci_dev * pdev,uint32_t mask,char * name)1456 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name)
1457 {
1458 struct pcim_iomap_devres *dr;
1459 void *res;
1460 uint32_t mappings, requests, req_mask;
1461 int bar, error;
1462
1463 dr = lkpi_pcim_iomap_devres_find(pdev);
1464 if (dr == NULL)
1465 return (-ENOMEM);
1466
1467 /* Request all the BARs ("regions") we do not iomap. */
1468 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask;
1469 for (bar = requests = 0; requests != req_mask; bar++) {
1470 if ((req_mask & (1 << bar)) == 0)
1471 continue;
1472 error = pci_request_region(pdev, bar, name);
1473 if (error != 0 && error != -ENODEV)
1474 goto err;
1475 requests |= (1 << bar);
1476 }
1477
1478 /* Now iomap all the requested (by "mask") ones. */
1479 for (bar = mappings = 0; mappings != mask; bar++) {
1480 if ((mask & (1 << bar)) == 0)
1481 continue;
1482
1483 /* Request double is not allowed. */
1484 if (dr->mmio_table[bar] != NULL) {
1485 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n",
1486 __func__, bar, dr->mmio_table[bar]);
1487 goto err;
1488 }
1489
1490 res = _lkpi_pci_iomap(pdev, bar, 0);
1491 if (res == NULL)
1492 goto err;
1493 dr->mmio_table[bar] = (void *)rman_get_bushandle(res);
1494 dr->res_table[bar] = res;
1495
1496 mappings |= (1 << bar);
1497 }
1498
1499 return (0);
1500
1501 err:
1502 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) {
1503 if ((mappings & (1 << bar)) != 0) {
1504 res = dr->mmio_table[bar];
1505 if (res == NULL)
1506 continue;
1507 pci_iounmap(pdev, res);
1508 } else if ((requests & (1 << bar)) != 0) {
1509 pci_release_region(pdev, bar);
1510 }
1511 }
1512
1513 return (-EINVAL);
1514 }
1515
1516 /* This is a FreeBSD extension so we can use bus_*(). */
1517 static inline void
linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev * pdev)1518 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev)
1519 {
1520 pdev->want_iomap_res = true;
1521 }
1522
1523 #endif /* _LINUXKPI_LINUX_PCI_H_ */
1524