1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997 Semen Ustimenko 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #define EPIC_MAX_MTU 1600 /* This is experiment-derived value */ 32 33 /* PCI aux configuration registers */ 34 #define PCIR_BASEIO PCIR_BAR(0) /* Base IO Address */ 35 #define PCIR_BASEMEM PCIR_BAR(1) /* Base Memory Address */ 36 37 /* PCI identification */ 38 #define SMC_VENDORID 0x10B8 39 #define SMC_DEVICEID_83C170 0x0005 40 41 /* EPIC's registers */ 42 #define COMMAND 0x0000 43 #define INTSTAT 0x0004 /* Interrupt status. See below */ 44 #define INTMASK 0x0008 /* Interrupt mask. See below */ 45 #define GENCTL 0x000C 46 #define NVCTL 0x0010 47 #define EECTL 0x0014 /* EEPROM control **/ 48 #define TEST1 0x001C /* XXXXX */ 49 #define CRCCNT 0x0020 /* CRC error counter */ 50 #define ALICNT 0x0024 /* FrameTooLang error counter */ 51 #define MPCNT 0x0028 /* MissedFrames error counters */ 52 #define MIICTL 0x0030 53 #define MIIDATA 0x0034 54 #define MIICFG 0x0038 55 #define IPG 0x003C 56 #define LAN0 0x0040 /* MAC address */ 57 #define LAN1 0x0044 /* MAC address */ 58 #define LAN2 0x0048 /* MAC address */ 59 #define ID_CHK 0x004C 60 #define MC0 0x0050 /* Multicast filter table */ 61 #define MC1 0x0054 /* Multicast filter table */ 62 #define MC2 0x0058 /* Multicast filter table */ 63 #define MC3 0x005C /* Multicast filter table */ 64 #define RXCON 0x0060 /* Rx control register */ 65 #define TXCON 0x0070 /* Tx control register */ 66 #define TXSTAT 0x0074 67 #define PRCDAR 0x0084 /* RxRing bus address */ 68 #define PRSTAT 0x00A4 69 #define PRCPTHR 0x00B0 70 #define PTCDAR 0x00C4 /* TxRing bus address */ 71 #define ETXTHR 0x00DC 72 73 #define COMMAND_STOP_RX 0x01 74 #define COMMAND_START_RX 0x02 75 #define COMMAND_TXQUEUED 0x04 76 #define COMMAND_RXQUEUED 0x08 77 #define COMMAND_NEXTFRAME 0x10 78 #define COMMAND_STOP_TDMA 0x20 79 #define COMMAND_STOP_RDMA 0x40 80 #define COMMAND_TXUGO 0x80 81 82 /* Interrupt register bits */ 83 #define INTSTAT_RCC 0x00000001 84 #define INTSTAT_HCC 0x00000002 85 #define INTSTAT_RQE 0x00000004 86 #define INTSTAT_OVW 0x00000008 87 #define INTSTAT_RXE 0x00000010 88 #define INTSTAT_TXC 0x00000020 89 #define INTSTAT_TCC 0x00000040 90 #define INTSTAT_TQE 0x00000080 91 #define INTSTAT_TXU 0x00000100 92 #define INTSTAT_CNT 0x00000200 93 #define INTSTAT_PREI 0x00000400 94 #define INTSTAT_RCT 0x00000800 95 #define INTSTAT_FATAL 0x00001000 /* One of DPE,APE,PMA,PTA happened */ 96 #define INTSTAT_UNUSED1 0x00002000 97 #define INTSTAT_UNUSED2 0x00004000 98 #define INTSTAT_GP2 0x00008000 /* PHY Event */ 99 #define INTSTAT_INT_ACTV 0x00010000 100 #define INTSTAT_RXIDLE 0x00020000 101 #define INTSTAT_TXIDLE 0x00040000 102 #define INTSTAT_RCIP 0x00080000 103 #define INTSTAT_TCIP 0x00100000 104 #define INTSTAT_RBE 0x00200000 105 #define INTSTAT_RCTS 0x00400000 106 #define INTSTAT_RSV 0x00800000 107 #define INTSTAT_DPE 0x01000000 /* PCI Fatal error */ 108 #define INTSTAT_APE 0x02000000 /* PCI Fatal error */ 109 #define INTSTAT_PMA 0x04000000 /* PCI Fatal error */ 110 #define INTSTAT_PTA 0x08000000 /* PCI Fatal error */ 111 112 #define GENCTL_SOFT_RESET 0x00000001 113 #define GENCTL_ENABLE_INTERRUPT 0x00000002 114 #define GENCTL_SOFTWARE_INTERRUPT 0x00000004 115 #define GENCTL_POWER_DOWN 0x00000008 116 #define GENCTL_ONECOPY 0x00000010 117 #define GENCTL_BIG_ENDIAN 0x00000020 118 #define GENCTL_RECEIVE_DMA_PRIORITY 0x00000040 119 #define GENCTL_TRANSMIT_DMA_PRIORITY 0x00000080 120 #define GENCTL_RECEIVE_FIFO_THRESHOLD128 0x00000300 121 #define GENCTL_RECEIVE_FIFO_THRESHOLD96 0x00000200 122 #define GENCTL_RECEIVE_FIFO_THRESHOLD64 0x00000100 123 #define GENCTL_RECEIVE_FIFO_THRESHOLD32 0x00000000 124 #define GENCTL_MEMORY_READ_LINE 0x00000400 125 #define GENCTL_MEMORY_READ_MULTIPLE 0x00000800 126 #define GENCTL_SOFTWARE1 0x00001000 127 #define GENCTL_SOFTWARE2 0x00002000 128 #define GENCTL_RESET_PHY 0x00004000 129 130 #define NVCTL_ENABLE_MEMORY_MAP 0x00000001 131 #define NVCTL_CLOCK_RUN_SUPPORTED 0x00000002 132 #define NVCTL_GP1_OUTPUT_ENABLE 0x00000004 133 #define NVCTL_GP2_OUTPUT_ENABLE 0x00000008 134 #define NVCTL_GP1 0x00000010 135 #define NVCTL_GP2 0x00000020 136 #define NVCTL_CARDBUS_MODE 0x00000040 137 #define NVCTL_IPG_DELAY_MASK(x) ((x&0xF)<<7) 138 139 #define RXCON_SAVE_ERRORED_PACKETS 0x00000001 140 #define RXCON_RECEIVE_RUNT_FRAMES 0x00000002 141 #define RXCON_RECEIVE_BROADCAST_FRAMES 0x00000004 142 #define RXCON_RECEIVE_MULTICAST_FRAMES 0x00000008 143 #define RXCON_RECEIVE_INVERSE_INDIVIDUAL_ADDRESS_FRAMES 0x00000010 144 #define RXCON_PROMISCUOUS_MODE 0x00000020 145 #define RXCON_MONITOR_MODE 0x00000040 146 #define RXCON_EARLY_RECEIVE_ENABLE 0x00000080 147 #define RXCON_EXTERNAL_BUFFER_DISABLE 0x00000000 148 #define RXCON_EXTERNAL_BUFFER_16K 0x00000100 149 #define RXCON_EXTERNAL_BUFFER_32K 0x00000200 150 #define RXCON_EXTERNAL_BUFFER_128K 0x00000300 151 152 #define TXCON_EARLY_TRANSMIT_ENABLE 0x00000001 153 #define TXCON_LOOPBACK_DISABLE 0x00000000 154 #define TXCON_LOOPBACK_MODE_INT 0x00000002 155 #define TXCON_LOOPBACK_MODE_PHY 0x00000004 156 #define TXCON_LOOPBACK_MODE 0x00000006 157 #define TXCON_FULL_DUPLEX 0x00000006 158 #define TXCON_SLOT_TIME 0x00000078 159 160 #define MIICFG_SERIAL_ENABLE 0x00000001 161 #define MIICFG_694_ENABLE 0x00000002 162 #define MIICFG_694_STATUS 0x00000004 163 #define MIICFG_PHY_PRESENT 0x00000008 164 #define MIICFG_SMI_ENABLE 0x00000010 165 166 #define TEST1_CLOCK_TEST 0x00000008 167 168 /* 169 * Some default values 170 */ 171 #define TXCON_DEFAULT (TXCON_SLOT_TIME | TXCON_EARLY_TRANSMIT_ENABLE) 172 #define TRANSMIT_THRESHOLD 0x300 173 #define TRANSMIT_THRESHOLD_MAX 0x600 174 175 #define RXCON_DEFAULT (RXCON_RECEIVE_MULTICAST_FRAMES | \ 176 RXCON_RECEIVE_BROADCAST_FRAMES) 177 178 #define RXCON_EARLY_RX (RXCON_EARLY_RECEIVE_ENABLE | \ 179 RXCON_SAVE_ERRORED_PACKETS) 180 /* 181 * EEPROM structure 182 * SMC9432* eeprom is organized by words and only first 8 words 183 * have distinctive meaning (according to datasheet) 184 */ 185 #define EEPROM_MAC0 0x0000 /* Byte 0 / Byte 1 */ 186 #define EEPROM_MAC1 0x0001 /* Byte 2 / Byte 3 */ 187 #define EEPROM_MAC2 0x0002 /* Byte 4 / Byte 5 */ 188 #define EEPROM_BID_CSUM 0x0003 /* Board Id / Check Sum */ 189 #define EEPROM_NVCTL 0x0004 /* NVCTL (bits 0-5) / nothing */ 190 #define EEPROM_PCI_MGD_MLD 0x0005 /* PCI MinGrant / MaxLatency. Desired */ 191 #define EEPROM_SSVENDID 0x0006 /* Subsystem Vendor Id */ 192 #define EEPROM_SSID 0x0006 /* Subsystem Id */ 193 194 /* 195 * Hardware structures. 196 */ 197 198 /* 199 * EPIC's hardware descriptors, must be aligned on dword in memory. 200 * NB: to make driver happy, this two structures MUST have their sizes 201 * be divisor of PAGE_SIZE. 202 */ 203 struct epic_tx_desc { 204 volatile u_int16_t status; 205 volatile u_int16_t txlength; 206 volatile u_int32_t bufaddr; 207 volatile u_int16_t buflength; 208 volatile u_int16_t control; 209 volatile u_int32_t next; 210 }; 211 struct epic_rx_desc { 212 volatile u_int16_t status; 213 volatile u_int16_t rxlength; 214 volatile u_int32_t bufaddr; 215 volatile u_int32_t buflength; 216 volatile u_int32_t next; 217 }; 218 219 /* 220 * This structure defines EPIC's fragment list, maximum number of frags 221 * is 63. Let's use the maximum, because size of struct MUST be divisor 222 * of PAGE_SIZE, and sometimes come mbufs with more then 30 frags. 223 */ 224 #define EPIC_MAX_FRAGS 63 225 struct epic_frag_list { 226 volatile u_int32_t numfrags; 227 struct { 228 volatile u_int32_t fragaddr; 229 volatile u_int32_t fraglen; 230 } frag[EPIC_MAX_FRAGS]; 231 volatile u_int32_t pad; /* align on 256 bytes */ 232 }; 233 234 /* 235 * NB: ALIGN OF ABOVE STRUCTURES 236 * epic_rx_desc, epic_tx_desc, epic_frag_list - must be aligned on dword 237 */ 238 239 #define SMC9432DMT 0xA010 240 #define SMC9432TX 0xA011 241 #define SMC9032TXM 0xA012 242 #define SMC9032TX 0xA013 243 #define SMC9432TXPWR 0xA014 244 #define SMC9432BTX 0xA015 245 #define SMC9432FTX 0xA016 246 #define SMC9432FTX_SC 0xA017 247 #define SMC9432TX_XG_ADHOC 0xA020 248 #define SMC9434TX_XG_ADHOC 0xA021 249 #define SMC9432FTX_ADHOC 0xA022 250 #define SMC9432BTX1 0xA024 251