1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2003-2012 Broadcom Corporation
5 * All Rights Reserved
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
25 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
26 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
27 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
28 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * $FreeBSD$
31 */
32
33 #ifndef __NLM_NAE_H__
34 #define __NLM_NAE_H__
35
36 /**
37 * @file_name nae.h
38 * @author Netlogic Microsystems
39 * @brief Basic definitions of XLP Networt Accelerator Engine
40 */
41
42 /* NAE specific registers */
43 #define NAE_REG(blk, intf, reg) (((blk) << 11) | ((intf) << 7) | (reg))
44
45 /* ingress path registers */
46 #define NAE_RX_CONFIG NAE_REG(7, 0, 0x10)
47 #define NAE_RX_IF_BASE_CONFIG0 NAE_REG(7, 0, 0x12)
48 #define NAE_RX_IF_BASE_CONFIG1 NAE_REG(7, 0, 0x13)
49 #define NAE_RX_IF_BASE_CONFIG2 NAE_REG(7, 0, 0x14)
50 #define NAE_RX_IF_BASE_CONFIG3 NAE_REG(7, 0, 0x15)
51 #define NAE_RX_IF_BASE_CONFIG4 NAE_REG(7, 0, 0x16)
52 #define NAE_RX_IF_BASE_CONFIG5 NAE_REG(7, 0, 0x17)
53 #define NAE_RX_IF_BASE_CONFIG6 NAE_REG(7, 0, 0x18)
54 #define NAE_RX_IF_BASE_CONFIG7 NAE_REG(7, 0, 0x19)
55 #define NAE_RX_IF_BASE_CONFIG8 NAE_REG(7, 0, 0x1a)
56 #define NAE_RX_IF_BASE_CONFIG9 NAE_REG(7, 0, 0x1b)
57 #define NAE_RX_IF_VEC_VALID NAE_REG(7, 0, 0x1c)
58 #define NAE_RX_IF_SLOT_CAL NAE_REG(7, 0, 0x1d)
59 #define NAE_PARSER_CONFIG NAE_REG(7, 0, 0x1e)
60 #define NAE_PARSER_SEQ_FIFO_CFG NAE_REG(7, 0, 0x1f)
61 #define NAE_FREE_IN_FIFO_CFG NAE_REG(7, 0, 0x20)
62 #define NAE_RXBUF_BASE_DPTH_ADDR NAE_REG(7, 0, 0x21)
63 #define NAE_RXBUF_BASE_DPTH NAE_REG(7, 0, 0x22)
64 #define NAE_RX_UCORE_CFG NAE_REG(7, 0, 0x23)
65 #define NAE_RX_UCORE_CAM_MASK0 NAE_REG(7, 0, 0x24)
66 #define NAE_RX_UCORE_CAM_MASK1 NAE_REG(7, 0, 0x25)
67 #define NAE_RX_UCORE_CAM_MASK2 NAE_REG(7, 0, 0x26)
68 #define NAE_RX_UCORE_CAM_MASK3 NAE_REG(7, 0, 0x27)
69 #define NAE_FREEIN_FIFO_UNIQ_SZ_CFG NAE_REG(7, 0, 0x28)
70 #define NAE_RX_CRC_POLY0_CFG NAE_REG(7, 0, 0x2a)
71 #define NAE_RX_CRC_POLY1_CFG NAE_REG(7, 0, 0x2b)
72 #define NAE_FREE_SPILL0_MEM_CFG NAE_REG(7, 0, 0x2c)
73 #define NAE_FREE_SPILL1_MEM_CFG NAE_REG(7, 0, 0x2d)
74 #define NAE_FREEFIFO_THRESH_CFG NAE_REG(7, 0, 0x2e)
75 #define NAE_FLOW_CRC16_POLY_CFG NAE_REG(7, 0, 0x2f)
76 #define NAE_EGR_NIOR_CAL_LEN_REG NAE_REG(7, 0, 0x4e)
77 #define NAE_EGR_NIOR_CRDT_CAL_PROG NAE_REG(7, 0, 0x52)
78 #define NAE_TEST NAE_REG(7, 0, 0x5f)
79 #define NAE_BIU_TIMEOUT_CFG NAE_REG(7, 0, 0x60)
80 #define NAE_BIU_CFG NAE_REG(7, 0, 0x61)
81 #define NAE_RX_FREE_FIFO_POP NAE_REG(7, 0, 0x62)
82 #define NAE_RX_DSBL_ECC NAE_REG(7, 0, 0x63)
83 #define NAE_FLOW_BASEMASK_CFG NAE_REG(7, 0, 0x80)
84 #define NAE_POE_CLASS_SETUP_CFG NAE_REG(7, 0, 0x81)
85 #define NAE_UCORE_IFACEMASK_CFG NAE_REG(7, 0, 0x82)
86 #define NAE_RXBUF_XOFFON_THRESH NAE_REG(7, 0, 0x83)
87 #define NAE_FLOW_TABLE1_CFG NAE_REG(7, 0, 0x84)
88 #define NAE_FLOW_TABLE2_CFG NAE_REG(7, 0, 0x85)
89 #define NAE_FLOW_TABLE3_CFG NAE_REG(7, 0, 0x86)
90 #define NAE_RX_FREE_FIFO_THRESH NAE_REG(7, 0, 0x87)
91 #define NAE_RX_PARSER_UNCLA NAE_REG(7, 0, 0x88)
92 #define NAE_RX_BUF_INTR_THRESH NAE_REG(7, 0, 0x89)
93 #define NAE_IFACE_FIFO_CFG NAE_REG(7, 0, 0x8a)
94 #define NAE_PARSER_SEQ_FIFO_THRESH_CFG NAE_REG(7, 0, 0x8b)
95 #define NAE_RX_ERRINJ_CTRL0 NAE_REG(7, 0, 0x8c)
96 #define NAE_RX_ERRINJ_CTRL1 NAE_REG(7, 0, 0x8d)
97 #define NAE_RX_ERR_LATCH0 NAE_REG(7, 0, 0x8e)
98 #define NAE_RX_ERR_LATCH1 NAE_REG(7, 0, 0x8f)
99 #define NAE_RX_PERF_CTR_CFG NAE_REG(7, 0, 0xa0)
100 #define NAE_RX_PERF_CTR_VAL NAE_REG(7, 0, 0xa1)
101
102 /* NAE hardware parser registers */
103 #define NAE_L2_TYPE_PORT0 NAE_REG(7, 0, 0x210)
104 #define NAE_L2_TYPE_PORT1 NAE_REG(7, 0, 0x211)
105 #define NAE_L2_TYPE_PORT2 NAE_REG(7, 0, 0x212)
106 #define NAE_L2_TYPE_PORT3 NAE_REG(7, 0, 0x213)
107 #define NAE_L2_TYPE_PORT4 NAE_REG(7, 0, 0x214)
108 #define NAE_L2_TYPE_PORT5 NAE_REG(7, 0, 0x215)
109 #define NAE_L2_TYPE_PORT6 NAE_REG(7, 0, 0x216)
110 #define NAE_L2_TYPE_PORT7 NAE_REG(7, 0, 0x217)
111 #define NAE_L2_TYPE_PORT8 NAE_REG(7, 0, 0x218)
112 #define NAE_L2_TYPE_PORT9 NAE_REG(7, 0, 0x219)
113 #define NAE_L2_TYPE_PORT10 NAE_REG(7, 0, 0x21a)
114 #define NAE_L2_TYPE_PORT11 NAE_REG(7, 0, 0x21b)
115 #define NAE_L2_TYPE_PORT12 NAE_REG(7, 0, 0x21c)
116 #define NAE_L2_TYPE_PORT13 NAE_REG(7, 0, 0x21d)
117 #define NAE_L2_TYPE_PORT14 NAE_REG(7, 0, 0x21e)
118 #define NAE_L2_TYPE_PORT15 NAE_REG(7, 0, 0x21f)
119 #define NAE_L2_TYPE_PORT16 NAE_REG(7, 0, 0x220)
120 #define NAE_L2_TYPE_PORT17 NAE_REG(7, 0, 0x221)
121 #define NAE_L2_TYPE_PORT18 NAE_REG(7, 0, 0x222)
122 #define NAE_L2_TYPE_PORT19 NAE_REG(7, 0, 0x223)
123 #define NAE_L3_CTABLE_MASK0 NAE_REG(7, 0, 0x22c)
124 #define NAE_L3_CTABLE_MASK1 NAE_REG(7, 0, 0x22d)
125 #define NAE_L3_CTABLE_MASK2 NAE_REG(7, 0, 0x22e)
126 #define NAE_L3_CTABLE_MASK3 NAE_REG(7, 0, 0x22f)
127 #define NAE_L3CTABLE0 NAE_REG(7, 0, 0x230)
128 #define NAE_L3CTABLE1 NAE_REG(7, 0, 0x231)
129 #define NAE_L3CTABLE2 NAE_REG(7, 0, 0x232)
130 #define NAE_L3CTABLE3 NAE_REG(7, 0, 0x233)
131 #define NAE_L3CTABLE4 NAE_REG(7, 0, 0x234)
132 #define NAE_L3CTABLE5 NAE_REG(7, 0, 0x235)
133 #define NAE_L3CTABLE6 NAE_REG(7, 0, 0x236)
134 #define NAE_L3CTABLE7 NAE_REG(7, 0, 0x237)
135 #define NAE_L3CTABLE8 NAE_REG(7, 0, 0x238)
136 #define NAE_L3CTABLE9 NAE_REG(7, 0, 0x239)
137 #define NAE_L3CTABLE10 NAE_REG(7, 0, 0x23a)
138 #define NAE_L3CTABLE11 NAE_REG(7, 0, 0x23b)
139 #define NAE_L3CTABLE12 NAE_REG(7, 0, 0x23c)
140 #define NAE_L3CTABLE13 NAE_REG(7, 0, 0x23d)
141 #define NAE_L3CTABLE14 NAE_REG(7, 0, 0x23e)
142 #define NAE_L3CTABLE15 NAE_REG(7, 0, 0x23f)
143 #define NAE_L4CTABLE0 NAE_REG(7, 0, 0x250)
144 #define NAE_L4CTABLE1 NAE_REG(7, 0, 0x251)
145 #define NAE_L4CTABLE2 NAE_REG(7, 0, 0x252)
146 #define NAE_L4CTABLE3 NAE_REG(7, 0, 0x253)
147 #define NAE_L4CTABLE4 NAE_REG(7, 0, 0x254)
148 #define NAE_L4CTABLE5 NAE_REG(7, 0, 0x255)
149 #define NAE_L4CTABLE6 NAE_REG(7, 0, 0x256)
150 #define NAE_L4CTABLE7 NAE_REG(7, 0, 0x257)
151 #define NAE_IPV6_EXT_HEADER0 NAE_REG(7, 0, 0x260)
152 #define NAE_IPV6_EXT_HEADER1 NAE_REG(7, 0, 0x261)
153 #define NAE_VLAN_TYPES01 NAE_REG(7, 0, 0x262)
154 #define NAE_VLAN_TYPES23 NAE_REG(7, 0, 0x263)
155
156 /* NAE Egress path registers */
157 #define NAE_TX_CONFIG NAE_REG(7, 0, 0x11)
158 #define NAE_DMA_TX_CREDIT_TH NAE_REG(7, 0, 0x29)
159 #define NAE_STG1_STG2CRDT_CMD NAE_REG(7, 0, 0x30)
160 #define NAE_STG2_EHCRDT_CMD NAE_REG(7, 0, 0x32)
161 #define NAE_EH_FREECRDT_CMD NAE_REG(7, 0, 0x34)
162 #define NAE_STG2_STRCRDT_CMD NAE_REG(7, 0, 0x36)
163 #define NAE_TXFIFO_IFACEMAP_CMD NAE_REG(7, 0, 0x38)
164 #define NAE_VFBID_DESTMAP_CMD NAE_REG(7, 0, 0x3a)
165 #define NAE_STG1_PMEM_PROG NAE_REG(7, 0, 0x3c)
166 #define NAE_STG2_PMEM_PROG NAE_REG(7, 0, 0x3e)
167 #define NAE_EH_PMEM_PROG NAE_REG(7, 0, 0x40)
168 #define NAE_FREE_PMEM_PROG NAE_REG(7, 0, 0x42)
169 #define NAE_TX_DDR_ACTVLIST_CMD NAE_REG(7, 0, 0x44)
170 #define NAE_TX_IF_BURSTMAX_CMD NAE_REG(7, 0, 0x46)
171 #define NAE_TX_IF_ENABLE_CMD NAE_REG(7, 0, 0x48)
172 #define NAE_TX_PKTLEN_PMEM_CMD NAE_REG(7, 0, 0x4a)
173 #define NAE_TX_SCHED_MAP_CMD0 NAE_REG(7, 0, 0x4c)
174 #define NAE_TX_SCHED_MAP_CMD1 NAE_REG(7, 0, 0x4d)
175 #define NAE_TX_PKT_PMEM_CMD0 NAE_REG(7, 0, 0x50)
176 #define NAE_TX_PKT_PMEM_CMD1 NAE_REG(7, 0, 0x51)
177 #define NAE_TX_SCHED_CTRL NAE_REG(7, 0, 0x53)
178 #define NAE_TX_CRC_POLY0 NAE_REG(7, 0, 0x54)
179 #define NAE_TX_CRC_POLY1 NAE_REG(7, 0, 0x55)
180 #define NAE_TX_CRC_POLY2 NAE_REG(7, 0, 0x56)
181 #define NAE_TX_CRC_POLY3 NAE_REG(7, 0, 0x57)
182 #define NAE_STR_PMEM_CMD NAE_REG(7, 0, 0x58)
183 #define NAE_TX_IORCRDT_INIT NAE_REG(7, 0, 0x59)
184 #define NAE_TX_DSBL_ECC NAE_REG(7, 0, 0x5a)
185 #define NAE_TX_IORCRDT_IGNORE NAE_REG(7, 0, 0x5b)
186 #define NAE_IF0_1588_TMSTMP_HI NAE_REG(7, 0, 0x300)
187 #define NAE_IF1_1588_TMSTMP_HI NAE_REG(7, 0, 0x302)
188 #define NAE_IF2_1588_TMSTMP_HI NAE_REG(7, 0, 0x304)
189 #define NAE_IF3_1588_TMSTMP_HI NAE_REG(7, 0, 0x306)
190 #define NAE_IF4_1588_TMSTMP_HI NAE_REG(7, 0, 0x308)
191 #define NAE_IF5_1588_TMSTMP_HI NAE_REG(7, 0, 0x30a)
192 #define NAE_IF6_1588_TMSTMP_HI NAE_REG(7, 0, 0x30c)
193 #define NAE_IF7_1588_TMSTMP_HI NAE_REG(7, 0, 0x30e)
194 #define NAE_IF8_1588_TMSTMP_HI NAE_REG(7, 0, 0x310)
195 #define NAE_IF9_1588_TMSTMP_HI NAE_REG(7, 0, 0x312)
196 #define NAE_IF10_1588_TMSTMP_HI NAE_REG(7, 0, 0x314)
197 #define NAE_IF11_1588_TMSTMP_HI NAE_REG(7, 0, 0x316)
198 #define NAE_IF12_1588_TMSTMP_HI NAE_REG(7, 0, 0x318)
199 #define NAE_IF13_1588_TMSTMP_HI NAE_REG(7, 0, 0x31a)
200 #define NAE_IF14_1588_TMSTMP_HI NAE_REG(7, 0, 0x31c)
201 #define NAE_IF15_1588_TMSTMP_HI NAE_REG(7, 0, 0x31e)
202 #define NAE_IF16_1588_TMSTMP_HI NAE_REG(7, 0, 0x320)
203 #define NAE_IF17_1588_TMSTMP_HI NAE_REG(7, 0, 0x322)
204 #define NAE_IF18_1588_TMSTMP_HI NAE_REG(7, 0, 0x324)
205 #define NAE_IF19_1588_TMSTMP_HI NAE_REG(7, 0, 0x326)
206 #define NAE_IF0_1588_TMSTMP_LO NAE_REG(7, 0, 0x301)
207 #define NAE_IF1_1588_TMSTMP_LO NAE_REG(7, 0, 0x303)
208 #define NAE_IF2_1588_TMSTMP_LO NAE_REG(7, 0, 0x305)
209 #define NAE_IF3_1588_TMSTMP_LO NAE_REG(7, 0, 0x307)
210 #define NAE_IF4_1588_TMSTMP_LO NAE_REG(7, 0, 0x309)
211 #define NAE_IF5_1588_TMSTMP_LO NAE_REG(7, 0, 0x30b)
212 #define NAE_IF6_1588_TMSTMP_LO NAE_REG(7, 0, 0x30d)
213 #define NAE_IF7_1588_TMSTMP_LO NAE_REG(7, 0, 0x30f)
214 #define NAE_IF8_1588_TMSTMP_LO NAE_REG(7, 0, 0x311)
215 #define NAE_IF9_1588_TMSTMP_LO NAE_REG(7, 0, 0x313)
216 #define NAE_IF10_1588_TMSTMP_LO NAE_REG(7, 0, 0x315)
217 #define NAE_IF11_1588_TMSTMP_LO NAE_REG(7, 0, 0x317)
218 #define NAE_IF12_1588_TMSTMP_LO NAE_REG(7, 0, 0x319)
219 #define NAE_IF13_1588_TMSTMP_LO NAE_REG(7, 0, 0x31b)
220 #define NAE_IF14_1588_TMSTMP_LO NAE_REG(7, 0, 0x31d)
221 #define NAE_IF15_1588_TMSTMP_LO NAE_REG(7, 0, 0x31f)
222 #define NAE_IF16_1588_TMSTMP_LO NAE_REG(7, 0, 0x321)
223 #define NAE_IF17_1588_TMSTMP_LO NAE_REG(7, 0, 0x323)
224 #define NAE_IF18_1588_TMSTMP_LO NAE_REG(7, 0, 0x325)
225 #define NAE_IF19_1588_TMSTMP_LO NAE_REG(7, 0, 0x327)
226 #define NAE_TX_EL0 NAE_REG(7, 0, 0x328)
227 #define NAE_TX_EL1 NAE_REG(7, 0, 0x329)
228 #define NAE_EIC0 NAE_REG(7, 0, 0x32a)
229 #define NAE_EIC1 NAE_REG(7, 0, 0x32b)
230 #define NAE_STG1_STG2CRDT_STATUS NAE_REG(7, 0, 0x32c)
231 #define NAE_STG2_EHCRDT_STATUS NAE_REG(7, 0, 0x32d)
232 #define NAE_STG2_FREECRDT_STATUS NAE_REG(7, 0, 0x32e)
233 #define NAE_STG2_STRCRDT_STATUS NAE_REG(7, 0, 0x32f)
234 #define NAE_TX_PERF_CNTR_INTR_STATUS NAE_REG(7, 0, 0x330)
235 #define NAE_TX_PERF_CNTR_ROLL_STATUS NAE_REG(7, 0, 0x331)
236 #define NAE_TX_PERF_CNTR0 NAE_REG(7, 0, 0x332)
237 #define NAE_TX_PERF_CNTR1 NAE_REG(7, 0, 0x334)
238 #define NAE_TX_PERF_CNTR2 NAE_REG(7, 0, 0x336)
239 #define NAE_TX_PERF_CNTR3 NAE_REG(7, 0, 0x338)
240 #define NAE_TX_PERF_CNTR4 NAE_REG(7, 0, 0x33a)
241 #define NAE_TX_PERF_CNTR0_CTL NAE_REG(7, 0, 0x333)
242 #define NAE_TX_PERF_CNTR1_CTL NAE_REG(7, 0, 0x335)
243 #define NAE_TX_PERF_CNTR2_CTL NAE_REG(7, 0, 0x337)
244 #define NAE_TX_PERF_CNTR3_CTL NAE_REG(7, 0, 0x339)
245 #define NAE_TX_PERF_CNTR4_CTL NAE_REG(7, 0, 0x33b)
246 #define NAE_VFBID_DESTMAP_STATUS NAE_REG(7, 0, 0x380)
247 #define NAE_STG2_PMEM_STATUS NAE_REG(7, 0, 0x381)
248 #define NAE_EH_PMEM_STATUS NAE_REG(7, 0, 0x382)
249 #define NAE_FREE_PMEM_STATUS NAE_REG(7, 0, 0x383)
250 #define NAE_TX_DDR_ACTVLIST_STATUS NAE_REG(7, 0, 0x384)
251 #define NAE_TX_IF_BURSTMAX_STATUS NAE_REG(7, 0, 0x385)
252 #define NAE_TX_PKTLEN_PMEM_STATUS NAE_REG(7, 0, 0x386)
253 #define NAE_TX_SCHED_MAP_STATUS0 NAE_REG(7, 0, 0x387)
254 #define NAE_TX_SCHED_MAP_STATUS1 NAE_REG(7, 0, 0x388)
255 #define NAE_TX_PKT_PMEM_STATUS NAE_REG(7, 0, 0x389)
256 #define NAE_STR_PMEM_STATUS NAE_REG(7, 0, 0x38a)
257
258 /* Network interface interrupt registers */
259 #define NAE_NET_IF0_INTR_STAT NAE_REG(7, 0, 0x280)
260 #define NAE_NET_IF1_INTR_STAT NAE_REG(7, 0, 0x282)
261 #define NAE_NET_IF2_INTR_STAT NAE_REG(7, 0, 0x284)
262 #define NAE_NET_IF3_INTR_STAT NAE_REG(7, 0, 0x286)
263 #define NAE_NET_IF4_INTR_STAT NAE_REG(7, 0, 0x288)
264 #define NAE_NET_IF5_INTR_STAT NAE_REG(7, 0, 0x28a)
265 #define NAE_NET_IF6_INTR_STAT NAE_REG(7, 0, 0x28c)
266 #define NAE_NET_IF7_INTR_STAT NAE_REG(7, 0, 0x28e)
267 #define NAE_NET_IF8_INTR_STAT NAE_REG(7, 0, 0x290)
268 #define NAE_NET_IF9_INTR_STAT NAE_REG(7, 0, 0x292)
269 #define NAE_NET_IF10_INTR_STAT NAE_REG(7, 0, 0x294)
270 #define NAE_NET_IF11_INTR_STAT NAE_REG(7, 0, 0x296)
271 #define NAE_NET_IF12_INTR_STAT NAE_REG(7, 0, 0x298)
272 #define NAE_NET_IF13_INTR_STAT NAE_REG(7, 0, 0x29a)
273 #define NAE_NET_IF14_INTR_STAT NAE_REG(7, 0, 0x29c)
274 #define NAE_NET_IF15_INTR_STAT NAE_REG(7, 0, 0x29e)
275 #define NAE_NET_IF16_INTR_STAT NAE_REG(7, 0, 0x2a0)
276 #define NAE_NET_IF17_INTR_STAT NAE_REG(7, 0, 0x2a2)
277 #define NAE_NET_IF18_INTR_STAT NAE_REG(7, 0, 0x2a4)
278 #define NAE_NET_IF19_INTR_STAT NAE_REG(7, 0, 0x2a6)
279 #define NAE_NET_IF0_INTR_MASK NAE_REG(7, 0, 0x281)
280 #define NAE_NET_IF1_INTR_MASK NAE_REG(7, 0, 0x283)
281 #define NAE_NET_IF2_INTR_MASK NAE_REG(7, 0, 0x285)
282 #define NAE_NET_IF3_INTR_MASK NAE_REG(7, 0, 0x287)
283 #define NAE_NET_IF4_INTR_MASK NAE_REG(7, 0, 0x289)
284 #define NAE_NET_IF5_INTR_MASK NAE_REG(7, 0, 0x28b)
285 #define NAE_NET_IF6_INTR_MASK NAE_REG(7, 0, 0x28d)
286 #define NAE_NET_IF7_INTR_MASK NAE_REG(7, 0, 0x28f)
287 #define NAE_NET_IF8_INTR_MASK NAE_REG(7, 0, 0x291)
288 #define NAE_NET_IF9_INTR_MASK NAE_REG(7, 0, 0x293)
289 #define NAE_NET_IF10_INTR_MASK NAE_REG(7, 0, 0x295)
290 #define NAE_NET_IF11_INTR_MASK NAE_REG(7, 0, 0x297)
291 #define NAE_NET_IF12_INTR_MASK NAE_REG(7, 0, 0x299)
292 #define NAE_NET_IF13_INTR_MASK NAE_REG(7, 0, 0x29b)
293 #define NAE_NET_IF14_INTR_MASK NAE_REG(7, 0, 0x29d)
294 #define NAE_NET_IF15_INTR_MASK NAE_REG(7, 0, 0x29f)
295 #define NAE_NET_IF16_INTR_MASK NAE_REG(7, 0, 0x2a1)
296 #define NAE_NET_IF17_INTR_MASK NAE_REG(7, 0, 0x2a3)
297 #define NAE_NET_IF18_INTR_MASK NAE_REG(7, 0, 0x2a5)
298 #define NAE_NET_IF19_INTR_MASK NAE_REG(7, 0, 0x2a7)
299 #define NAE_COMMON0_INTR_STAT NAE_REG(7, 0, 0x2a8)
300 #define NAE_COMMON0_INTR_MASK NAE_REG(7, 0, 0x2a9)
301 #define NAE_COMMON1_INTR_STAT NAE_REG(7, 0, 0x2aa)
302 #define NAE_COMMON1_INTR_MASK NAE_REG(7, 0, 0x2ab)
303
304 /* Network Interface Low-block Registers */
305 #define NAE_PHY_LANE0_STATUS(block) NAE_REG(block, 0xe, 0)
306 #define NAE_PHY_LANE1_STATUS(block) NAE_REG(block, 0xe, 1)
307 #define NAE_PHY_LANE2_STATUS(block) NAE_REG(block, 0xe, 2)
308 #define NAE_PHY_LANE3_STATUS(block) NAE_REG(block, 0xe, 3)
309 #define NAE_PHY_LANE0_CTRL(block) NAE_REG(block, 0xe, 4)
310 #define NAE_PHY_LANE1_CTRL(block) NAE_REG(block, 0xe, 5)
311 #define NAE_PHY_LANE2_CTRL(block) NAE_REG(block, 0xe, 6)
312 #define NAE_PHY_LANE3_CTRL(block) NAE_REG(block, 0xe, 7)
313
314 /* Network interface Top-block registers */
315 #define NAE_LANE_CFG_CPLX_0_1 NAE_REG(7, 0, 0x780)
316 #define NAE_LANE_CFG_CPLX_2_3 NAE_REG(7, 0, 0x781)
317 #define NAE_LANE_CFG_CPLX_4 NAE_REG(7, 0, 0x782)
318 #define NAE_LANE_CFG_SOFTRESET NAE_REG(7, 0, 0x783)
319 #define NAE_1588_PTP_OFFSET_HI NAE_REG(7, 0, 0x784)
320 #define NAE_1588_PTP_OFFSET_LO NAE_REG(7, 0, 0x785)
321 #define NAE_1588_PTP_INC_DEN NAE_REG(7, 0, 0x786)
322 #define NAE_1588_PTP_INC_NUM NAE_REG(7, 0, 0x787)
323 #define NAE_1588_PTP_INC_INTG NAE_REG(7, 0, 0x788)
324 #define NAE_1588_PTP_CONTROL NAE_REG(7, 0, 0x789)
325 #define NAE_1588_PTP_STATUS NAE_REG(7, 0, 0x78a)
326 #define NAE_1588_PTP_USER_VALUE_HI NAE_REG(7, 0, 0x78b)
327 #define NAE_1588_PTP_USER_VALUE_LO NAE_REG(7, 0, 0x78c)
328 #define NAE_1588_PTP_TMR1_HI NAE_REG(7, 0, 0x78d)
329 #define NAE_1588_PTP_TMR1_LO NAE_REG(7, 0, 0x78e)
330 #define NAE_1588_PTP_TMR2_HI NAE_REG(7, 0, 0x78f)
331 #define NAE_1588_PTP_TMR2_LO NAE_REG(7, 0, 0x790)
332 #define NAE_1588_PTP_TMR3_HI NAE_REG(7, 0, 0x791)
333 #define NAE_1588_PTP_TMR3_LO NAE_REG(7, 0, 0x792)
334 #define NAE_TX_FC_CAL_IDX_TBL_CTRL NAE_REG(7, 0, 0x793)
335 #define NAE_TX_FC_CAL_TBL_CTRL NAE_REG(7, 0, 0x794)
336 #define NAE_TX_FC_CAL_TBL_DATA0 NAE_REG(7, 0, 0x795)
337 #define NAE_TX_FC_CAL_TBL_DATA1 NAE_REG(7, 0, 0x796)
338 #define NAE_TX_FC_CAL_TBL_DATA2 NAE_REG(7, 0, 0x797)
339 #define NAE_TX_FC_CAL_TBL_DATA3 NAE_REG(7, 0, 0x798)
340 #define NAE_INT_MDIO_CTRL NAE_REG(7, 0, 0x799)
341 #define NAE_INT_MDIO_CTRL_DATA NAE_REG(7, 0, 0x79a)
342 #define NAE_INT_MDIO_RD_STAT NAE_REG(7, 0, 0x79b)
343 #define NAE_INT_MDIO_LINK_STAT NAE_REG(7, 0, 0x79c)
344 #define NAE_EXT_G0_MDIO_CTRL NAE_REG(7, 0, 0x79d)
345 #define NAE_EXT_G1_MDIO_CTRL NAE_REG(7, 0, 0x7a1)
346 #define NAE_EXT_G0_MDIO_CTRL_DATA NAE_REG(7, 0, 0x79e)
347 #define NAE_EXT_G1_MDIO_CTRL_DATA NAE_REG(7, 0, 0x7a2)
348 #define NAE_EXT_G0_MDIO_RD_STAT NAE_REG(7, 0, 0x79f)
349 #define NAE_EXT_G1_MDIO_RD_STAT NAE_REG(7, 0, 0x7a3)
350 #define NAE_EXT_G0_MDIO_LINK_STAT NAE_REG(7, 0, 0x7a0)
351 #define NAE_EXT_G1_MDIO_LINK_STAT NAE_REG(7, 0, 0x7a4)
352 #define NAE_EXT_XG0_MDIO_CTRL NAE_REG(7, 0, 0x7a5)
353 #define NAE_EXT_XG1_MDIO_CTRL NAE_REG(7, 0, 0x7a9)
354 #define NAE_EXT_XG0_MDIO_CTRL_DATA NAE_REG(7, 0, 0x7a6)
355 #define NAE_EXT_XG1_MDIO_CTRL_DATA NAE_REG(7, 0, 0x7aa)
356 #define NAE_EXT_XG0_MDIO_RD_STAT NAE_REG(7, 0, 0x7a7)
357 #define NAE_EXT_XG1_MDIO_RD_STAT NAE_REG(7, 0, 0x7ab)
358 #define NAE_EXT_XG0_MDIO_LINK_STAT NAE_REG(7, 0, 0x7a8)
359 #define NAE_EXT_XG1_MDIO_LINK_STAT NAE_REG(7, 0, 0x7ac)
360 #define NAE_GMAC_FC_SLOT0 NAE_REG(7, 0, 0x7ad)
361 #define NAE_GMAC_FC_SLOT1 NAE_REG(7, 0, 0x7ae)
362 #define NAE_GMAC_FC_SLOT2 NAE_REG(7, 0, 0x7af)
363 #define NAE_GMAC_FC_SLOT3 NAE_REG(7, 0, 0x7b0)
364 #define NAE_NETIOR_NTB_SLOT NAE_REG(7, 0, 0x7b1)
365 #define NAE_NETIOR_MISC_CTRL0 NAE_REG(7, 0, 0x7b2)
366 #define NAE_NETIOR_INT0 NAE_REG(7, 0, 0x7b3)
367 #define NAE_NETIOR_INT0_MASK NAE_REG(7, 0, 0x7b4)
368 #define NAE_NETIOR_INT1 NAE_REG(7, 0, 0x7b5)
369 #define NAE_NETIOR_INT1_MASK NAE_REG(7, 0, 0x7b6)
370 #define NAE_GMAC_PFC_REPEAT NAE_REG(7, 0, 0x7b7)
371 #define NAE_XGMAC_PFC_REPEAT NAE_REG(7, 0, 0x7b8)
372 #define NAE_NETIOR_MISC_CTRL1 NAE_REG(7, 0, 0x7b9)
373 #define NAE_NETIOR_MISC_CTRL2 NAE_REG(7, 0, 0x7ba)
374 #define NAE_NETIOR_INT2 NAE_REG(7, 0, 0x7bb)
375 #define NAE_NETIOR_INT2_MASK NAE_REG(7, 0, 0x7bc)
376 #define NAE_NETIOR_MISC_CTRL3 NAE_REG(7, 0, 0x7bd)
377
378 /* Network interface lane configuration registers */
379 #define NAE_LANE_CFG_MISCREG1 NAE_REG(7, 0xf, 0x39)
380 #define NAE_LANE_CFG_MISCREG2 NAE_REG(7, 0xf, 0x3A)
381
382 /* Network interface soft reset register */
383 #define NAE_SOFT_RESET NAE_REG(7, 0xf, 3)
384
385 /* ucore instruction/shared CAM RAM access */
386 #define NAE_UCORE_SHARED_RAM_OFFSET 0x10000
387
388 #define PORTS_PER_CMPLX 4
389 #define NAE_CACHELINE_SIZE 64
390
391 #define PHY_LANE_0_CTRL 4
392 #define PHY_LANE_1_CTRL 5
393 #define PHY_LANE_2_CTRL 6
394 #define PHY_LANE_3_CTRL 7
395
396 #define PHY_LANE_STAT_SRCS 0x00000001
397 #define PHY_LANE_STAT_STD 0x00000010
398 #define PHY_LANE_STAT_SFEA 0x00000020
399 #define PHY_LANE_STAT_STCS 0x00000040
400 #define PHY_LANE_STAT_SPC 0x00000200
401 #define PHY_LANE_STAT_XLF 0x00000400
402 #define PHY_LANE_STAT_PCR 0x00000800
403
404 #define PHY_LANE_CTRL_DATA_POS 0
405 #define PHY_LANE_CTRL_ADDR_POS 8
406 #define PHY_LANE_CTRL_CMD_READ 0x00010000
407 #define PHY_LANE_CTRL_CMD_WRITE 0x00000000
408 #define PHY_LANE_CTRL_CMD_START 0x00020000
409 #define PHY_LANE_CTRL_CMD_PENDING 0x00040000
410 #define PHY_LANE_CTRL_ALL 0x00200000
411 #define PHY_LANE_CTRL_FAST_INIT 0x00400000
412 #define PHY_LANE_CTRL_REXSEL_POS 23
413 #define PHY_LANE_CTRL_PHYMODE_POS 25
414 #define PHY_LANE_CTRL_PWRDOWN 0x20000000
415 #define PHY_LANE_CTRL_RST 0x40000000
416 #define PHY_LANE_CTRL_RST_XAUI 0xc0000000
417 #define PHY_LANE_CTRL_BPC_XAUI 0x80000000
418
419 #define LANE_CFG_CPLX_0_1 0x0
420 #define LANE_CFG_CPLX_2_3 0x1
421 #define LANE_CFG_CPLX_4 0x2
422
423 #define MAC_CONF1 0x0
424 #define MAC_CONF2 0x1
425 #define MAX_FRM 0x4
426
427 #define NETIOR_GMAC_CTRL1 0x7F
428 #define NETIOR_GMAC_CTRL2 0x7E
429 #define NETIOR_GMAC_CTRL3 0x7C
430
431 #define SGMII_CAL_SLOTS 3
432 #define XAUI_CAL_SLOTS 13
433 #define IL8_CAL_SLOTS 26
434 #define IL4_CAL_SLOTS 10
435
436 #define NAE_DRR_QUANTA 2048
437
438 #define XLP3XX_STG2_FIFO_SZ 512
439 #define XLP3XX_EH_FIFO_SZ 512
440 #define XLP3XX_FROUT_FIFO_SZ 512
441 #define XLP3XX_MS_FIFO_SZ 512
442 #define XLP3XX_PKT_FIFO_SZ 8192
443 #define XLP3XX_PKTLEN_FIFO_SZ 512
444
445 #define XLP3XX_MAX_STG2_OFFSET 0x7F
446 #define XLP3XX_MAX_EH_OFFSET 0x1f
447 #define XLP3XX_MAX_FREE_OUT_OFFSET 0x1f
448 #define XLP3XX_MAX_MS_OFFSET 0xF
449 #define XLP3XX_MAX_PMEM_OFFSET 0x7FE
450
451 #define XLP3XX_STG1_2_CREDIT XLP3XX_STG2_FIFO_SZ
452 #define XLP3XX_STG2_EH_CREDIT XLP3XX_EH_FIFO_SZ
453 #define XLP3XX_STG2_FROUT_CREDIT XLP3XX_FROUT_FIFO_SZ
454 #define XLP3XX_STG2_MS_CREDIT XLP3XX_MS_FIFO_SZ
455
456 #define XLP8XX_STG2_FIFO_SZ 2048
457 #define XLP8XX_EH_FIFO_SZ 4096
458 #define XLP8XX_FROUT_FIFO_SZ 4096
459 #define XLP8XX_MS_FIFO_SZ 2048
460 #define XLP8XX_PKT_FIFO_SZ 16384
461 #define XLP8XX_PKTLEN_FIFO_SZ 2048
462
463 #define XLP8XX_MAX_STG2_OFFSET 0x7F
464 #define XLP8XX_MAX_EH_OFFSET 0x7F
465 #define XLP8XX_MAX_FREE_OUT_OFFSET 0x7F
466 #define XLP8XX_MAX_MS_OFFSET 0x1F
467 #define XLP8XX_MAX_PMEM_OFFSET 0x7FE
468
469 #define XLP8XX_STG1_2_CREDIT XLP8XX_STG2_FIFO_SZ
470 #define XLP8XX_STG2_EH_CREDIT XLP8XX_EH_FIFO_SZ
471 #define XLP8XX_STG2_FROUT_CREDIT XLP8XX_FROUT_FIFO_SZ
472 #define XLP8XX_STG2_MS_CREDIT XLP8XX_MS_FIFO_SZ
473
474 #define MAX_CAL_SLOTS 64
475 #define XLP_MAX_PORTS 18
476 #define XLP_STORM_MAX_PORTS 8
477
478 #define MAX_FREE_FIFO_POOL_8XX 20
479 #define MAX_FREE_FIFO_POOL_3XX 9
480
481 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
482
483 #define nlm_read_nae_reg(b, r) nlm_read_reg_xkphys(b, r)
484 #define nlm_write_nae_reg(b, r, v) nlm_write_reg_xkphys(b, r, v)
485 #define nlm_get_nae_pcibase(node) \
486 nlm_pcicfg_base(XLP_IO_NAE_OFFSET(node))
487 #define nlm_get_nae_regbase(node) \
488 nlm_xkphys_map_pcibar0(nlm_get_nae_pcibase(node))
489
490 #define MAX_POE_CLASSES 8
491 #define MAX_POE_CLASS_CTXT_TBL_SZ ((NUM_CONTEXTS / MAX_POE_CLASSES) + 1)
492 #define TXINITIORCR(x) (((x) & 0x7ffff) << 8)
493
494 enum XLPNAE_TX_TYPE {
495 P2D_NEOP = 0,
496 P2P,
497 P2D_EOP,
498 MSC
499 };
500
501 enum nblock_type {
502 UNKNOWN = 0, /* DONT MAKE IT NON-ZERO */
503 SGMIIC = 1,
504 XAUIC = 2,
505 ILC = 3
506 };
507
508 enum nae_interface_type {
509 GMAC_0 = 0,
510 GMAC_1,
511 GMAC_2,
512 GMAC_3,
513 XGMAC,
514 INTERLAKEN,
515 PHY = 0xE,
516 LANE_CFG = 0xF,
517 };
518
519 enum {
520 LM_UNCONNECTED = 0,
521 LM_SGMII = 1,
522 LM_XAUI = 2,
523 LM_IL = 3,
524 };
525
526 enum nae_block {
527 BLOCK_0 = 0,
528 BLOCK_1,
529 BLOCK_2,
530 BLOCK_3,
531 BLOCK_4,
532 BLOCK_5,
533 BLOCK_6,
534 BLOCK_7,
535 };
536
537 enum {
538 PHYMODE_NONE = 0,
539 PHYMODE_HS_SGMII = 1,
540 PHYMODE_XAUI = 1,
541 PHYMODE_SGMII = 2,
542 PHYMODE_IL = 3,
543 };
544
545 static __inline int
nae_num_complex(uint64_t nae_pcibase)546 nae_num_complex(uint64_t nae_pcibase)
547 {
548 return (nlm_read_reg(nae_pcibase, XLP_PCI_DEVINFO_REG0) & 0xff);
549 }
550
551 static __inline int
nae_num_context(uint64_t nae_pcibase)552 nae_num_context(uint64_t nae_pcibase)
553 {
554 return (nlm_read_reg(nae_pcibase, XLP_PCI_DEVINFO_REG5));
555 }
556
557 /* per port config structure */
558 struct nae_port_config {
559 int node; /* node id (quickread) */
560 int block; /* network block id (quickread) */
561 int port; /* port id - among the 18 in XLP */
562 int type; /* port type - see xlp_gmac_port_types */
563 int mdio_bus;
564 int phy_addr;
565 int num_channels;
566 int num_free_descs;
567 int free_desc_sizes;
568 int ucore_mask;
569 int loopback_mode; /* is complex is in loopback? */
570 uint32_t freein_spill_size; /* Freein spill size for each port */
571 uint32_t free_fifo_size; /* (512entries x 2desc/entry)1024desc */
572 uint32_t iface_fifo_size;/* 256 entries x 64B/entry = 16KB */
573 uint32_t pseq_fifo_size; /* 1024 entries - 1 pktlen/entry */
574 uint32_t rxbuf_size; /* 4096 entries x 64B = 256KB */
575 uint32_t rx_if_base_config;
576 uint32_t rx_slots_reqd;
577 uint32_t tx_slots_reqd;
578 uint32_t stg2_fifo_size;
579 uint32_t eh_fifo_size;
580 uint32_t frout_fifo_size;
581 uint32_t ms_fifo_size;
582 uint32_t pkt_fifo_size;
583 uint32_t pktlen_fifo_size;
584 uint32_t max_stg2_offset;
585 uint32_t max_eh_offset;
586 uint32_t max_frout_offset;
587 uint32_t max_ms_offset;
588 uint32_t max_pmem_offset;
589 uint32_t stg1_2_credit;
590 uint32_t stg2_eh_credit;
591 uint32_t stg2_frout_credit;
592 uint32_t stg2_ms_credit;
593 uint32_t vlan_pri_en;
594 uint32_t txq;
595 uint32_t rxfreeq;
596 uint32_t ieee1588_inc_intg;
597 uint32_t ieee1588_inc_den;
598 uint32_t ieee1588_inc_num;
599 uint64_t ieee1588_userval;
600 uint64_t ieee1588_ptpoff;
601 uint64_t ieee1588_tmr1;
602 uint64_t ieee1588_tmr2;
603 uint64_t ieee1588_tmr3;
604 };
605
606 void nlm_nae_flush_free_fifo(uint64_t nae_base, int nblocks);
607 void nlm_program_nae_parser_seq_fifo(uint64_t, int, struct nae_port_config *);
608 void nlm_setup_rx_cal_cfg(uint64_t, int, struct nae_port_config *);
609 void nlm_setup_tx_cal_cfg(uint64_t, int, struct nae_port_config *cfg);
610 void nlm_deflate_frin_fifo_carving(uint64_t, int);
611 void nlm_reset_nae(int);
612 int nlm_set_nae_frequency(int, int);
613 void nlm_setup_poe_class_config(uint64_t nae_base, int max_poe_classes,
614 int num_contexts, int *poe_cl_tbl);
615 void nlm_setup_vfbid_mapping(uint64_t);
616 void nlm_setup_flow_crc_poly(uint64_t, uint32_t);
617 void nlm_setup_iface_fifo_cfg(uint64_t, int, struct nae_port_config *);
618 void nlm_setup_rx_base_config(uint64_t, int, struct nae_port_config *);
619 void nlm_setup_rx_buf_config(uint64_t, int, struct nae_port_config *);
620 void nlm_setup_freein_fifo_cfg(uint64_t, struct nae_port_config *);
621 int nlm_get_flow_mask(int);
622 void nlm_program_flow_cfg(uint64_t, int, uint32_t, uint32_t);
623 void xlp_ax_nae_lane_reset_txpll(uint64_t, int, int, int);
624 void xlp_nae_lane_reset_txpll(uint64_t, int, int, int);
625 void xlp_nae_config_lane_gmac(uint64_t, int);
626 void config_egress_fifo_carvings(uint64_t, int, int, int, int,
627 struct nae_port_config *);
628 void config_egress_fifo_credits(uint64_t, int, int, int, int,
629 struct nae_port_config *);
630 void nlm_config_freein_fifo_uniq_cfg(uint64_t, int, int);
631 void nlm_config_ucore_iface_mask_cfg(uint64_t, int, int);
632 int nlm_nae_init_netior(uint64_t nae_base, int nblocks);
633 void nlm_nae_init_ingress(uint64_t, uint32_t);
634 void nlm_nae_init_egress(uint64_t);
635 uint32_t ucore_spray_config(uint32_t, uint32_t, int);
636 void nlm_nae_init_ucore(uint64_t nae_base, int if_num, uint32_t ucore_mask);
637 int nlm_nae_open_if(uint64_t, int, int, int, uint32_t);
638 void nlm_mac_enable(uint64_t, int, int, int);
639 void nlm_mac_disable(uint64_t, int, int, int);
640 uint64_t nae_tx_desc(u_int, u_int, u_int, u_int, uint64_t);
641 void nlm_setup_l2type(uint64_t, int, uint32_t, uint32_t, uint32_t,
642 uint32_t, uint32_t, uint32_t);
643 void nlm_setup_l3ctable_mask(uint64_t, int, uint32_t, uint32_t);
644 void nlm_setup_l3ctable_even(uint64_t, int, uint32_t, uint32_t, uint32_t,
645 uint32_t, uint32_t);
646 void nlm_setup_l3ctable_odd(uint64_t, int, uint32_t, uint32_t, uint32_t,
647 uint32_t, uint32_t, uint32_t);
648 void nlm_setup_l4ctable_even(uint64_t, int, uint32_t, uint32_t, uint32_t,
649 uint32_t, uint32_t, uint32_t);
650 void nlm_setup_l4ctable_odd(uint64_t, int, uint32_t, uint32_t, uint32_t, uint32_t);
651 void nlm_enable_hardware_parser(uint64_t);
652 void nlm_enable_hardware_parser_per_port(uint64_t, int, int);
653 void nlm_prepad_enable(uint64_t, int);
654 void nlm_setup_1588_timer(uint64_t, struct nae_port_config *);
655
656 #endif /* !(LOCORE) && !(__ASSEMBLY__) */
657
658 #endif
659