1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (C) 2020 Marvell International Ltd. 3 */ 4 5 #ifndef _OTX2_REGEXDEV_HW_ACCESS_H_ 6 #define _OTX2_REGEXDEV_HW_ACCESS_H_ 7 8 #include <stdint.h> 9 10 #include "otx2_regexdev.h" 11 12 /* REE instruction queue length */ 13 #define OTX2_REE_IQ_LEN (1 << 13) 14 15 #define OTX2_REE_DEFAULT_CMD_QLEN OTX2_REE_IQ_LEN 16 17 /* Status register bits */ 18 #define OTX2_REE_STATUS_PMI_EOJ_BIT (1 << 14) 19 #define OTX2_REE_STATUS_PMI_SOJ_BIT (1 << 13) 20 #define OTX2_REE_STATUS_MP_CNT_DET_BIT (1 << 7) 21 #define OTX2_REE_STATUS_MM_CNT_DET_BIT (1 << 6) 22 #define OTX2_REE_STATUS_ML_CNT_DET_BIT (1 << 5) 23 #define OTX2_REE_STATUS_MST_CNT_DET_BIT (1 << 4) 24 #define OTX2_REE_STATUS_MPT_CNT_DET_BIT (1 << 3) 25 26 /* Register offsets */ 27 /* REE LF registers */ 28 #define OTX2_REE_LF_DONE_INT 0x120ull 29 #define OTX2_REE_LF_DONE_INT_W1S 0x130ull 30 #define OTX2_REE_LF_DONE_INT_ENA_W1S 0x138ull 31 #define OTX2_REE_LF_DONE_INT_ENA_W1C 0x140ull 32 #define OTX2_REE_LF_MISC_INT 0x300ull 33 #define OTX2_REE_LF_MISC_INT_W1S 0x310ull 34 #define OTX2_REE_LF_MISC_INT_ENA_W1S 0x320ull 35 #define OTX2_REE_LF_MISC_INT_ENA_W1C 0x330ull 36 #define OTX2_REE_LF_ENA 0x10ull 37 #define OTX2_REE_LF_SBUF_ADDR 0x20ull 38 #define OTX2_REE_LF_DONE 0x100ull 39 #define OTX2_REE_LF_DONE_ACK 0x110ull 40 #define OTX2_REE_LF_DONE_WAIT 0x148ull 41 #define OTX2_REE_LF_DOORBELL 0x400ull 42 #define OTX2_REE_LF_OUTSTAND_JOB 0x410ull 43 44 /* BAR 0 */ 45 #define OTX2_REE_AF_QUE_SBUF_CTL(a) (0x1200ull | (uint64_t)(a) << 3) 46 #define OTX2_REE_PRIV_LF_CFG(a) (0x41000ull | (uint64_t)(a) << 3) 47 48 #define OTX2_REE_LF_BAR2(vf, q_id) \ 49 ((vf)->otx2_dev.bar2 + \ 50 (((vf)->block_address << 20) | ((q_id) << 12))) 51 52 53 #define OTX2_REE_QUEUE_HI_PRIO 0x1 54 55 enum ree_desc_type_e { 56 REE_TYPE_JOB_DESC = 0x0, 57 REE_TYPE_RESULT_DESC = 0x1, 58 REE_TYPE_ENUM_LAST = 0x2 59 }; 60 61 union otx2_ree_priv_lf_cfg { 62 uint64_t u; 63 struct { 64 uint64_t slot : 8; 65 uint64_t pf_func : 16; 66 uint64_t reserved_24_62 : 39; 67 uint64_t ena : 1; 68 } s; 69 }; 70 71 72 union otx2_ree_lf_sbuf_addr { 73 uint64_t u; 74 struct { 75 uint64_t off : 7; 76 uint64_t ptr : 46; 77 uint64_t reserved_53_63 : 11; 78 } s; 79 }; 80 81 union otx2_ree_lf_ena { 82 uint64_t u; 83 struct { 84 uint64_t ena : 1; 85 uint64_t reserved_1_63 : 63; 86 } s; 87 }; 88 89 union otx2_ree_af_reexm_max_match { 90 uint64_t u; 91 struct { 92 uint64_t max : 8; 93 uint64_t reserved_8_63 : 56; 94 } s; 95 }; 96 97 union otx2_ree_lf_done { 98 uint64_t u; 99 struct { 100 uint64_t done : 20; 101 uint64_t reserved_20_63 : 44; 102 } s; 103 }; 104 105 union otx2_ree_inst { 106 uint64_t u[8]; 107 struct { 108 uint64_t doneint : 1; 109 uint64_t reserved_1_3 : 3; 110 uint64_t dg : 1; 111 uint64_t reserved_5_7 : 3; 112 uint64_t ooj : 1; 113 uint64_t reserved_9_15 : 7; 114 uint64_t reserved_16_63 : 48; 115 uint64_t inp_ptr_addr : 64; 116 uint64_t inp_ptr_ctl : 64; 117 uint64_t res_ptr_addr : 64; 118 uint64_t wq_ptr : 64; 119 uint64_t tag : 32; 120 uint64_t tt : 2; 121 uint64_t ggrp : 10; 122 uint64_t reserved_364_383 : 20; 123 uint64_t reserved_384_391 : 8; 124 uint64_t ree_job_id : 24; 125 uint64_t ree_job_ctrl : 16; 126 uint64_t ree_job_length : 15; 127 uint64_t reserved_447_447 : 1; 128 uint64_t ree_job_subset_id_0 : 16; 129 uint64_t ree_job_subset_id_1 : 16; 130 uint64_t ree_job_subset_id_2 : 16; 131 uint64_t ree_job_subset_id_3 : 16; 132 } cn98xx; 133 }; 134 135 union otx2_ree_res_status { 136 uint64_t u; 137 struct { 138 uint64_t job_type : 3; 139 uint64_t mpt_cnt_det : 1; 140 uint64_t mst_cnt_det : 1; 141 uint64_t ml_cnt_det : 1; 142 uint64_t mm_cnt_det : 1; 143 uint64_t mp_cnt_det : 1; 144 uint64_t mode : 2; 145 uint64_t reserved_10_11 : 2; 146 uint64_t reserved_12_12 : 1; 147 uint64_t pmi_soj : 1; 148 uint64_t pmi_eoj : 1; 149 uint64_t reserved_15_15 : 1; 150 uint64_t reserved_16_63 : 48; 151 } s; 152 }; 153 154 union otx2_ree_res { 155 uint64_t u[8]; 156 struct ree_res_s_98 { 157 uint64_t done : 1; 158 uint64_t hwjid : 7; 159 uint64_t ree_res_job_id : 24; 160 uint64_t ree_res_status : 16; 161 uint64_t ree_res_dmcnt : 8; 162 uint64_t ree_res_mcnt : 8; 163 uint64_t ree_meta_ptcnt : 16; 164 uint64_t ree_meta_icnt : 16; 165 uint64_t ree_meta_lcnt : 16; 166 uint64_t ree_pmi_min_byte_ptr : 16; 167 uint64_t ree_err : 1; 168 uint64_t reserved_129_190 : 62; 169 uint64_t doneint : 1; 170 uint64_t reserved_192_255 : 64; 171 uint64_t reserved_256_319 : 64; 172 uint64_t reserved_320_383 : 64; 173 uint64_t reserved_384_447 : 64; 174 uint64_t reserved_448_511 : 64; 175 } s; 176 }; 177 178 union otx2_ree_match { 179 uint64_t u; 180 struct { 181 uint64_t ree_rule_id : 32; 182 uint64_t start_ptr : 14; 183 uint64_t reserved_46_47 : 2; 184 uint64_t match_length : 15; 185 uint64_t reserved_63_63 : 1; 186 } s; 187 }; 188 189 void otx2_ree_err_intr_unregister(const struct rte_regexdev *dev); 190 191 int otx2_ree_err_intr_register(const struct rte_regexdev *dev); 192 193 int otx2_ree_iq_enable(const struct rte_regexdev *dev, 194 const struct otx2_ree_qp *qp, 195 uint8_t pri, uint32_t size_div128); 196 197 void otx2_ree_iq_disable(struct otx2_ree_qp *qp); 198 199 int otx2_ree_max_matches_get(const struct rte_regexdev *dev, 200 uint8_t *max_matches); 201 202 #endif /* _OTX2_REGEXDEV_HW_ACCESS_H_ */ 203