1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the SelectionDAGISel class, which is used as the common 11 // base class for SelectionDAG-based instruction selectors. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H 16 #define LLVM_CODEGEN_SELECTIONDAGISEL_H 17 18 #include "llvm/CodeGen/MachineFunctionPass.h" 19 #include "llvm/CodeGen/SelectionDAG.h" 20 #include "llvm/CodeGen/TargetSubtargetInfo.h" 21 #include "llvm/IR/BasicBlock.h" 22 #include "llvm/Pass.h" 23 #include <memory> 24 25 namespace llvm { 26 class FastISel; 27 class SelectionDAGBuilder; 28 class SDValue; 29 class MachineRegisterInfo; 30 class MachineBasicBlock; 31 class MachineFunction; 32 class MachineInstr; 33 class OptimizationRemarkEmitter; 34 class TargetLowering; 35 class TargetLibraryInfo; 36 class FunctionLoweringInfo; 37 class ScheduleHazardRecognizer; 38 class GCFunctionInfo; 39 class ScheduleDAGSDNodes; 40 class LoadInst; 41 42 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based 43 /// pattern-matching instruction selectors. 44 class SelectionDAGISel : public MachineFunctionPass { 45 public: 46 TargetMachine &TM; 47 const TargetLibraryInfo *LibInfo; 48 FunctionLoweringInfo *FuncInfo; 49 MachineFunction *MF; 50 MachineRegisterInfo *RegInfo; 51 SelectionDAG *CurDAG; 52 SelectionDAGBuilder *SDB; 53 AliasAnalysis *AA; 54 GCFunctionInfo *GFI; 55 CodeGenOpt::Level OptLevel; 56 const TargetInstrInfo *TII; 57 const TargetLowering *TLI; 58 bool FastISelFailed; 59 SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs; 60 61 /// Current optimization remark emitter. 62 /// Used to report things like combines and FastISel failures. 63 std::unique_ptr<OptimizationRemarkEmitter> ORE; 64 65 static char ID; 66 67 explicit SelectionDAGISel(TargetMachine &tm, 68 CodeGenOpt::Level OL = CodeGenOpt::Default); 69 ~SelectionDAGISel() override; 70 getTargetLowering()71 const TargetLowering *getTargetLowering() const { return TLI; } 72 73 void getAnalysisUsage(AnalysisUsage &AU) const override; 74 75 bool runOnMachineFunction(MachineFunction &MF) override; 76 EmitFunctionEntryCode()77 virtual void EmitFunctionEntryCode() {} 78 79 /// PreprocessISelDAG - This hook allows targets to hack on the graph before 80 /// instruction selection starts. PreprocessISelDAG()81 virtual void PreprocessISelDAG() {} 82 83 /// PostprocessISelDAG() - This hook allows the target to hack on the graph 84 /// right after selection. PostprocessISelDAG()85 virtual void PostprocessISelDAG() {} 86 87 /// Main hook for targets to transform nodes into machine nodes. 88 virtual void Select(SDNode *N) = 0; 89 90 /// SelectInlineAsmMemoryOperand - Select the specified address as a target 91 /// addressing mode, according to the specified constraint. If this does 92 /// not match or is not implemented, return true. The resultant operands 93 /// (which will appear in the machine instruction) should be added to the 94 /// OutOps vector. SelectInlineAsmMemoryOperand(const SDValue & Op,unsigned ConstraintID,std::vector<SDValue> & OutOps)95 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 96 unsigned ConstraintID, 97 std::vector<SDValue> &OutOps) { 98 return true; 99 } 100 101 /// IsProfitableToFold - Returns true if it's profitable to fold the specific 102 /// operand node N of U during instruction selection that starts at Root. 103 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const; 104 105 /// IsLegalToFold - Returns true if the specific operand node N of 106 /// U can be folded during instruction selection that starts at Root. 107 /// FIXME: This is a static member function because the MSP430/X86 108 /// targets, which uses it during isel. This could become a proper member. 109 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 110 CodeGenOpt::Level OptLevel, 111 bool IgnoreChains = false); 112 113 static void InvalidateNodeId(SDNode *N); 114 static int getUninvalidatedNodeId(SDNode *N); 115 116 static void EnforceNodeIdInvariant(SDNode *N); 117 118 // Opcodes used by the DAG state machine: 119 enum BuiltinOpcodes { 120 OPC_Scope, 121 OPC_RecordNode, 122 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3, 123 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7, 124 OPC_RecordMemRef, 125 OPC_CaptureGlueInput, 126 OPC_MoveChild, 127 OPC_MoveChild0, OPC_MoveChild1, OPC_MoveChild2, OPC_MoveChild3, 128 OPC_MoveChild4, OPC_MoveChild5, OPC_MoveChild6, OPC_MoveChild7, 129 OPC_MoveParent, 130 OPC_CheckSame, 131 OPC_CheckChild0Same, OPC_CheckChild1Same, 132 OPC_CheckChild2Same, OPC_CheckChild3Same, 133 OPC_CheckPatternPredicate, 134 OPC_CheckPredicate, 135 OPC_CheckPredicateWithOperands, 136 OPC_CheckOpcode, 137 OPC_SwitchOpcode, 138 OPC_CheckType, 139 OPC_CheckTypeRes, 140 OPC_SwitchType, 141 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type, 142 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type, 143 OPC_CheckChild6Type, OPC_CheckChild7Type, 144 OPC_CheckInteger, 145 OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer, 146 OPC_CheckChild3Integer, OPC_CheckChild4Integer, 147 OPC_CheckCondCode, 148 OPC_CheckValueType, 149 OPC_CheckComplexPat, 150 OPC_CheckAndImm, OPC_CheckOrImm, 151 OPC_CheckFoldableChainNode, 152 153 OPC_EmitInteger, 154 OPC_EmitRegister, 155 OPC_EmitRegister2, 156 OPC_EmitConvertToTarget, 157 OPC_EmitMergeInputChains, 158 OPC_EmitMergeInputChains1_0, 159 OPC_EmitMergeInputChains1_1, 160 OPC_EmitMergeInputChains1_2, 161 OPC_EmitCopyToReg, 162 OPC_EmitNodeXForm, 163 OPC_EmitNode, 164 // Space-optimized forms that implicitly encode number of result VTs. 165 OPC_EmitNode0, OPC_EmitNode1, OPC_EmitNode2, 166 OPC_MorphNodeTo, 167 // Space-optimized forms that implicitly encode number of result VTs. 168 OPC_MorphNodeTo0, OPC_MorphNodeTo1, OPC_MorphNodeTo2, 169 OPC_CompleteMatch, 170 // Contains offset in table for pattern being selected 171 OPC_Coverage 172 }; 173 174 enum { 175 OPFL_None = 0, // Node has no chain or glue input and isn't variadic. 176 OPFL_Chain = 1, // Node has a chain input. 177 OPFL_GlueInput = 2, // Node has a glue input. 178 OPFL_GlueOutput = 4, // Node has a glue output. 179 OPFL_MemRefs = 8, // Node gets accumulated MemRefs. 180 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs. 181 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs. 182 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs. 183 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs. 184 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs. 185 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs. 186 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs. 187 188 OPFL_VariadicInfo = OPFL_Variadic6 189 }; 190 191 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the 192 /// number of fixed arity values that should be skipped when copying from the 193 /// root. getNumFixedFromVariadicInfo(unsigned Flags)194 static inline int getNumFixedFromVariadicInfo(unsigned Flags) { 195 return ((Flags&OPFL_VariadicInfo) >> 4)-1; 196 } 197 198 199 protected: 200 /// DAGSize - Size of DAG being instruction selected. 201 /// 202 unsigned DAGSize; 203 204 /// ReplaceUses - replace all uses of the old node F with the use 205 /// of the new node T. ReplaceUses(SDValue F,SDValue T)206 void ReplaceUses(SDValue F, SDValue T) { 207 CurDAG->ReplaceAllUsesOfValueWith(F, T); 208 EnforceNodeIdInvariant(T.getNode()); 209 } 210 211 /// ReplaceUses - replace all uses of the old nodes F with the use 212 /// of the new nodes T. ReplaceUses(const SDValue * F,const SDValue * T,unsigned Num)213 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) { 214 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num); 215 for (unsigned i = 0; i < Num; ++i) 216 EnforceNodeIdInvariant(T[i].getNode()); 217 } 218 219 /// ReplaceUses - replace all uses of the old node F with the use 220 /// of the new node T. ReplaceUses(SDNode * F,SDNode * T)221 void ReplaceUses(SDNode *F, SDNode *T) { 222 CurDAG->ReplaceAllUsesWith(F, T); 223 EnforceNodeIdInvariant(T); 224 } 225 226 /// Replace all uses of \c F with \c T, then remove \c F from the DAG. ReplaceNode(SDNode * F,SDNode * T)227 void ReplaceNode(SDNode *F, SDNode *T) { 228 CurDAG->ReplaceAllUsesWith(F, T); 229 EnforceNodeIdInvariant(T); 230 CurDAG->RemoveDeadNode(F); 231 } 232 233 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 234 /// by tblgen. Others should not call it. 235 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, 236 const SDLoc &DL); 237 238 /// getPatternForIndex - Patterns selected by tablegen during ISEL getPatternForIndex(unsigned index)239 virtual StringRef getPatternForIndex(unsigned index) { 240 llvm_unreachable("Tblgen should generate the implementation of this!"); 241 } 242 243 /// getIncludePathForIndex - get the td source location of pattern instantiation getIncludePathForIndex(unsigned index)244 virtual StringRef getIncludePathForIndex(unsigned index) { 245 llvm_unreachable("Tblgen should generate the implementation of this!"); 246 } 247 public: 248 // Calls to these predicates are generated by tblgen. 249 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 250 int64_t DesiredMaskS) const; 251 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 252 int64_t DesiredMaskS) const; 253 254 255 /// CheckPatternPredicate - This function is generated by tblgen in the 256 /// target. It runs the specified pattern predicate and returns true if it 257 /// succeeds or false if it fails. The number is a private implementation 258 /// detail to the code tblgen produces. CheckPatternPredicate(unsigned PredNo)259 virtual bool CheckPatternPredicate(unsigned PredNo) const { 260 llvm_unreachable("Tblgen should generate the implementation of this!"); 261 } 262 263 /// CheckNodePredicate - This function is generated by tblgen in the target. 264 /// It runs node predicate number PredNo and returns true if it succeeds or 265 /// false if it fails. The number is a private implementation 266 /// detail to the code tblgen produces. CheckNodePredicate(SDNode * N,unsigned PredNo)267 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const { 268 llvm_unreachable("Tblgen should generate the implementation of this!"); 269 } 270 271 /// CheckNodePredicateWithOperands - This function is generated by tblgen in 272 /// the target. 273 /// It runs node predicate number PredNo and returns true if it succeeds or 274 /// false if it fails. The number is a private implementation detail to the 275 /// code tblgen produces. CheckNodePredicateWithOperands(SDNode * N,unsigned PredNo,const SmallVectorImpl<SDValue> & Operands)276 virtual bool CheckNodePredicateWithOperands( 277 SDNode *N, unsigned PredNo, 278 const SmallVectorImpl<SDValue> &Operands) const { 279 llvm_unreachable("Tblgen should generate the implementation of this!"); 280 } 281 CheckComplexPattern(SDNode * Root,SDNode * Parent,SDValue N,unsigned PatternNo,SmallVectorImpl<std::pair<SDValue,SDNode * >> & Result)282 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, 283 unsigned PatternNo, 284 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) { 285 llvm_unreachable("Tblgen should generate the implementation of this!"); 286 } 287 RunSDNodeXForm(SDValue V,unsigned XFormNo)288 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) { 289 llvm_unreachable("Tblgen should generate this!"); 290 } 291 292 void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 293 unsigned TableSize); 294 295 /// Return true if complex patterns for this target can mutate the 296 /// DAG. ComplexPatternFuncMutatesDAG()297 virtual bool ComplexPatternFuncMutatesDAG() const { 298 return false; 299 } 300 301 bool isOrEquivalentToAdd(const SDNode *N) const; 302 303 private: 304 305 // Calls to these functions are generated by tblgen. 306 void Select_INLINEASM(SDNode *N); 307 void Select_READ_REGISTER(SDNode *Op); 308 void Select_WRITE_REGISTER(SDNode *Op); 309 void Select_UNDEF(SDNode *N); 310 void CannotYetSelect(SDNode *N); 311 312 private: 313 void DoInstructionSelection(); 314 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 315 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo); 316 317 SDNode *MutateStrictFPToFP(SDNode *Node, unsigned NewOpc); 318 319 /// Prepares the landing pad to take incoming values or do other EH 320 /// personality specific tasks. Returns true if the block should be 321 /// instruction selected, false if no code should be emitted for it. 322 bool PrepareEHLandingPad(); 323 324 /// Perform instruction selection on all basic blocks in the function. 325 void SelectAllBasicBlocks(const Function &Fn); 326 327 /// Perform instruction selection on a single basic block, for 328 /// instructions between \p Begin and \p End. \p HadTailCall will be set 329 /// to true if a call in the block was translated as a tail call. 330 void SelectBasicBlock(BasicBlock::const_iterator Begin, 331 BasicBlock::const_iterator End, 332 bool &HadTailCall); 333 void FinishBasicBlock(); 334 335 void CodeGenAndEmitDAG(); 336 337 /// Generate instructions for lowering the incoming arguments of the 338 /// given function. 339 void LowerArguments(const Function &F); 340 341 void ComputeLiveOutVRegInfo(); 342 343 /// Create the scheduler. If a specific scheduler was specified 344 /// via the SchedulerRegistry, use it, otherwise select the 345 /// one preferred by the target. 346 /// 347 ScheduleDAGSDNodes *CreateScheduler(); 348 349 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel 350 /// state machines that start with a OPC_SwitchOpcode node. 351 std::vector<unsigned> OpcodeOffset; 352 353 void UpdateChains(SDNode *NodeToMatch, SDValue InputChain, 354 SmallVectorImpl<SDNode *> &ChainNodesMatched, 355 bool isMorphNodeTo); 356 }; 357 358 } 359 360 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */ 361