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Searched defs:NumIntermediates (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1089 unsigned &NumIntermediates, in getVectorTypeBreakdownMVT()
1467 unsigned NumIntermediates; in computeRegisterProperties() local
1534 unsigned &NumIntermediates, in getVectorTypeBreakdown()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h1025 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
1528 unsigned NumIntermediates; in getRegisterType() local
1561 unsigned NumIntermediates; variable
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp119 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp335 unsigned NumIntermediates; in getCopyFromPartsVector() local
702 unsigned NumIntermediates; in getCopyToPartsVector() local
H A DSelectionDAG.cpp2270 unsigned NumIntermediates; in getReducedAlign() local
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp870 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2543 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()