| /freebsd-14.2/contrib/llvm-project/clang/include/clang/Analysis/Analyses/ |
| H A D | ThreadSafetyLogical.h | 27 Not enumerator
86 Not(LExpr *Exp) : LExpr(LExpr::Not), Exp(Exp) {} in Not() function
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| /freebsd-14.2/contrib/llvm-project/clang/include/clang/Analysis/FlowSensitive/ |
| H A D | Formula.h | 58 Not, /// True if its only operand is false in alignas() enumerator
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFastISel.cpp | 424 bool &Not) { in getRegForI1Value()
912 bool Not; in selectSelect() local
1100 bool Not = false; in selectFCmp() local
1313 bool Not; in selectBr() local
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| /freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CompressInstEmitter.cpp | 692 StringRef Not = Op.first ? "!" : ""; in emitCompressInstEmitter() local
703 StringRef Not = Op.first ? "!" : ""; in emitCompressInstEmitter() local
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAddSub.cpp | 1626 Value *Not = Builder.CreateXor(A, AllOnes); in visitAdd() local
2522 Value *Not = Builder.CreateNot(Op1); in visitSub() local
2528 Value *Not = Builder.CreateNot(Op0); in visitSub() local
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| H A D | InstCombineAndOrXor.cpp | 3621 Value *Not = Builder.CreateNot(NotOp, NotOp->getName() + ".not"); in visitOr() local
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCExpr.h | 433 Not, ///< Bitwise negation. enumerator
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanTransforms.cpp | 558 VPInstruction *Not = dyn_cast<VPInstruction>(Term->getOperand(0)); in canSimplifyBranchOnCond() local
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| H A D | VPlan.h | 1134 Not, enumerator
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 582 auto Not = [&](auto V) -> std::pair<Value *, uint8_t> { in simplifyTernarylogic() local
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| H A D | X86ISelLowering.cpp | 4983 if (SDValue Not = IsNOT(V.getOperand(0), DAG)) { in IsNOT() local
30201 bool Not = false; in FindSingleBitChange() local
47827 if (SDValue Not = IsNOT(N0, DAG)) { in combineAndNotIntoANDNP() local
47830 } else if (SDValue Not = IsNOT(N1, DAG)) { in combineAndNotIntoANDNP() local
47875 if (SDValue Not = IsNOT(Src, DAG)) { in combineAndShuffleNot() local
47891 if (SDValue Not = GetNot(N0)) { in combineAndShuffleNot() local
47894 } else if (SDValue Not = GetNot(N1)) { in combineAndShuffleNot() local
52210 if (SDValue Not = IsNOT(N0, DAG)) in combineAndnp() local
52216 if (SDValue Not = IsNOT(N1, DAG)) in combineAndnp() local
52239 SDValue Not = getConstVector(EltBits0, VT, DAG, DL); in combineAndnp() local
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 2599 SDValue Not = in lowerShiftLeftParts() local
2638 SDValue Not = in lowerShiftRightParts() local
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 1616 SDValue Not = TLO.DAG.getNOT(dl, Op0.getOperand(0), VT); in SimplifyDemandedBits() local
5207 SDValue Not = DAG.getNOT(dl, N1, OpVT); in SimplifySetCC() local
8935 SDValue Not = DAG.getNode(ISD::VP_XOR, dl, VT, Op, in expandVPCTTZ() local
10066 SDValue Not = DAG.getNOT(dl, OverflowMask, VT); in expandAddSubSat() local
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| H A D | DAGCombiner.cpp | 2679 SDValue Not = ShiftOp.getOperand(0); in foldAddSubOfSignBit() local
2777 SDValue Not = DAG.getNOT(DL, X, X.getValueType()); in visitADDLike() local
2940 SDValue Not = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0), in visitADDLike() local
3166 SDValue Not = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0), in visitADDLikeCommutative() local
11516 SDValue Not = DAG.getNOT(DL, Sra, VT); in foldVSelectToSignBitSplatMask() local
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| H A D | SelectionDAG.cpp | 5389 if (SDValue NotOperand = in haveNoCommonBitsSetCommutative()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 7581 MachineInstr *Not = in lowerScalarXnor() local
7613 MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest) in splitScalarNotBinop() local
7638 MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Interm) in splitScalarBinOpN2() local
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| H A D | AMDGPUISelLowering.cpp | 2392 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64); in LowerFTRUNC() local
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| H A D | AMDGPULegalizerInfo.cpp | 2446 auto Not = B.buildNot(S64, Shr); in legalizeIntrinsicTrunc() local
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 2606 MachineSDNode *Not = in selectShiftMask() local
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 3395 auto Not = Builder.buildNot(MRI.getType(X), X); in applyXorOfAndWithSameReg() local
6466 Register Not = MRI.createGenericVirtualRegister(CondTy); in tryFoldSelectOfConstants() local
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| H A D | LegalizerHelper.cpp | 7551 Register Not = IsAdd ? MIRBuilder.buildNot(Ty, LHS).getReg(0) : LHS; in lowerAddSubSatToMinMax() local
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 3662 MachineSDNode *Not = in tryShiftAmountMod() local
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