1 //===---------------------- InOrderIssueStage.h -----------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// InOrderIssueStage implements an in-order execution pipeline.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_MCA_STAGES_INORDERISSUESTAGE_H
15 #define LLVM_MCA_STAGES_INORDERISSUESTAGE_H
16 
17 #include "llvm/MCA/CustomBehaviour.h"
18 #include "llvm/MCA/HardwareUnits/ResourceManager.h"
19 #include "llvm/MCA/SourceMgr.h"
20 #include "llvm/MCA/Stages/Stage.h"
21 
22 namespace llvm {
23 namespace mca {
24 class RegisterFile;
25 
26 struct StallInfo {
27   enum class StallKind {
28     DEFAULT,
29     REGISTER_DEPS,
30     DISPATCH,
31     DELAY,
32     CUSTOM_STALL
33   };
34 
35   InstRef IR;
36   unsigned CyclesLeft;
37   StallKind Kind;
38 
StallInfoStallInfo39   StallInfo() : IR(), CyclesLeft(), Kind(StallKind::DEFAULT) {}
40 
getStallKindStallInfo41   StallKind getStallKind() const { return Kind; }
getCyclesLeftStallInfo42   unsigned getCyclesLeft() const { return CyclesLeft; }
getInstructionStallInfo43   const InstRef &getInstruction() const { return IR; }
getInstructionStallInfo44   InstRef &getInstruction() { return IR; }
45 
isValidStallInfo46   bool isValid() const { return (bool)IR; }
47   void clear();
48   void update(const InstRef &Inst, unsigned Cycles, StallKind SK);
49   void cycleEnd();
50 };
51 
52 class InOrderIssueStage final : public Stage {
53   const MCSubtargetInfo &STI;
54   RegisterFile &PRF;
55   ResourceManager RM;
56   CustomBehaviour &CB;
57 
58   /// Instructions that were issued, but not executed yet.
59   SmallVector<InstRef, 4> IssuedInst;
60 
61   /// Number of instructions issued in the current cycle.
62   unsigned NumIssued;
63 
64   StallInfo SI;
65 
66   /// Instruction that is issued in more than 1 cycle.
67   InstRef CarriedOver;
68   /// Number of CarriedOver uops left to issue.
69   unsigned CarryOver;
70 
71   /// Number of instructions that can be issued in the current cycle.
72   unsigned Bandwidth;
73 
74   /// Number of cycles (counted from the current cycle) until the last write is
75   /// committed. This is taken into account to ensure that writes commit in the
76   /// program order.
77   unsigned LastWriteBackCycle;
78 
79   InOrderIssueStage(const InOrderIssueStage &Other) = delete;
80   InOrderIssueStage &operator=(const InOrderIssueStage &Other) = delete;
81 
82   /// Returns true if IR can execute during this cycle.
83   /// In case of stall, it updates SI with information about the stalled
84   /// instruction and the stall reason.
85   bool canExecute(const InstRef &IR);
86 
87   /// Issue the instruction, or update the StallInfo.
88   Error tryIssue(InstRef &IR);
89 
90   /// Update status of instructions from IssuedInst.
91   void updateIssuedInst();
92 
93   /// Continue to issue the CarriedOver instruction.
94   void updateCarriedOver();
95 
96   /// Notifies a stall event to the Stage listener. Stall information is
97   /// obtained from the internal StallInfo field.
98   void notifyStallEvent();
99 
100   void notifyInstructionIssued(const InstRef &IR,
101                                ArrayRef<ResourceUse> UsedRes);
102   void notifyInstructionDispatched(const InstRef &IR, unsigned Ops,
103                                    ArrayRef<unsigned> UsedRegs);
104   void notifyInstructionExecuted(const InstRef &IR);
105   void notifyInstructionRetired(const InstRef &IR,
106                                 ArrayRef<unsigned> FreedRegs);
107 
108   /// Retire instruction once it is executed.
109   void retireInstruction(InstRef &IR);
110 
111 public:
112   InOrderIssueStage(const MCSubtargetInfo &STI, RegisterFile &PRF,
113                     CustomBehaviour &CB);
114 
115   unsigned getIssueWidth() const;
116   bool isAvailable(const InstRef &) const override;
117   bool hasWorkToComplete() const override;
118   Error execute(InstRef &IR) override;
119   Error cycleStart() override;
120   Error cycleEnd() override;
121 };
122 
123 } // namespace mca
124 } // namespace llvm
125 
126 #endif // LLVM_MCA_STAGES_INORDERISSUESTAGE_H
127