1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #ifndef _LIO_HW_DEFS_H_ 6 #define _LIO_HW_DEFS_H_ 7 8 #include <rte_io.h> 9 10 #ifndef PCI_VENDOR_ID_CAVIUM 11 #define PCI_VENDOR_ID_CAVIUM 0x177D 12 #endif 13 14 #define LIO_CN23XX_VF_VID 0x9712 15 16 /* CN23xx subsystem device ids */ 17 #define PCI_SUBSYS_DEV_ID_CN2350_210 0x0004 18 #define PCI_SUBSYS_DEV_ID_CN2360_210 0x0005 19 #define PCI_SUBSYS_DEV_ID_CN2360_225 0x0006 20 #define PCI_SUBSYS_DEV_ID_CN2350_225 0x0007 21 #define PCI_SUBSYS_DEV_ID_CN2350_210SVPN3 0x0008 22 #define PCI_SUBSYS_DEV_ID_CN2360_210SVPN3 0x0009 23 #define PCI_SUBSYS_DEV_ID_CN2350_210SVPT 0x000a 24 #define PCI_SUBSYS_DEV_ID_CN2360_210SVPT 0x000b 25 26 /* --------------------------CONFIG VALUES------------------------ */ 27 28 /* CN23xx IQ configuration macros */ 29 #define CN23XX_MAX_RINGS_PER_PF 64 30 #define CN23XX_MAX_RINGS_PER_VF 8 31 32 #define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF 33 #define CN23XX_MAX_IQ_DESCRIPTORS 512 34 #define CN23XX_MIN_IQ_DESCRIPTORS 128 35 36 #define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF 37 #define CN23XX_MAX_OQ_DESCRIPTORS 512 38 #define CN23XX_MIN_OQ_DESCRIPTORS 128 39 #define CN23XX_OQ_BUF_SIZE 1536 40 41 #define CN23XX_OQ_REFIL_THRESHOLD 16 42 43 #define CN23XX_DEFAULT_NUM_PORTS 1 44 45 #define CN23XX_CFG_IO_QUEUES CN23XX_MAX_RINGS_PER_PF 46 47 /* common OCTEON configuration macros */ 48 #define OCTEON_64BYTE_INSTR 64 49 #define OCTEON_OQ_INFOPTR_MODE 1 50 51 /* Max IOQs per LIO Link */ 52 #define LIO_MAX_IOQS_PER_IF 64 53 54 /* Wait time in milliseconds for FLR */ 55 #define LIO_PCI_FLR_WAIT 100 56 57 enum lio_card_type { 58 LIO_23XX /* 23xx */ 59 }; 60 61 #define LIO_23XX_NAME "23xx" 62 63 #define LIO_DEV_RUNNING 0xc 64 65 #define LIO_OQ_REFILL_THRESHOLD_CFG(cfg) \ 66 ((cfg)->default_config->oq.refill_threshold) 67 #define LIO_NUM_DEF_TX_DESCS_CFG(cfg) \ 68 ((cfg)->default_config->num_def_tx_descs) 69 70 #define LIO_IQ_INSTR_TYPE(cfg) ((cfg)->default_config->iq.instr_type) 71 72 /* The following config values are fixed and should not be modified. */ 73 74 /* Maximum number of Instruction queues */ 75 #define LIO_MAX_INSTR_QUEUES(lio_dev) CN23XX_MAX_RINGS_PER_VF 76 77 #define LIO_MAX_POSSIBLE_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES 78 #define LIO_MAX_POSSIBLE_OUTPUT_QUEUES CN23XX_MAX_OUTPUT_QUEUES 79 80 #define LIO_DEVICE_NAME_LEN 32 81 #define LIO_BASE_MAJOR_VERSION 1 82 #define LIO_BASE_MINOR_VERSION 5 83 #define LIO_BASE_MICRO_VERSION 1 84 85 #define LIO_FW_VERSION_LENGTH 32 86 87 #define LIO_Q_RECONF_MIN_VERSION "1.7.0" 88 #define LIO_VF_TRUST_MIN_VERSION "1.7.1" 89 90 /** Tag types used by Octeon cores in its work. */ 91 enum octeon_tag_type { 92 OCTEON_ORDERED_TAG = 0, 93 OCTEON_ATOMIC_TAG = 1, 94 }; 95 96 /* pre-defined host->NIC tag values */ 97 #define LIO_CONTROL (0x11111110) 98 #define LIO_DATA(i) (0x11111111 + (i)) 99 100 /* used for NIC operations */ 101 #define LIO_OPCODE 1 102 103 /* Subcodes are used by host driver/apps to identify the sub-operation 104 * for the core. They only need to by unique for a given subsystem. 105 */ 106 #define LIO_OPCODE_SUBCODE(op, sub) \ 107 ((((op) & 0x0f) << 8) | ((sub) & 0x7f)) 108 109 /** LIO_OPCODE subcodes */ 110 /* This subcode is sent by core PCI driver to indicate cores are ready. */ 111 #define LIO_OPCODE_NW_DATA 0x02 /* network packet data */ 112 #define LIO_OPCODE_CMD 0x03 113 #define LIO_OPCODE_INFO 0x04 114 #define LIO_OPCODE_PORT_STATS 0x05 115 #define LIO_OPCODE_IF_CFG 0x09 116 117 #define LIO_MIN_RX_BUF_SIZE 64 118 #define LIO_MAX_RX_PKTLEN (64 * 1024) 119 120 /* NIC Command types */ 121 #define LIO_CMD_CHANGE_MTU 0x1 122 #define LIO_CMD_CHANGE_DEVFLAGS 0x3 123 #define LIO_CMD_RX_CTL 0x4 124 #define LIO_CMD_CLEAR_STATS 0x6 125 #define LIO_CMD_SET_RSS 0xD 126 #define LIO_CMD_TNL_RX_CSUM_CTL 0x10 127 #define LIO_CMD_TNL_TX_CSUM_CTL 0x11 128 #define LIO_CMD_ADD_VLAN_FILTER 0x17 129 #define LIO_CMD_DEL_VLAN_FILTER 0x18 130 #define LIO_CMD_VXLAN_PORT_CONFIG 0x19 131 #define LIO_CMD_QUEUE_COUNT_CTL 0x1f 132 133 #define LIO_CMD_VXLAN_PORT_ADD 0x0 134 #define LIO_CMD_VXLAN_PORT_DEL 0x1 135 #define LIO_CMD_RXCSUM_ENABLE 0x0 136 #define LIO_CMD_TXCSUM_ENABLE 0x0 137 138 /* RX(packets coming from wire) Checksum verification flags */ 139 /* TCP/UDP csum */ 140 #define LIO_L4_CSUM_VERIFIED 0x1 141 #define LIO_IP_CSUM_VERIFIED 0x2 142 143 /* RSS */ 144 #define LIO_RSS_PARAM_DISABLE_RSS 0x10 145 #define LIO_RSS_PARAM_HASH_KEY_UNCHANGED 0x08 146 #define LIO_RSS_PARAM_ITABLE_UNCHANGED 0x04 147 #define LIO_RSS_PARAM_HASH_INFO_UNCHANGED 0x02 148 149 #define LIO_RSS_HASH_IPV4 0x100 150 #define LIO_RSS_HASH_TCP_IPV4 0x200 151 #define LIO_RSS_HASH_IPV6 0x400 152 #define LIO_RSS_HASH_TCP_IPV6 0x1000 153 #define LIO_RSS_HASH_IPV6_EX 0x800 154 #define LIO_RSS_HASH_TCP_IPV6_EX 0x2000 155 156 #define LIO_RSS_OFFLOAD_ALL ( \ 157 LIO_RSS_HASH_IPV4 | \ 158 LIO_RSS_HASH_TCP_IPV4 | \ 159 LIO_RSS_HASH_IPV6 | \ 160 LIO_RSS_HASH_TCP_IPV6 | \ 161 LIO_RSS_HASH_IPV6_EX | \ 162 LIO_RSS_HASH_TCP_IPV6_EX) 163 164 #define LIO_RSS_MAX_TABLE_SZ 128 165 #define LIO_RSS_MAX_KEY_SZ 40 166 #define LIO_RSS_PARAM_SIZE 16 167 168 /* Interface flags communicated between host driver and core app. */ 169 enum lio_ifflags { 170 LIO_IFFLAG_PROMISC = 0x01, 171 LIO_IFFLAG_ALLMULTI = 0x02, 172 LIO_IFFLAG_UNICAST = 0x10 173 }; 174 175 /* Routines for reading and writing CSRs */ 176 #ifdef RTE_LIBRTE_LIO_DEBUG_REGS 177 #define lio_write_csr(lio_dev, reg_off, value) \ 178 do { \ 179 typeof(lio_dev) _dev = lio_dev; \ 180 typeof(reg_off) _reg_off = reg_off; \ 181 typeof(value) _value = value; \ 182 PMD_REGS_LOG(_dev, \ 183 "Write32: Reg: 0x%08lx Val: 0x%08lx\n", \ 184 (unsigned long)_reg_off, \ 185 (unsigned long)_value); \ 186 rte_write32(_value, _dev->hw_addr + _reg_off); \ 187 } while (0) 188 189 #define lio_write_csr64(lio_dev, reg_off, val64) \ 190 do { \ 191 typeof(lio_dev) _dev = lio_dev; \ 192 typeof(reg_off) _reg_off = reg_off; \ 193 typeof(val64) _val64 = val64; \ 194 PMD_REGS_LOG( \ 195 _dev, \ 196 "Write64: Reg: 0x%08lx Val: 0x%016llx\n", \ 197 (unsigned long)_reg_off, \ 198 (unsigned long long)_val64); \ 199 rte_write64(_val64, _dev->hw_addr + _reg_off); \ 200 } while (0) 201 202 #define lio_read_csr(lio_dev, reg_off) \ 203 ({ \ 204 typeof(lio_dev) _dev = lio_dev; \ 205 typeof(reg_off) _reg_off = reg_off; \ 206 uint32_t val = rte_read32(_dev->hw_addr + _reg_off); \ 207 PMD_REGS_LOG(_dev, \ 208 "Read32: Reg: 0x%08lx Val: 0x%08lx\n", \ 209 (unsigned long)_reg_off, \ 210 (unsigned long)val); \ 211 val; \ 212 }) 213 214 #define lio_read_csr64(lio_dev, reg_off) \ 215 ({ \ 216 typeof(lio_dev) _dev = lio_dev; \ 217 typeof(reg_off) _reg_off = reg_off; \ 218 uint64_t val64 = rte_read64(_dev->hw_addr + _reg_off); \ 219 PMD_REGS_LOG( \ 220 _dev, \ 221 "Read64: Reg: 0x%08lx Val: 0x%016llx\n", \ 222 (unsigned long)_reg_off, \ 223 (unsigned long long)val64); \ 224 val64; \ 225 }) 226 #else 227 #define lio_write_csr(lio_dev, reg_off, value) \ 228 rte_write32(value, (lio_dev)->hw_addr + (reg_off)) 229 230 #define lio_write_csr64(lio_dev, reg_off, val64) \ 231 rte_write64(val64, (lio_dev)->hw_addr + (reg_off)) 232 233 #define lio_read_csr(lio_dev, reg_off) \ 234 rte_read32((lio_dev)->hw_addr + (reg_off)) 235 236 #define lio_read_csr64(lio_dev, reg_off) \ 237 rte_read64((lio_dev)->hw_addr + (reg_off)) 238 #endif 239 #endif /* _LIO_HW_DEFS_H_ */ 240