1 /*- 2 * File Name : trm.h 3 * 4 * Tekram DC395U/UW/F ,DC315/U 5 * PCI SCSI Bus Master Host Adapter Device Driver 6 * (SCSI chip set used Tekram ASIC TRM-S1040) 7 * 8 * SPDX-License-Identifier: BSD-3-Clause 9 * 10 * (C)Copyright 1995-2001 Tekram Technology Co.,Ltd. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 */ 36 37 #ifndef trm_H 38 #define trm_H 39 40 /* SCSI CAM */ 41 42 #define TRM_TRANS_CUR 0x01 /* Modify current neogtiation status */ 43 #define TRM_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 44 #define TRM_TRANS_GOAL 0x04 /* Modify negotiation goal */ 45 #define TRM_TRANS_USER 0x08 /* Modify user negotiation settings */ 46 47 struct trm_transinfo { 48 u_int8_t width; 49 u_int8_t period; 50 u_int8_t offset; 51 }; 52 53 struct trm_target_info { 54 u_int8_t disc_tag; /* bits define..... */ 55 #define TRM_CUR_DISCENB 0x01 /* current setting disconnect enable */ 56 #define TRM_CUR_TAGENB 0x02 /* current setting tag command Q enable */ 57 #define TRM_USR_DISCENB 0x04 /* user adapter device setting disconnect enable */ 58 #define TRM_USR_TAGENB 0x08 /* user adapter device setting tag command Q enable*/ 59 struct trm_transinfo current; /* info of current */ 60 struct trm_transinfo goal; /* info of after negotiating */ 61 struct trm_transinfo user; /* info of user adapter device setting */ 62 }; 63 /* 64 * SCSI CAM ** 65 */ 66 67 /* 68 * bus_dma_segment_t 69 * 70 * Describes a single contiguous DMA transaction. Values 71 * are suitable for programming into DMA registers. 72 * 73 *typedef struct bus_dma_segment 74 *{ 75 * bus_addr_t ds_addr; // DMA address 76 * bus_size_t ds_len; // length of transfer 77 *} bus_dma_segment_t; 78 */ 79 80 /*;----------------------Segment Entry------------------------------------*/ 81 typedef struct _SGentry { 82 u_int32_t address; 83 u_int32_t length; 84 } SGentry, *PSEG; 85 /* 86 *----------------------------------------------------------------------- 87 * feature of chip set MAX value 88 *----------------------------------------------------------------------- 89 */ 90 91 #define TRM_MAX_ADAPTER_NUM 4 92 #define TRM_MAX_DEVICES 16 93 #define TRM_MAX_SG_LISTENTRY 32 94 #define TRM_MAX_TARGETS 16 95 #define TRM_MAX_TAGS_CMD_QUEUE 256 /* MAX_CMD_QUEUE 20*/ 96 #define TRM_MAX_CMD_PER_LUN 32 97 #define TRM_MAX_SRB_CNT 256 98 #define TRM_MAX_START_JOB 256 99 #define TRM_MAXPHYS (128 * 1024) 100 #define TRM_NSEG (btoc(TRM_MAXPHYS) + 1) 101 #define TRM_MAXTRANSFER_SIZE 0xFFFFFF /* restricted by 24 bit counter */ 102 #define PAGELEN 4096 103 104 #define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40MHz) */ 105 106 /* 107 * CAM ccb 108 * Union of all CCB types for kernel space allocation. This union should 109 * never be used for manipulating CCBs - its only use is for the allocation 110 * and deallocation of raw CCB space and is the return type of xpt_ccb_alloc 111 * and the argument to xpt_ccb_free. 112 * 113 *union ccb { 114 * struct ccb_hdr ccb_h; // For convenience 115 * struct ccb_scsiio csio; 116 * struct ccb_getdev cgd; 117 * struct ccb_getdevlist cgdl; 118 * struct ccb_pathinq cpi; 119 * struct ccb_relsim crs; 120 * struct ccb_setasync csa; 121 * struct ccb_setdev csd; 122 * struct ccb_dev_match cdm; 123 * struct ccb_trans_settings cts; 124 * struct ccb_calc_geometry ccg; 125 * struct ccb_abort cab; 126 * struct ccb_resetbus crb; 127 * struct ccb_resetdev crd; 128 * struct ccb_termio tio; 129 * struct ccb_accept_tio atio; 130 * struct ccb_scsiio ctio; 131 * struct ccb_en_lun cel; 132 * struct ccb_immed_notify cin; 133 * struct ccb_notify_ack cna; 134 * struct ccb_eng_inq cei; 135 * struct ccb_eng_exec cee; 136 * struct ccb_rescan crcn; 137 * struct ccb_debug cdbg; 138 * }; 139 */ 140 141 /* 142 *----------------------------------------------------------------------- 143 * SCSI Request Block 144 *----------------------------------------------------------------------- 145 */ 146 struct _SRB { 147 u_int8_t CmdBlock[12]; 148 u_long Segment0[2]; 149 u_long Segment1[2]; 150 struct _SRB *pNextSRB; 151 struct _DCB *pSRBDCB; 152 SGentry SgSenseTemp; 153 154 PSEG pSRBSGL; /* scatter gather list */ 155 156 u_int32_t SRBSGPhyAddr; /* a segment starting address */ 157 u_int32_t SRBTotalXferLength; 158 159 /* 160 * CAM ccb 161 */ 162 union ccb *pccb; 163 bus_dmamap_t sg_dmamap; 164 bus_dmamap_t dmamap; 165 u_int16_t SRBState; 166 u_int8_t * pMsgPtr; 167 168 u_int8_t SRBSGCount; 169 u_int8_t SRBSGIndex; 170 u_int8_t MsgInBuf[6]; 171 u_int8_t MsgOutBuf[6]; 172 173 u_int8_t AdaptStatus; 174 u_int8_t TargetStatus; 175 u_int8_t MsgCnt; 176 u_int8_t TagNumber; 177 178 u_int8_t SRBStatus; 179 u_int8_t RetryCnt; 180 u_int8_t SRBFlag; 181 u_int8_t ScsiCmdLen; 182 u_int8_t ScsiPhase; 183 u_int8_t Reserved[3]; /*;for dword alignment */ 184 }; 185 typedef struct _SRB TRM_SRB, *PSRB; 186 187 /* 188 *----------------------------------------------------------------------- 189 * Device Control Block 190 *----------------------------------------------------------------------- 191 */ 192 struct _DCB 193 { 194 PSRB pWaitingSRB; 195 PSRB pWaitingLastSRB; 196 197 PSRB pGoingSRB; 198 PSRB pGoingLastSRB; 199 200 PSRB pActiveSRB; 201 202 u_int16_t GoingSRBCnt; 203 u_int16_t MaxActiveCommandCnt; 204 205 u_int8_t TargetID; /*; SCSI Target ID (SCSI Only) */ 206 u_int8_t TargetLUN; /*; SCSI Log. Unit (SCSI Only) */ 207 u_int8_t DCBFlag; 208 u_int8_t DevType; 209 210 u_int8_t SyncMode; /* mode ? (1 sync):(0 async) */ 211 u_int8_t MaxNegoPeriod; /* for nego. */ 212 u_int8_t SyncPeriod; /* for reg. */ 213 u_int8_t SyncOffset; /* for reg. and nego.(low nibble) */ 214 215 u_int8_t DevMode; 216 u_int8_t AdpMode; 217 218 u_int8_t IdentifyMsg; 219 u_int8_t DCBstatus; /* DCB status */ 220 /*u_int8_t Reserved[3]; for dword alignment */ 221 struct trm_target_info tinfo; /* 10 bytes */ 222 struct _DCB *pNextDCB; 223 }; 224 typedef struct _DCB TRM_DCB, *PDCB; 225 226 /* 227 *----------------------------------------------------------------------- 228 * Adapter Control Block 229 *----------------------------------------------------------------------- 230 */ 231 struct _ACB 232 { 233 device_t dev; 234 235 bus_space_tag_t tag; 236 bus_space_handle_t bsh; 237 bus_dma_tag_t parent_dmat; 238 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 239 bus_dma_tag_t srb_dmat; 240 bus_dma_tag_t sense_dmat; /* dmat for sense buffer */ 241 bus_dma_tag_t sg_dmat; 242 bus_dmamap_t sense_dmamap; 243 bus_dmamap_t srb_dmamap; 244 bus_addr_t sense_busaddr; 245 struct scsi_sense_data *sense_buffers; 246 struct resource *iores, *irq; 247 void *ih; 248 /* 249 * CAM SIM/XPT 250 */ 251 struct cam_sim *psim; 252 struct cam_path *ppath; 253 254 TRM_SRB TmpSRB; 255 TRM_DCB DCBarray[16][8]; 256 257 u_int32_t srb_physbase; 258 259 PSRB pFreeSRB; 260 PDCB pActiveDCB; 261 262 PDCB pLinkDCB; 263 PDCB pDCBRunRobin; 264 265 u_int16_t max_id; 266 u_int16_t max_lun; 267 268 u_int8_t msgin123[4]; 269 270 u_int8_t scan_devices[16][8]; 271 272 u_int8_t AdaptSCSIID; /*; Adapter SCSI Target ID */ 273 u_int8_t AdaptSCSILUN; /*; Adapter SCSI LUN */ 274 u_int8_t DeviceCnt; 275 u_int8_t ACBFlag; 276 277 u_int8_t TagMaxNum; 278 u_int8_t Config; 279 u_int8_t AdaptType; 280 u_int8_t AdapterUnit; /* nth Adapter this driver */ 281 }; 282 typedef struct _ACB TRM_ACB, *PACB; 283 /* 284 * ----SRB State machine definition 285 */ 286 #define SRB_FREE 0x0000 287 #define SRB_WAIT 0x0001 288 #define SRB_READY 0x0002 289 #define SRB_MSGOUT 0x0004 /*arbitration+msg_out 1st byte*/ 290 #define SRB_MSGIN 0x0008 291 #define SRB_EXTEND_MSGIN 0x0010 292 #define SRB_COMMAND 0x0020 293 #define SRB_START_ 0x0040 /*arbitration+msg_out+command_out*/ 294 #define SRB_DISCONNECT 0x0080 295 #define SRB_DATA_XFER 0x0100 296 #define SRB_XFERPAD 0x0200 297 #define SRB_STATUS 0x0400 298 #define SRB_COMPLETED 0x0800 299 #define SRB_ABORT_SENT 0x1000 300 #define SRB_DO_SYNC_NEGO 0x2000 301 #define SRB_DO_WIDE_NEGO 0x4000 302 #define SRB_UNEXPECT_RESEL 0x8000 303 /* 304 * 305 * ACB Config 306 * 307 */ 308 #define HCC_WIDE_CARD 0x20 309 #define HCC_SCSI_RESET 0x10 310 #define HCC_PARITY 0x08 311 #define HCC_AUTOTERM 0x04 312 #define HCC_LOW8TERM 0x02 313 #define HCC_UP8TERM 0x01 314 /* 315 * ---ACB Flag 316 */ 317 #define RESET_DEV 0x00000001 318 #define RESET_DETECT 0x00000002 319 #define RESET_DONE 0x00000004 320 321 /* 322 * ---DCB Flag 323 */ 324 #define ABORT_DEV_ 0x00000001 325 326 /* 327 * ---DCB status 328 */ 329 #define DS_IN_QUEUE 0x00000001 330 331 /* 332 * ---SRB status 333 */ 334 #define SRB_OK 0x00000001 335 #define ABORTION 0x00000002 336 #define OVER_RUN 0x00000004 337 #define UNDER_RUN 0x00000008 338 #define PARITY_ERROR 0x00000010 339 #define SRB_ERROR 0x00000020 340 341 /* 342 * ---SRB Flag 343 */ 344 #define DATAOUT 0x00000080 345 #define DATAIN 0x00000040 346 #define RESIDUAL_VALID 0x00000020 347 #define ENABLE_TIMER 0x00000010 348 #define RESET_DEV0 0x00000004 349 #define ABORT_DEV 0x00000002 350 #define AUTO_REQSENSE 0x00000001 351 352 /* 353 * ---Adapter status 354 */ 355 #define H_STATUS_GOOD 0x00 356 #define H_SEL_TIMEOUT 0x11 357 #define H_OVER_UNDER_RUN 0x12 358 #define H_UNEXP_BUS_FREE 0x13 359 #define H_TARGET_PHASE_F 0x14 360 #define H_INVALID_CCB_OP 0x16 361 #define H_LINK_CCB_BAD 0x17 362 #define H_BAD_TARGET_DIR 0x18 363 #define H_DUPLICATE_CCB 0x19 364 #define H_BAD_CCB_OR_SG 0x1A 365 #define H_ABORT 0x0FF 366 367 /* 368 * ---SCSI Status byte codes 369 */ 370 #define SCSI_STAT_GOOD 0x00 /*; Good status */ 371 #define SCSI_STAT_CHECKCOND 0x02 /*; SCSI Check Condition */ 372 #define SCSI_STAT_CONDMET 0x04 /*; Condition Met */ 373 #define SCSI_STAT_BUSY 0x08 /*; Target busy status */ 374 #define SCSI_STAT_INTER 0x10 /*; Intermediate status */ 375 #define SCSI_STAT_INTERCONDMET 0x14 /*; Intermediate condition met */ 376 #define SCSI_STAT_RESCONFLICT 0x18 /*; Reservation conflict */ 377 #define SCSI_STAT_CMDTERM 0x22 /*; Command Terminated */ 378 #define SCSI_STAT_QUEUEFULL 0x28 /*; Queue Full */ 379 #define SCSI_STAT_UNEXP_BUS_F 0xFD /*; Unexpect Bus Free */ 380 #define SCSI_STAT_BUS_RST_DETECT 0xFE /*; Scsi Bus Reset detected */ 381 #define SCSI_STAT_SEL_TIMEOUT 0xFF /*; Selection Time out */ 382 383 /* 384 * ---Sync_Mode 385 */ 386 #define SYNC_WIDE_TAG_ATNT_DISABLE 0x00000000 387 #define SYNC_NEGO_ENABLE 0x00000001 388 #define SYNC_NEGO_DONE 0x00000002 389 #define WIDE_NEGO_ENABLE 0x00000004 390 #define WIDE_NEGO_DONE 0x00000008 391 #define EN_TAG_QUEUING 0x00000010 392 #define EN_ATN_STOP 0x00000020 393 394 #define SYNC_NEGO_OFFSET 15 395 /* 396 * ---SCSI bus phase 397 */ 398 #define SCSI_DATA_OUT_ 0 399 #define SCSI_DATA_IN_ 1 400 #define SCSI_COMMAND 2 401 #define SCSI_STATUS_ 3 402 #define SCSI_NOP0 4 403 #define SCSI_NOP1 5 404 #define SCSI_MSG_OUT 6 405 #define SCSI_MSG_IN 7 406 407 /* 408 * ----SCSI MSG u_int8_t 409 */ 410 #define MSG_COMPLETE 0x00 411 #define MSG_EXTENDED 0x01 412 #define MSG_SAVE_PTR 0x02 413 #define MSG_RESTORE_PTR 0x03 414 #define MSG_DISCONNECT 0x04 415 #define MSG_INITIATOR_ERROR 0x05 416 #define MSG_ABORT 0x06 417 #define MSG_REJECT_ 0x07 418 #define MSG_NOP 0x08 419 #define MSG_PARITY_ERROR 0x09 420 #define MSG_LINK_CMD_COMPL 0x0A 421 #define MSG_LINK_CMD_COMPL_FLG 0x0B 422 #define MSG_BUS_RESET 0x0C 423 /* #define MSG_ABORT_TAG 0x0D */ 424 #define MSG_SIMPLE_QTAG 0x20 425 #define MSG_HEAD_QTAG 0x21 426 #define MSG_ORDER_QTAG 0x22 427 #define MSG_IGNOREWIDE 0x23 428 /* #define MSG_IDENTIFY 0x80 */ 429 #define MSG_HOST_ID 0xC0 430 /* bus wide length */ 431 #define MSG_EXT_WDTR_BUS_8_BIT 0x00 432 #define MSG_EXT_WDTR_BUS_16_BIT 0x01 433 #define MSG_EXT_WDTR_BUS_32_BIT 0x02 434 /* 435 * ----SCSI STATUS u_int8_t 436 */ 437 #define STATUS_GOOD 0x00 438 #define CHECK_CONDITION_ 0x02 439 #define STATUS_BUSY 0x08 440 #define STATUS_INTERMEDIATE 0x10 441 #define RESERVE_CONFLICT 0x18 442 443 /* 444 * ---- cmd->result 445 */ 446 #define STATUS_MASK_ 0xFF 447 #define MSG_MASK 0xFF00 448 #define RETURN_MASK 0xFF0000 449 450 /* 451 * Inquiry Data format 452 */ 453 454 typedef struct _SCSIInqData { /* INQ */ 455 456 u_int8_t DevType; /* Periph Qualifier & Periph Dev Type */ 457 u_int8_t RMB_TypeMod; /* rem media bit & Dev Type Modifier */ 458 u_int8_t Vers; /* ISO, ECMA, & ANSI versions */ 459 u_int8_t RDF; /* AEN, TRMIOP, & response data format*/ 460 u_int8_t AddLen; /* length of additional data */ 461 u_int8_t Res1; /* reserved */ 462 u_int8_t Res2; /* reserved */ 463 u_int8_t Flags; /* RelADr,Wbus32,Wbus16,Sync,etc. */ 464 u_int8_t VendorID[8]; /* Vendor Identification */ 465 u_int8_t ProductID[16]; /* Product Identification */ 466 u_int8_t ProductRev[4]; /* Product Revision */ 467 } SCSI_INQDATA, *PSCSI_INQDATA; 468 469 470 /* 471 * Inquiry byte 0 masks 472 */ 473 #define SCSI_DEVTYPE 0x1F /* Peripheral Device Type */ 474 #define SCSI_PERIPHQUAL 0xE0 /* Peripheral Qualifier */ 475 /* 476 * Inquiry byte 1 mask 477 */ 478 #define SCSI_REMOVABLE_MEDIA 0x80 /* Removable Media bit (1=removable) */ 479 /* 480 * Peripheral Device Type definitions 481 */ 482 #define SCSI_DASD 0x00 /* Direct-access Device */ 483 #define SCSI_SEQACESS 0x01 /* Sequential-access device */ 484 #define SCSI_PRINTER 0x02 /* Printer device */ 485 #define SCSI_PROCESSOR 0x03 /* Processor device */ 486 #define SCSI_WRITEONCE 0x04 /* Write-once device */ 487 #define SCSI_CDROM 0x05 /* CD-ROM device */ 488 #define SCSI_SCANNER 0x06 /* Scanner device */ 489 #define SCSI_OPTICAL 0x07 /* Optical memory device */ 490 #define SCSI_MEDCHGR 0x08 /* Medium changer device */ 491 #define SCSI_COMM 0x09 /* Communications device */ 492 #define SCSI_NODEV 0x1F /* Unknown or no device type */ 493 /* 494 * Inquiry flag definitions (Inq data byte 7) 495 */ 496 #define SCSI_INQ_RELADR 0x80 /* device supports relative addressing*/ 497 #define SCSI_INQ_WBUS32 0x40 /* device supports 32 bit data xfers */ 498 #define SCSI_INQ_WBUS16 0x20 /* device supports 16 bit data xfers */ 499 #define SCSI_INQ_SYNC 0x10 /* device supports synchronous xfer */ 500 #define SCSI_INQ_LINKED 0x08 /* device supports linked commands */ 501 #define SCSI_INQ_CMDQUEUE 0x02 /* device supports command queueing */ 502 #define SCSI_INQ_SFTRE 0x01 /* device supports soft resets */ 503 /* 504 *========================================================== 505 * EEPROM byte offset 506 *========================================================== 507 */ 508 typedef struct _EEprom { 509 u_int8_t EE_MODE1; 510 u_int8_t EE_SPEED; 511 u_int8_t xx1; 512 u_int8_t xx2; 513 } EEprom, *PEEprom; 514 515 #define EE_ADAPT_SCSI_ID 64 516 #define EE_MODE2 65 517 #define EE_DELAY 66 518 #define EE_TAG_CMD_NUM 67 519 520 /* 521 * EE_MODE1 bits definition 522 */ 523 #define PARITY_CHK_ 0x00000001 524 #define SYNC_NEGO_ 0x00000002 525 #define EN_DISCONNECT_ 0x00000004 526 #define SEND_START_ 0x00000008 527 #define TAG_QUEUING_ 0x00000010 528 529 /* 530 * EE_MODE2 bits definition 531 */ 532 #define MORE2_DRV 0x00000001 533 #define GREATER_1G 0x00000002 534 #define RST_SCSI_BUS 0x00000004 535 #define ACTIVE_NEGATION 0x00000008 536 #define NO_SEEK 0x00000010 537 #define LUN_CHECK 0x00000020 538 539 #define ENABLE_CE 0x01 540 #define DISABLE_CE 0x00 541 #define EEPROM_READ 0x80 542 543 /* 544 * The PCI configuration register offset for TRM_S1040 545 * Registers bit Definition 546 */ 547 #define TRMREG_ID 0x00 /* Vendor and Device ID */ 548 #define TRMREG_COMMAND 0x04 /* PCI command register */ 549 #define TRMREG_IOBASE 0x10 /* I/O Space base address */ 550 #define TRMREG_ROMBASE 0x30 /* Expansion ROM Base Address */ 551 #define TRMREG_INTLINE 0x3C /* Interrupt line */ 552 553 /* 554 * 555 * The SCSI register offset for TRM_S1040 556 * 557 */ 558 #define TRMREG_SCSI_STATUS 0x80 /* SCSI Status (R) */ 559 /* ######### */ 560 #define COMMANDPHASEDONE 0x2000 /* SCSI command phase done */ 561 #define SCSIXFERDONE 0x0800 /* SCSI SCSI transfer done */ 562 #define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI SCSI transfer count to zero*/ 563 #define SCSIINTERRUPT 0x0080 /* SCSI interrupt pending */ 564 #define COMMANDABORT 0x0040 /* SCSI command abort */ 565 #define SEQUENCERACTIVE 0x0020 /* SCSI sequencer active */ 566 #define PHASEMISMATCH 0x0010 /* SCSI phase mismatch */ 567 #define PARITYERROR 0x0008 /* SCSI parity error */ 568 569 #define PHASEMASK 0x0007 /* Phase MSG/CD/IO */ 570 #define PH_DATA_OUT 0x00 /* Data out phase */ 571 #define PH_DATA_IN 0x01 /* Data in phase */ 572 #define PH_COMMAND 0x02 /* Command phase */ 573 #define PH_STATUS 0x03 /* Status phase */ 574 #define PH_BUS_FREE 0x05 /* Invalid phase used as bus free */ 575 #define PH_MSG_OUT 0x06 /* Message out phase */ 576 #define PH_MSG_IN 0x07 /* Message in phase */ 577 578 #define TRMREG_SCSI_CONTROL 0x80 /* SCSI Control (W) */ 579 /* ######### */ 580 #define DO_CLRATN 0x0400 /* Clear ATN */ 581 #define DO_SETATN 0x0200 /* Set ATN */ 582 #define DO_CMDABORT 0x0100 /* Abort SCSI command */ 583 #define DO_RSTMODULE 0x0010 /* Reset SCSI chip */ 584 #define DO_RSTSCSI 0x0008 /* Reset SCSI bus */ 585 #define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */ 586 #define DO_DATALATCH 0x0002 /* Enable SCSI bus data latch */ 587 #define DO_HWRESELECT 0x0001 /* Enable hardware reselection */ 588 #define TRMREG_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter 5bits(R) */ 589 #define TRMREG_SCSI_SIGNAL 0x83 /* SCSI low level signal (R/W) */ 590 #define TRMREG_SCSI_INTSTATUS 0x84 /* SCSI Interrupt Status (R) */ 591 /* ######### */ 592 #define INT_SCAM 0x80 /* SCAM selection interrupt */ 593 #define INT_SELECT 0x40 /* Selection interrupt */ 594 #define INT_SELTIMEOUT 0x20 /* Selection timeout interrupt */ 595 #define INT_DISCONNECT 0x10 /* Bus disconnected interrupt */ 596 #define INT_RESELECTED 0x08 /* Reselected interrupt */ 597 #define INT_SCSIRESET 0x04 /* SCSI reset detected interrupt*/ 598 #define INT_BUSSERVICE 0x02 /* Bus service interrupt */ 599 #define INT_CMDDONE 0x01 /* SCSI command done interrupt */ 600 #define TRMREG_SCSI_OFFSET 0x84 /* SCSI Offset Count (W) */ 601 /* 602 * Bit Name Definition 603 * 07-05 0 RSVD Reversed. Always 0. 604 * 04 0 OFFSET4 Reversed for LVDS. Always 0. 605 * 03-00 0 OFFSET[03:00] Offset number from 0 to 15 606 */ 607 #define TRMREG_SCSI_SYNC 0x85 /* SCSI Synchronous Control (R/W)*/ 608 /* ######### */ 609 #define LVDS_SYNC 0x20 /* Enable LVDS synchronous */ 610 #define WIDE_SYNC 0x10 /* Enable WIDE synchronous */ 611 #define ALT_SYNC 0x08 /* Enable Fast-20 alternate synchronous */ 612 /* 613 * SYNCM 7 6 5 4 3 2 1 0 614 * Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0 615 * Default 0 0 0 0 0 0 0 0 616 * 617 * 618 * Bit Name Definition 619 * 07-06 0 RSVD Reversed. Always read 0 620 * 05 0 LVDS Reversed. Always read 0 621 * 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI transfer. 622 * 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode. 623 * 624 * @@ When this bit is set, 625 * the synchronous period bits 2:0 626 * in the Synchronous Mode register 627 * are used to transfer data 628 * at the Fast-20 rate. 629 * @@ When this bit is reset, 630 * the synchronous period bits 2:0 631 * in the Synchronous Mode Register 632 * are used to transfer data 633 * at the Fast-40 rate. 634 * 635 * 02-00 0 PERIOD[2:0]/SXPD[02:00] Synchronous SCSI Transfer Rate. 636 * These 3 bits specify 637 * the Synchronous SCSI Transfer Rate 638 * for Fast-20 and Fast-10. 639 * These bits are also reset 640 * by a SCSI Bus reset. 641 * 642 * For Fast-10 bit ALTPD = 0 and LVDS = 0 643 * and 0x00000004,0x00000002,0x00000001 is defined as follows : 644 * 645 * 000 100ns, 10.0 Mbytes/s 646 * 001 150ns, 6.6 Mbytes/s 647 * 010 200ns, 5.0 Mbytes/s 648 * 011 250ns, 4.0 Mbytes/s 649 * 100 300ns, 3.3 Mbytes/s 650 * 101 350ns, 2.8 Mbytes/s 651 * 110 400ns, 2.5 Mbytes/s 652 * 111 450ns, 2.2 Mbytes/s 653 * 654 * For Fast-20 bit ALTPD = 1 and LVDS = 0 655 * and 0x00000004,0x00000002,0x00000001 is defined as follows : 656 * 657 * 000 50ns, 20.0 Mbytes/s 658 * 001 75ns, 13.3 Mbytes/s 659 * 010 100ns, 10.0 Mbytes/s 660 * 011 125ns, 8.0 Mbytes/s 661 * 100 150ns, 6.6 Mbytes/s 662 * 101 175ns, 5.7 Mbytes/s 663 * 110 200ns, 5.0 Mbytes/s 664 * 111 250ns, 4.0 Mbytes/s 665 * 666 * For Fast-40 bit ALTPD = 0 and LVDS = 1 667 * and 0x00000004,0x00000002,0x00000001 is defined as follows : 668 * 669 * 000 25ns, 40.0 Mbytes/s 670 * 001 50ns, 20.0 Mbytes/s 671 * 010 75ns, 13.3 Mbytes/s 672 * 011 100ns, 10.0 Mbytes/s 673 * 100 125ns, 8.0 Mbytes/s 674 * 101 150ns, 6.6 Mbytes/s 675 * 110 175ns, 5.7 Mbytes/s 676 * 111 200ns, 5.0 Mbytes/s 677 */ 678 679 /* 680 *************************************** 681 */ 682 #define TRMREG_SCSI_TARGETID 0x86 /* SCSI Target ID (R/W) */ 683 /* 684 *************************************** 685 */ 686 #define TRMREG_SCSI_IDMSG 0x87 /* SCSI Identify Message (R) */ 687 /* 688 *************************************** 689 */ 690 #define TRMREG_SCSI_HOSTID 0x87 /* SCSI Host ID (W) */ 691 /* 692 *************************************** 693 */ 694 #define TRMREG_SCSI_COUNTER 0x88 /* SCSI Transfer Counter 24bits(R/W)*/ 695 /* 696 *************************************** 697 */ 698 #define TRMREG_SCSI_INTEN 0x8C /* SCSI Interrupt Enable (R/W) */ 699 /* ######### */ 700 #define EN_SCAM 0x80 /* Enable SCAM selection interrupt*/ 701 #define EN_SELECT 0x40 /* Enable selection interrupt */ 702 #define EN_SELTIMEOUT 0x20 /* Enable selection timeout interrupt*/ 703 #define EN_DISCONNECT 0x10 /* Enable bus disconnected interrupt*/ 704 #define EN_RESELECTED 0x08 /* Enable reselected interrupt */ 705 #define EN_SCSIRESET 0x04 /* Enable SCSI reset detected interrupt*/ 706 #define EN_BUSSERVICE 0x02 /* Enable bus service interrupt */ 707 #define EN_CMDDONE 0x01 /* Enable SCSI command done interrupt*/ 708 /* 709 *************************************** 710 */ 711 #define TRMREG_SCSI_CONFIG0 0x8D /* SCSI Configuration 0 (R/W) */ 712 /* ######### */ 713 #define PHASELATCH 0x40 /* Enable phase latch */ 714 #define INITIATOR 0x20 /* Enable initiator mode */ 715 #define PARITYCHECK 0x10 /* Enable parity check */ 716 #define BLOCKRST 0x01 /* Disable SCSI reset1 */ 717 /* 718 *************************************** 719 */ 720 #define TRMREG_SCSI_CONFIG1 0x8E /* SCSI Configuration 1 (R/W) */ 721 /* ######### */ 722 #define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */ 723 #define FILTER_DISABLE 0x08 /* Disable SCSI data filter */ 724 #define ACTIVE_NEG 0x02 /* Enable active negation */ 725 #define ACTIVE_HISLEW 0x01 /* Enable high slew rate (3/6 ns) */ 726 /* 727 *************************************** 728 */ 729 #define TRMREG_SCSI_CONFIG2 0x8F /* SCSI Configuration 2 (R/W) */ 730 /* 731 *************************************** 732 */ 733 #define TRMREG_SCSI_COMMAND 0x90 /* SCSI Command (R/W) */ 734 /* ######### */ 735 #define SCMD_COMP 0x12 /* Command complete */ 736 #define SCMD_SEL_ATN 0x60 /* Selection with ATN */ 737 #define SCMD_SEL_ATN3 0x64 /* Selection with ATN3 */ 738 #define SCMD_SEL_ATNSTOP 0xB8 /* Selection with ATN and Stop */ 739 #define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */ 740 #define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */ 741 #define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */ 742 #define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */ 743 #define SCMD_MSGACCEPT 0xD8 /* Message accept */ 744 /* 745 * Code Command Description 746 * 747 * 02 Enable reselection with FIFO 748 * 40 Select without ATN with FIFO 749 * 60 Select with ATN with FIFO 750 * 64 Select with ATN3 with FIFO 751 * A0 Select with ATN and stop with FIFO 752 * C0 Transfer information out with FIFO 753 * C1 Transfer information out with DMA 754 * C2 Transfer information in with FIFO 755 * C3 Transfer information in with DMA 756 * 12 Initiator command complete with FIFO 757 * 50 Initiator transfer information out sequence without ATN with FIFO 758 * 70 Initiator transfer information out sequence with ATN with FIFO 759 * 74 Initiator transfer information out sequence with ATN3 with FIFO 760 * 52 Initiator transfer information in sequence without ATN with FIFO 761 * 72 Initiator transfer information in sequence with ATN with FIFO 762 * 76 Initiator transfer information in sequence with ATN3 with FIFO 763 * 90 Initiator transfer information out command complete with FIFO 764 * 92 Initiator transfer information in command complete with FIFO 765 * D2 Enable selection 766 * 08 Reselection 767 * 48 Disconnect command with FIFO 768 * 88 Terminate command with FIFO 769 * C8 Target command complete with FIFO 770 * 18 SCAM Arbitration/ Selection 771 * 5A Enable reselection 772 * 98 Select without ATN with FIFO 773 * B8 Select with ATN with FIFO 774 * D8 Message Accepted 775 * 58 NOP 776 */ 777 /* 778 *************************************** 779 */ 780 #define TRMREG_SCSI_TIMEOUT 0x91 /* SCSI Time Out Value (R/W) */ 781 /* 782 *************************************** 783 */ 784 #define TRMREG_SCSI_FIFO 0x98 /* SCSI FIFO (R/W) */ 785 /* 786 *************************************** 787 */ 788 #define TRMREG_SCSI_TCR00 0x9C /* SCSI Target Control 0 (R/W) */ 789 /* ######### */ 790 #define TCR0_DO_WIDE_NEGO 0x80 /* Do wide NEGO */ 791 #define TCR0_DO_SYNC_NEGO 0x40 /* Do sync NEGO */ 792 #define TCR0_DISCONNECT_EN 0x20 /* Disconnection enable */ 793 #define TCR0_OFFSET_MASK 0x1F /* Offset number */ 794 /* 795 *************************************** 796 */ 797 #define TRMREG_SCSI_TCR01 0x9D /* SCSI Target Control 0 (R/W) */ 798 /* ######### */ 799 #define TCR0_ENABLE_LVDS 0xF8 /* LVD */ 800 #define TCR0_ENABLE_WIDE 0xF9 /* SE */ 801 /* 802 **************************************** 803 */ 804 805 /* 806 *************************************** 807 */ 808 #define TRMREG_SCSI_TCR1 0x9E /* SCSI Target Control 1 (R/W) */ 809 /* ######### */ 810 #define MAXTAG_MASK 0x7F00 /* Maximum tags (127) */ 811 #define NON_TAG_BUSY 0x0080 /* Non tag command active */ 812 #define ACTTAG_MASK 0x007F /* Active tags */ 813 /* 814 * 815 * The DMA register offset for TRM_S1040 816 * 817 */ 818 #define TRMREG_DMA_COMMAND 0xA0 /* DMA Command (R/W) */ 819 /* ######### */ 820 #define XFERDATAIN 0x0103 /* Transfer data in */ 821 #define XFERDATAOUT 0x0102 /* Transfer data out */ 822 /* 823 *************************************** 824 */ 825 #define TRMREG_DMA_FIFOCNT 0xA1 /* DMA FIFO Counter (R) */ 826 /* 827 *************************************** 828 */ 829 #define TRMREG_DMA_CONTROL 0xA1 /* DMA Control (W) */ 830 /* ######### */ 831 #define STOPDMAXFER 0x08 /* Stop DMA transfer */ 832 #define ABORTXFER 0x04 /* Abort DMA transfer */ 833 #define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */ 834 #define STARTDMAXFER 0x01 /* Start DMA transfer */ 835 /* 836 *************************************** 837 */ 838 #define TRMREG_DMA_STATUS 0xA3 /* DMA Interrupt Status (R/W) */ 839 /* ######### */ 840 #define XFERPENDING 0x80 /* Transfer pending */ 841 #define DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */ 842 #define SCSICOMP 0x01 /* SCSI complete interrupt */ 843 /* 844 *************************************** 845 */ 846 #define TRMREG_DMA_INTEN 0xA4 /* DMA Interrupt Enable (R/W)*/ 847 /* ######### */ 848 #define EN_SCSIINTR 0x01 /* Enable SCSI complete interrupt */ 849 /* 850 *************************************** 851 */ 852 #define TRMREG_DMA_CONFIG 0xA6 /* DMA Configuration (R/W) */ 853 /* ######### */ 854 #define DMA_ENHANCE 0x8000 /* Enable DMA enhance feature */ 855 /* 856 *************************************** 857 */ 858 #define TRMREG_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W)*/ 859 /* 860 *************************************** 861 */ 862 #define TRMREG_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */ 863 /* 864 *************************************** 865 */ 866 #define TRMREG_DMA_XLOWADDR 0xB0 /* DMA Transfer Physical Low Address */ 867 /* 868 *************************************** 869 */ 870 #define TRMREG_DMA_XHIGHADDR 0xB4 /* DMA Transfer Physical High Address */ 871 872 /* 873 * 874 * The general register offset for TRM_S1040 875 * 876 */ 877 #define TRMREG_GEN_CONTROL 0xD4 /* Global Control */ 878 /* ######### */ 879 #define EN_EEPROM 0x10 /* Enable EEPROM programming */ 880 #define AUTOTERM 0x04 /* Enable Auto SCSI terminator */ 881 #define LOW8TERM 0x02 /* Enable Lower 8 bit SCSI terminator */ 882 #define UP8TERM 0x01 /* Enable Upper 8 bit SCSI terminator */ 883 /* 884 *************************************** 885 */ 886 #define TRMREG_GEN_STATUS 0xD5 /* Global Status */ 887 /* ######### */ 888 #define GTIMEOUT 0x80 /* Global timer reach 0 */ 889 #define CON5068 0x10 /* External 50/68 pin connected */ 890 #define CON68 0x08 /* Internal 68 pin connected */ 891 #define CON50 0x04 /* Internal 50 pin connected */ 892 #define WIDESCSI 0x02 /* Wide SCSI card */ 893 /* 894 *************************************** 895 */ 896 #define TRMREG_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port */ 897 /* ######### */ 898 #define NVR_BITOUT 0x08 /* Serial data out */ 899 #define NVR_BITIN 0x04 /* Serial data in */ 900 #define NVR_CLOCK 0x02 /* Serial clock */ 901 #define NVR_SELECT 0x01 /* Serial select */ 902 /* 903 *************************************** 904 */ 905 #define TRMREG_GEN_EDATA 0xD7 /* Parallel EEPROM data port */ 906 /* 907 *************************************** 908 */ 909 #define TRMREG_GEN_EADDRESS 0xD8 /* Parallel EEPROM address */ 910 /* 911 *************************************** 912 */ 913 #define TRMREG_GEN_TIMER 0xDB /* Global timer */ 914 915 /* 916 * The SEEPROM structure for TRM_S1040 917 */ 918 typedef struct NVRAM_TARGET_STRUCT 919 { 920 u_int8_t NvmTarCfg0; /* Target configuration byte 0 */ 921 u_int8_t NvmTarPeriod; /* Target period */ 922 u_int8_t NvmTarCfg2; /* Target configuration byte 2 */ 923 u_int8_t NvmTarCfg3; /* Target configuration byte 3 */ 924 } NVRAMTARGETTYPE; 925 /* NvmTarCfg0: Target configuration byte 0 :..pDCB->DevMode */ 926 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 927 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tag queuing */ 928 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP*/ 929 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 930 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 931 #define NTC_DO_PARITY_CHK 0x01 /* (it should define at NAC ) 932 Parity check enable */ 933 934 /* 935 * 936 * 937 * 938 */ 939 typedef struct NVRAM_STRUC { 940 u_int8_t NvramSubVendorID[2]; /*0,1 Sub Vendor ID */ 941 u_int8_t NvramSubSysID[2]; /*2,3 Sub System ID*/ 942 u_int8_t NvramSubClass; /*4 Sub Class */ 943 u_int8_t NvramVendorID[2]; /*5,6 Vendor ID */ 944 u_int8_t NvramDeviceID[2]; /*7,8 Device ID */ 945 u_int8_t NvramReserved; /*9 Reserved */ 946 NVRAMTARGETTYPE NvramTarget[TRM_MAX_TARGETS];/* *10,11,12,13 947 *14,15,16,17 * .... 948 * .... 949 *70,71,72,73 950 */ 951 u_int8_t NvramScsiId; /*74 Host Adapter SCSI ID */ 952 u_int8_t NvramChannelCfg; /*75 Channel configuration */ 953 u_int8_t NvramDelayTime; /*76 Power on delay time */ 954 u_int8_t NvramMaxTag; /*77 Maximum tags */ 955 u_int8_t NvramReserved0; /*78 */ 956 u_int8_t NvramBootTarget; /*79 */ 957 u_int8_t NvramBootLun; /*80 */ 958 u_int8_t NvramReserved1; /*81 */ 959 u_int16_t Reserved[22]; /*82,..125 */ 960 u_int16_t NvramCheckSum; /*126,127*/ 961 } NVRAMTYPE,*PNVRAMTYPE; 962 /* Nvram Initiater bits definition */ 963 #define MORE2_DRV 0x00000001 964 #define GREATER_1G 0x00000002 965 #define RST_SCSI_BUS 0x00000004 966 #define ACTIVE_NEGATION 0x00000008 967 #define NO_SEEK 0x00000010 968 #define LUN_CHECK 0x00000020 969 970 /* Nvram Adapter NvramChannelCfg bits definition */ 971 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device*/ 972 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 973 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 974 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives*/ 975 /* 976 *#define NAC_DO_PARITY_CHK 0x08 // Parity check enable 977 */ 978 979 #endif /* trm_H */ 980