1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019-2020 Intel Corporation
3 */
4
5
6 #ifndef _IGC_OSDEP_H_
7 #define _IGC_OSDEP_H_
8
9 #include <stdint.h>
10 #include <stdio.h>
11 #include <stdarg.h>
12 #include <string.h>
13 #include <stdbool.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
16 #include <rte_log.h>
17 #include <rte_debug.h>
18 #include <rte_byteorder.h>
19 #include <rte_io.h>
20
21 #include "../igc_logs.h"
22
23 #define DELAY(x) rte_delay_us(x)
24 #define usec_delay(x) DELAY(x)
25 #define usec_delay_irq(x) DELAY(x)
26 #define msec_delay(x) DELAY(1000 * (x))
27 #define msec_delay_irq(x) DELAY(1000 * (x))
28
29 #define DEBUGFUNC(F) DEBUGOUT(F "\n")
30 #define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args)
31 #define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args)
32 #define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args)
33 #define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args)
34 #define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args)
35 #define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args)
36
37 #define UNREFERENCED_PARAMETER(_p) (void)(_p)
38 #define UNREFERENCED_1PARAMETER(_p) (void)(_p)
39 #define UNREFERENCED_2PARAMETER(_p, _q) \
40 do { \
41 (void)(_p); \
42 (void)(_q); \
43 } while (0)
44 #define UNREFERENCED_3PARAMETER(_p, _q, _r) \
45 do { \
46 (void)(_p); \
47 (void)(_q); \
48 (void)(_r); \
49 } while (0)
50 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) \
51 do { \
52 (void)(_p); \
53 (void)(_q); \
54 (void)(_r); \
55 (void)(_s); \
56 } while (0)
57
58 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
59
60 /* Mutex used in the shared code */
61 #define IGC_MUTEX uintptr_t
62 #define IGC_MUTEX_INIT(mutex) (*(mutex) = 0)
63 #define IGC_MUTEX_LOCK(mutex) (*(mutex) = 1)
64 #define IGC_MUTEX_UNLOCK(mutex) (*(mutex) = 0)
65
66 typedef uint64_t u64;
67 typedef uint32_t u32;
68 typedef uint16_t u16;
69 typedef uint8_t u8;
70 typedef int64_t s64;
71 typedef int32_t s32;
72 typedef int16_t s16;
73 typedef int8_t s8;
74
75 #define __le16 u16
76 #define __le32 u32
77 #define __le64 u64
78
79 #define IGC_WRITE_FLUSH(a) IGC_READ_REG(a, IGC_STATUS)
80
81 #define IGC_PCI_REG(reg) rte_read32(reg)
82
83 #define IGC_PCI_REG16(reg) rte_read16(reg)
84
85 #define IGC_PCI_REG_WRITE(reg, value) \
86 rte_write32((rte_cpu_to_le_32(value)), reg)
87
88 #define IGC_PCI_REG_WRITE_RELAXED(reg, value) \
89 rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
90
91 #define IGC_PCI_REG_WRITE16(reg, value) \
92 rte_write16((rte_cpu_to_le_16(value)), reg)
93
94 #define IGC_PCI_REG_ADDR(hw, reg) \
95 ((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
96
97 #define IGC_PCI_REG_ARRAY_ADDR(hw, reg, index) \
98 IGC_PCI_REG_ADDR((hw), (reg) + ((index) << 2))
99
100 #define IGC_PCI_REG_FLASH_ADDR(hw, reg) \
101 ((volatile uint32_t *)((char *)(hw)->flash_address + (reg)))
102
igc_read_addr(volatile void * addr)103 static inline uint32_t igc_read_addr(volatile void *addr)
104 {
105 return rte_le_to_cpu_32(IGC_PCI_REG(addr));
106 }
107
igc_read_addr16(volatile void * addr)108 static inline uint16_t igc_read_addr16(volatile void *addr)
109 {
110 return rte_le_to_cpu_16(IGC_PCI_REG16(addr));
111 }
112
113 /* Register READ/WRITE macros */
114
115 #define IGC_READ_REG(hw, reg) \
116 igc_read_addr(IGC_PCI_REG_ADDR((hw), (reg)))
117
118 #define IGC_READ_REG_LE_VALUE(hw, reg) \
119 rte_read32(IGC_PCI_REG_ADDR((hw), (reg)))
120
121 #define IGC_WRITE_REG(hw, reg, value) \
122 IGC_PCI_REG_WRITE(IGC_PCI_REG_ADDR((hw), (reg)), (value))
123
124 #define IGC_WRITE_REG_LE_VALUE(hw, reg, value) \
125 rte_write32(value, IGC_PCI_REG_ADDR((hw), (reg)))
126
127 #define IGC_READ_REG_ARRAY(hw, reg, index) \
128 IGC_PCI_REG(IGC_PCI_REG_ARRAY_ADDR((hw), (reg), (index)))
129
130 #define IGC_WRITE_REG_ARRAY(hw, reg, index, value) \
131 IGC_PCI_REG_WRITE(IGC_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), \
132 (value))
133
134 #define IGC_READ_REG_ARRAY_DWORD IGC_READ_REG_ARRAY
135 #define IGC_WRITE_REG_ARRAY_DWORD IGC_WRITE_REG_ARRAY
136
137 /*
138 * To be able to do IO write, we need to map IO BAR
139 * (bar 2/4 depending on device).
140 * Right now mapping multiple BARs is not supported by DPDK.
141 * Fortunatelly we need it only for legacy hw support.
142 */
143
144 #define IGC_WRITE_REG_IO(hw, reg, value) \
145 IGC_WRITE_REG(hw, reg, value)
146
147 /*
148 * Tested on I217/I218 chipset.
149 */
150
151 #define IGC_READ_FLASH_REG(hw, reg) \
152 igc_read_addr(IGC_PCI_REG_FLASH_ADDR((hw), (reg)))
153
154 #define IGC_READ_FLASH_REG16(hw, reg) \
155 igc_read_addr16(IGC_PCI_REG_FLASH_ADDR((hw), (reg)))
156
157 #define IGC_WRITE_FLASH_REG(hw, reg, value) \
158 IGC_PCI_REG_WRITE(IGC_PCI_REG_FLASH_ADDR((hw), (reg)), (value))
159
160 #define IGC_WRITE_FLASH_REG16(hw, reg, value) \
161 IGC_PCI_REG_WRITE16(IGC_PCI_REG_FLASH_ADDR((hw), (reg)), (value))
162
163 #endif /* _IGC_OSDEP_H_ */
164