1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
3 */
4
5 #ifndef _ICE_RXTX_H_
6 #define _ICE_RXTX_H_
7
8 #include "ice_ethdev.h"
9
10 #define ICE_ALIGN_RING_DESC 32
11 #define ICE_MIN_RING_DESC 64
12 #define ICE_MAX_RING_DESC 4096
13 #define ICE_DMA_MEM_ALIGN 4096
14 #define ICE_RING_BASE_ALIGN 128
15
16 #define ICE_RX_MAX_BURST 32
17 #define ICE_TX_MAX_BURST 32
18
19 #define ICE_CHK_Q_ENA_COUNT 100
20 #define ICE_CHK_Q_ENA_INTERVAL_US 100
21
22 #ifdef RTE_LIBRTE_ICE_16BYTE_RX_DESC
23 #define ice_rx_flex_desc ice_16b_rx_flex_desc
24 #else
25 #define ice_rx_flex_desc ice_32b_rx_flex_desc
26 #endif
27
28 #define ICE_SUPPORT_CHAIN_NUM 5
29
30 #define ICE_TD_CMD ICE_TX_DESC_CMD_EOP
31
32 #define ICE_VPMD_RX_BURST 32
33 #define ICE_VPMD_TX_BURST 32
34 #define ICE_RXQ_REARM_THRESH 32
35 #define ICE_MAX_RX_BURST ICE_RXQ_REARM_THRESH
36 #define ICE_TX_MAX_FREE_BUF_SZ 64
37 #define ICE_DESCS_PER_LOOP 4
38
39 #define ICE_FDIR_PKT_LEN 512
40
41 #define ICE_RXDID_COMMS_OVS 22
42
43 typedef void (*ice_rx_release_mbufs_t)(struct ice_rx_queue *rxq);
44 typedef void (*ice_tx_release_mbufs_t)(struct ice_tx_queue *txq);
45 typedef void (*ice_rxd_to_pkt_fields_t)(struct ice_rx_queue *rxq,
46 struct rte_mbuf *mb,
47 volatile union ice_rx_flex_desc *rxdp);
48
49 struct ice_rx_entry {
50 struct rte_mbuf *mbuf;
51 };
52
53 struct ice_rx_queue {
54 struct rte_mempool *mp; /* mbuf pool to populate RX ring */
55 volatile union ice_rx_flex_desc *rx_ring;/* RX ring virtual address */
56 rte_iova_t rx_ring_dma; /* RX ring DMA address */
57 struct ice_rx_entry *sw_ring; /* address of RX soft ring */
58 uint16_t nb_rx_desc; /* number of RX descriptors */
59 uint16_t rx_free_thresh; /* max free RX desc to hold */
60 uint16_t rx_tail; /* current value of tail */
61 uint16_t nb_rx_hold; /* number of held free RX desc */
62 struct rte_mbuf *pkt_first_seg; /**< first segment of current packet */
63 struct rte_mbuf *pkt_last_seg; /**< last segment of current packet */
64 uint16_t rx_nb_avail; /**< number of staged packets ready */
65 uint16_t rx_next_avail; /**< index of next staged packets */
66 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
67 struct rte_mbuf fake_mbuf; /**< dummy mbuf */
68 struct rte_mbuf *rx_stage[ICE_RX_MAX_BURST * 2];
69
70 uint16_t rxrearm_nb; /**< number of remaining to be re-armed */
71 uint16_t rxrearm_start; /**< the idx we start the re-arming from */
72 uint64_t mbuf_initializer; /**< value to init mbufs */
73
74 uint16_t port_id; /* device port ID */
75 uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
76 uint8_t fdir_enabled; /* 0 if FDIR disabled, 1 when enabled */
77 uint16_t queue_id; /* RX queue index */
78 uint16_t reg_idx; /* RX queue register index */
79 uint8_t drop_en; /* if not 0, set register bit */
80 volatile uint8_t *qrx_tail; /* register address of tail */
81 struct ice_vsi *vsi; /* the VSI this queue belongs to */
82 uint16_t rx_buf_len; /* The packet buffer size */
83 uint16_t rx_hdr_len; /* The header buffer size */
84 uint16_t max_pkt_len; /* Maximum packet length */
85 bool q_set; /* indicate if rx queue has been configured */
86 bool rx_deferred_start; /* don't start this queue in dev start */
87 uint8_t proto_xtr; /* Protocol extraction from flexible descriptor */
88 uint64_t xtr_ol_flag; /* Protocol extraction offload flag */
89 ice_rxd_to_pkt_fields_t rxd_to_pkt_fields; /* handle FlexiMD by RXDID */
90 ice_rx_release_mbufs_t rx_rel_mbufs;
91 };
92
93 struct ice_tx_entry {
94 struct rte_mbuf *mbuf;
95 uint16_t next_id;
96 uint16_t last_id;
97 };
98
99 struct ice_vec_tx_entry {
100 struct rte_mbuf *mbuf;
101 };
102
103 struct ice_tx_queue {
104 uint16_t nb_tx_desc; /* number of TX descriptors */
105 rte_iova_t tx_ring_dma; /* TX ring DMA address */
106 volatile struct ice_tx_desc *tx_ring; /* TX ring virtual address */
107 struct ice_tx_entry *sw_ring; /* virtual address of SW ring */
108 uint16_t tx_tail; /* current value of tail register */
109 volatile uint8_t *qtx_tail; /* register address of tail */
110 uint16_t nb_tx_used; /* number of TX desc used since RS bit set */
111 /* index to last TX descriptor to have been cleaned */
112 uint16_t last_desc_cleaned;
113 /* Total number of TX descriptors ready to be allocated. */
114 uint16_t nb_tx_free;
115 /* Start freeing TX buffers if there are less free descriptors than
116 * this value.
117 */
118 uint16_t tx_free_thresh;
119 /* Number of TX descriptors to use before RS bit is set. */
120 uint16_t tx_rs_thresh;
121 uint8_t pthresh; /**< Prefetch threshold register. */
122 uint8_t hthresh; /**< Host threshold register. */
123 uint8_t wthresh; /**< Write-back threshold reg. */
124 uint16_t port_id; /* Device port identifier. */
125 uint16_t queue_id; /* TX queue index. */
126 uint32_t q_teid; /* TX schedule node id. */
127 uint16_t reg_idx;
128 uint64_t offloads;
129 struct ice_vsi *vsi; /* the VSI this queue belongs to */
130 uint16_t tx_next_dd;
131 uint16_t tx_next_rs;
132 bool tx_deferred_start; /* don't start this queue in dev start */
133 bool q_set; /* indicate if tx queue has been configured */
134 ice_tx_release_mbufs_t tx_rel_mbufs;
135 };
136
137 /* Offload features */
138 union ice_tx_offload {
139 uint64_t data;
140 struct {
141 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
142 uint64_t l3_len:9; /* L3 (IP) Header Length. */
143 uint64_t l4_len:8; /* L4 Header Length. */
144 uint64_t tso_segsz:16; /* TCP TSO segment size */
145 uint64_t outer_l2_len:8; /* outer L2 Header Length */
146 uint64_t outer_l3_len:16; /* outer L3 Header Length */
147 };
148 };
149
150 /* Rx Flex Descriptor for Comms Package Profile
151 * RxDID Profile ID 22 (swap Hash and FlowID)
152 * Flex-field 0: Flow ID lower 16-bits
153 * Flex-field 1: Flow ID upper 16-bits
154 * Flex-field 2: RSS hash lower 16-bits
155 * Flex-field 3: RSS hash upper 16-bits
156 * Flex-field 4: AUX0
157 * Flex-field 5: AUX1
158 */
159 struct ice_32b_rx_flex_desc_comms_ovs {
160 /* Qword 0 */
161 u8 rxdid;
162 u8 mir_id_umb_cast;
163 __le16 ptype_flexi_flags0;
164 __le16 pkt_len;
165 __le16 hdr_len_sph_flex_flags1;
166
167 /* Qword 1 */
168 __le16 status_error0;
169 __le16 l2tag1;
170 __le32 flow_id;
171
172 /* Qword 2 */
173 __le16 status_error1;
174 u8 flexi_flags2;
175 u8 ts_low;
176 __le16 l2tag2_1st;
177 __le16 l2tag2_2nd;
178
179 /* Qword 3 */
180 __le32 rss_hash;
181 union {
182 struct {
183 __le16 aux0;
184 __le16 aux1;
185 } flex;
186 __le32 ts_high;
187 } flex_ts;
188 };
189
190 int ice_rx_queue_setup(struct rte_eth_dev *dev,
191 uint16_t queue_idx,
192 uint16_t nb_desc,
193 unsigned int socket_id,
194 const struct rte_eth_rxconf *rx_conf,
195 struct rte_mempool *mp);
196 int ice_tx_queue_setup(struct rte_eth_dev *dev,
197 uint16_t queue_idx,
198 uint16_t nb_desc,
199 unsigned int socket_id,
200 const struct rte_eth_txconf *tx_conf);
201 int ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
202 int ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
203 int ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
204 int ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
205 int ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
206 int ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
207 int ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
208 int ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
209 void ice_rx_queue_release(void *rxq);
210 void ice_tx_queue_release(void *txq);
211 void ice_free_queues(struct rte_eth_dev *dev);
212 int ice_fdir_setup_tx_resources(struct ice_pf *pf);
213 int ice_fdir_setup_rx_resources(struct ice_pf *pf);
214 uint16_t ice_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
215 uint16_t nb_pkts);
216 uint16_t ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
217 uint16_t nb_pkts);
218 void ice_set_rx_function(struct rte_eth_dev *dev);
219 uint16_t ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
220 uint16_t nb_pkts);
221 void ice_set_tx_function_flag(struct rte_eth_dev *dev,
222 struct ice_tx_queue *txq);
223 void ice_set_tx_function(struct rte_eth_dev *dev);
224 uint32_t ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
225 void ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
226 struct rte_eth_rxq_info *qinfo);
227 void ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
228 struct rte_eth_txq_info *qinfo);
229 int ice_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
230 struct rte_eth_burst_mode *mode);
231 int ice_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
232 struct rte_eth_burst_mode *mode);
233 int ice_rx_descriptor_status(void *rx_queue, uint16_t offset);
234 int ice_tx_descriptor_status(void *tx_queue, uint16_t offset);
235 void ice_set_default_ptype_table(struct rte_eth_dev *dev);
236 const uint32_t *ice_dev_supported_ptypes_get(struct rte_eth_dev *dev);
237 void ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq,
238 uint32_t rxdid);
239
240 int ice_rx_vec_dev_check(struct rte_eth_dev *dev);
241 int ice_tx_vec_dev_check(struct rte_eth_dev *dev);
242 int ice_rxq_vec_setup(struct ice_rx_queue *rxq);
243 int ice_txq_vec_setup(struct ice_tx_queue *txq);
244 uint16_t ice_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
245 uint16_t nb_pkts);
246 uint16_t ice_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
247 uint16_t nb_pkts);
248 uint16_t ice_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
249 uint16_t nb_pkts);
250 uint16_t ice_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
251 uint16_t nb_pkts);
252 uint16_t ice_recv_scattered_pkts_vec_avx2(void *rx_queue,
253 struct rte_mbuf **rx_pkts,
254 uint16_t nb_pkts);
255 uint16_t ice_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
256 uint16_t nb_pkts);
257 uint16_t ice_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
258 uint16_t nb_pkts);
259 uint16_t ice_recv_scattered_pkts_vec_avx512(void *rx_queue,
260 struct rte_mbuf **rx_pkts,
261 uint16_t nb_pkts);
262 uint16_t ice_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
263 uint16_t nb_pkts);
264 int ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc);
265 int ice_tx_done_cleanup(void *txq, uint32_t free_cnt);
266
267 #define FDIR_PARSING_ENABLE_PER_QUEUE(ad, on) do { \
268 int i; \
269 for (i = 0; i < (ad)->eth_dev->data->nb_rx_queues; i++) { \
270 struct ice_rx_queue *rxq = (ad)->eth_dev->data->rx_queues[i]; \
271 if (!rxq) \
272 continue; \
273 rxq->fdir_enabled = on; \
274 } \
275 PMD_DRV_LOG(DEBUG, "FDIR processing on RX set to %d", on); \
276 } while (0)
277
278 /* Enable/disable flow director parsing from Rx descriptor in data path. */
279 static inline
ice_fdir_rx_parsing_enable(struct ice_adapter * ad,bool on)280 void ice_fdir_rx_parsing_enable(struct ice_adapter *ad, bool on)
281 {
282 if (on) {
283 /* Enable flow director parsing from Rx descriptor */
284 FDIR_PARSING_ENABLE_PER_QUEUE(ad, on);
285 ad->fdir_ref_cnt++;
286 } else {
287 if (ad->fdir_ref_cnt >= 1) {
288 ad->fdir_ref_cnt--;
289
290 if (ad->fdir_ref_cnt == 0)
291 FDIR_PARSING_ENABLE_PER_QUEUE(ad, on);
292 }
293 }
294 }
295
296 #endif /* _ICE_RXTX_H_ */
297