1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
3 */
4
5 #ifndef _IAVF_RXTX_H_
6 #define _IAVF_RXTX_H_
7
8 /* In QLEN must be whole number of 32 descriptors. */
9 #define IAVF_ALIGN_RING_DESC 32
10 #define IAVF_MIN_RING_DESC 64
11 #define IAVF_MAX_RING_DESC 4096
12 #define IAVF_DMA_MEM_ALIGN 4096
13 /* Base address of the HW descriptor ring should be 128B aligned. */
14 #define IAVF_RING_BASE_ALIGN 128
15
16 /* used for Rx Bulk Allocate */
17 #define IAVF_RX_MAX_BURST 32
18
19 /* used for Vector PMD */
20 #define IAVF_VPMD_RX_MAX_BURST 32
21 #define IAVF_VPMD_TX_MAX_BURST 32
22 #define IAVF_RXQ_REARM_THRESH 32
23 #define IAVF_VPMD_DESCS_PER_LOOP 4
24 #define IAVF_VPMD_TX_MAX_FREE_BUF 64
25
26 #define IAVF_TX_NO_VECTOR_FLAGS ( \
27 RTE_ETH_TX_OFFLOAD_MULTI_SEGS | \
28 RTE_ETH_TX_OFFLOAD_TCP_TSO | \
29 RTE_ETH_TX_OFFLOAD_SECURITY)
30
31 #define IAVF_TX_VECTOR_OFFLOAD ( \
32 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | \
33 RTE_ETH_TX_OFFLOAD_QINQ_INSERT | \
34 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | \
35 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | \
36 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \
37 RTE_ETH_TX_OFFLOAD_TCP_CKSUM)
38
39 #define IAVF_RX_VECTOR_OFFLOAD ( \
40 RTE_ETH_RX_OFFLOAD_CHECKSUM | \
41 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM | \
42 RTE_ETH_RX_OFFLOAD_VLAN | \
43 RTE_ETH_RX_OFFLOAD_RSS_HASH)
44
45 #define IAVF_VECTOR_PATH 0
46 #define IAVF_VECTOR_OFFLOAD_PATH 1
47
48 #define DEFAULT_TX_RS_THRESH 32
49 #define DEFAULT_TX_FREE_THRESH 32
50
51 #define IAVF_MIN_TSO_MSS 256
52 #define IAVF_MAX_TSO_MSS 9668
53 #define IAVF_TSO_MAX_SEG UINT8_MAX
54 #define IAVF_TX_MAX_MTU_SEG 8
55
56 #define IAVF_TX_CKSUM_OFFLOAD_MASK ( \
57 RTE_MBUF_F_TX_IP_CKSUM | \
58 RTE_MBUF_F_TX_L4_MASK | \
59 RTE_MBUF_F_TX_TCP_SEG)
60
61 #define IAVF_TX_OFFLOAD_MASK ( \
62 RTE_MBUF_F_TX_OUTER_IPV6 | \
63 RTE_MBUF_F_TX_OUTER_IPV4 | \
64 RTE_MBUF_F_TX_IPV6 | \
65 RTE_MBUF_F_TX_IPV4 | \
66 RTE_MBUF_F_TX_VLAN | \
67 RTE_MBUF_F_TX_IP_CKSUM | \
68 RTE_MBUF_F_TX_L4_MASK | \
69 RTE_MBUF_F_TX_TCP_SEG | \
70 RTE_ETH_TX_OFFLOAD_SECURITY)
71
72 #define IAVF_TX_OFFLOAD_NOTSUP_MASK \
73 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ IAVF_TX_OFFLOAD_MASK)
74
75 extern uint64_t iavf_timestamp_dynflag;
76 extern int iavf_timestamp_dynfield_offset;
77
78 /**
79 * Rx Flex Descriptors
80 * These descriptors are used instead of the legacy version descriptors
81 */
82 union iavf_16b_rx_flex_desc {
83 struct {
84 __le64 pkt_addr; /* Packet buffer address */
85 __le64 hdr_addr; /* Header buffer address */
86 /* bit 0 of hdr_addr is DD bit */
87 } read;
88 struct {
89 /* Qword 0 */
90 u8 rxdid; /* descriptor builder profile ID */
91 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
92 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
93 __le16 pkt_len; /* [15:14] are reserved */
94 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
95 /* sph=[11:11] */
96 /* ff1/ext=[15:12] */
97
98 /* Qword 1 */
99 __le16 status_error0;
100 __le16 l2tag1;
101 __le16 flex_meta0;
102 __le16 flex_meta1;
103 } wb; /* writeback */
104 };
105
106 union iavf_32b_rx_flex_desc {
107 struct {
108 __le64 pkt_addr; /* Packet buffer address */
109 __le64 hdr_addr; /* Header buffer address */
110 /* bit 0 of hdr_addr is DD bit */
111 __le64 rsvd1;
112 __le64 rsvd2;
113 } read;
114 struct {
115 /* Qword 0 */
116 u8 rxdid; /* descriptor builder profile ID */
117 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
118 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
119 __le16 pkt_len; /* [15:14] are reserved */
120 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
121 /* sph=[11:11] */
122 /* ff1/ext=[15:12] */
123
124 /* Qword 1 */
125 __le16 status_error0;
126 __le16 l2tag1;
127 __le16 flex_meta0;
128 __le16 flex_meta1;
129
130 /* Qword 2 */
131 __le16 status_error1;
132 u8 flex_flags2;
133 u8 time_stamp_low;
134 __le16 l2tag2_1st;
135 __le16 l2tag2_2nd;
136
137 /* Qword 3 */
138 __le16 flex_meta2;
139 __le16 flex_meta3;
140 union {
141 struct {
142 __le16 flex_meta4;
143 __le16 flex_meta5;
144 } flex;
145 __le32 ts_high;
146 } flex_ts;
147 } wb; /* writeback */
148 };
149
150 /* HW desc structure, both 16-byte and 32-byte types are supported */
151 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
152 #define iavf_rx_desc iavf_16byte_rx_desc
153 #define iavf_rx_flex_desc iavf_16b_rx_flex_desc
154 #else
155 #define iavf_rx_desc iavf_32byte_rx_desc
156 #define iavf_rx_flex_desc iavf_32b_rx_flex_desc
157 #endif
158
159 typedef void (*iavf_rxd_to_pkt_fields_t)(struct iavf_rx_queue *rxq,
160 struct rte_mbuf *mb,
161 volatile union iavf_rx_flex_desc *rxdp);
162
163 struct iavf_rxq_ops {
164 void (*release_mbufs)(struct iavf_rx_queue *rxq);
165 };
166
167 struct iavf_txq_ops {
168 void (*release_mbufs)(struct iavf_tx_queue *txq);
169 };
170
171
172 struct iavf_rx_queue_stats {
173 uint64_t reserved;
174 struct iavf_ipsec_crypto_stats ipsec_crypto;
175 };
176
177 /* Structure associated with each Rx queue. */
178 struct iavf_rx_queue {
179 struct rte_mempool *mp; /* mbuf pool to populate Rx ring */
180 const struct rte_memzone *mz; /* memzone for Rx ring */
181 volatile union iavf_rx_desc *rx_ring; /* Rx ring virtual address */
182 uint64_t rx_ring_phys_addr; /* Rx ring DMA address */
183 struct rte_mbuf **sw_ring; /* address of SW ring */
184 uint16_t nb_rx_desc; /* ring length */
185 uint16_t rx_tail; /* current value of tail */
186 volatile uint8_t *qrx_tail; /* register address of tail */
187 uint16_t rx_free_thresh; /* max free RX desc to hold */
188 uint16_t nb_rx_hold; /* number of held free RX desc */
189 struct rte_mbuf *pkt_first_seg; /* first segment of current packet */
190 struct rte_mbuf *pkt_last_seg; /* last segment of current packet */
191 struct rte_mbuf fake_mbuf; /* dummy mbuf */
192 uint8_t rxdid;
193
194 /* used for VPMD */
195 uint16_t rxrearm_nb; /* number of remaining to be re-armed */
196 uint16_t rxrearm_start; /* the idx we start the re-arming from */
197 uint64_t mbuf_initializer; /* value to init mbufs */
198
199 /* for rx bulk */
200 uint16_t rx_nb_avail; /* number of staged packets ready */
201 uint16_t rx_next_avail; /* index of next staged packets */
202 uint16_t rx_free_trigger; /* triggers rx buffer allocation */
203 struct rte_mbuf *rx_stage[IAVF_RX_MAX_BURST * 2]; /* store mbuf */
204
205 uint16_t port_id; /* device port ID */
206 uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
207 uint8_t fdir_enabled; /* 0 if FDIR disabled, 1 when enabled */
208 uint16_t queue_id; /* Rx queue index */
209 uint16_t rx_buf_len; /* The packet buffer size */
210 uint16_t rx_hdr_len; /* The header buffer size */
211 uint16_t max_pkt_len; /* Maximum packet length */
212 struct iavf_vsi *vsi; /**< the VSI this queue belongs to */
213
214 bool q_set; /* if rx queue has been configured */
215 bool rx_deferred_start; /* don't start this queue in dev start */
216 const struct iavf_rxq_ops *ops;
217 uint8_t rx_flags;
218 #define IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1 BIT(0)
219 #define IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2 BIT(1)
220 uint8_t proto_xtr; /* protocol extraction type */
221 uint64_t xtr_ol_flag;
222 /* flexible descriptor metadata extraction offload flag */
223 struct iavf_rx_queue_stats stats;
224 uint64_t offloads;
225 };
226
227 struct iavf_tx_entry {
228 struct rte_mbuf *mbuf;
229 uint16_t next_id;
230 uint16_t last_id;
231 };
232
233 struct iavf_tx_vec_entry {
234 struct rte_mbuf *mbuf;
235 };
236
237 /* Structure associated with each TX queue. */
238 struct iavf_tx_queue {
239 const struct rte_memzone *mz; /* memzone for Tx ring */
240 volatile struct iavf_tx_desc *tx_ring; /* Tx ring virtual address */
241 uint64_t tx_ring_phys_addr; /* Tx ring DMA address */
242 struct iavf_tx_entry *sw_ring; /* address array of SW ring */
243 uint16_t nb_tx_desc; /* ring length */
244 uint16_t tx_tail; /* current value of tail */
245 volatile uint8_t *qtx_tail; /* register address of tail */
246 /* number of used desc since RS bit set */
247 uint16_t nb_used;
248 uint16_t nb_free;
249 uint16_t last_desc_cleaned; /* last desc have been cleaned*/
250 uint16_t free_thresh;
251 uint16_t rs_thresh;
252
253 uint16_t port_id;
254 uint16_t queue_id;
255 uint64_t offloads;
256 uint16_t next_dd; /* next to set RS, for VPMD */
257 uint16_t next_rs; /* next to check DD, for VPMD */
258 uint16_t ipsec_crypto_pkt_md_offset;
259
260 bool q_set; /* if rx queue has been configured */
261 bool tx_deferred_start; /* don't start this queue in dev start */
262 const struct iavf_txq_ops *ops;
263 #define IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1 BIT(0)
264 #define IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2 BIT(1)
265 uint8_t vlan_flag;
266 uint8_t tc;
267 };
268
269 /* Offload features */
270 union iavf_tx_offload {
271 uint64_t data;
272 struct {
273 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
274 uint64_t l3_len:9; /* L3 (IP) Header Length. */
275 uint64_t l4_len:8; /* L4 Header Length. */
276 uint64_t tso_segsz:16; /* TCP TSO segment size */
277 /* uint64_t unused : 24; */
278 };
279 };
280
281 /* Rx Flex Descriptor
282 * RxDID Profile ID 16-21
283 * Flex-field 0: RSS hash lower 16-bits
284 * Flex-field 1: RSS hash upper 16-bits
285 * Flex-field 2: Flow ID lower 16-bits
286 * Flex-field 3: Flow ID upper 16-bits
287 * Flex-field 4: AUX0
288 * Flex-field 5: AUX1
289 */
290 struct iavf_32b_rx_flex_desc_comms {
291 /* Qword 0 */
292 u8 rxdid;
293 u8 mir_id_umb_cast;
294 __le16 ptype_flexi_flags0;
295 __le16 pkt_len;
296 __le16 hdr_len_sph_flex_flags1;
297
298 /* Qword 1 */
299 __le16 status_error0;
300 __le16 l2tag1;
301 __le32 rss_hash;
302
303 /* Qword 2 */
304 __le16 status_error1;
305 u8 flexi_flags2;
306 u8 ts_low;
307 __le16 l2tag2_1st;
308 __le16 l2tag2_2nd;
309
310 /* Qword 3 */
311 __le32 flow_id;
312 union {
313 struct {
314 __le16 aux0;
315 __le16 aux1;
316 } flex;
317 __le32 ts_high;
318 } flex_ts;
319 };
320
321 /* Rx Flex Descriptor
322 * RxDID Profile ID 22-23 (swap Hash and FlowID)
323 * Flex-field 0: Flow ID lower 16-bits
324 * Flex-field 1: Flow ID upper 16-bits
325 * Flex-field 2: RSS hash lower 16-bits
326 * Flex-field 3: RSS hash upper 16-bits
327 * Flex-field 4: AUX0
328 * Flex-field 5: AUX1
329 */
330 struct iavf_32b_rx_flex_desc_comms_ovs {
331 /* Qword 0 */
332 u8 rxdid;
333 u8 mir_id_umb_cast;
334 __le16 ptype_flexi_flags0;
335 __le16 pkt_len;
336 __le16 hdr_len_sph_flex_flags1;
337
338 /* Qword 1 */
339 __le16 status_error0;
340 __le16 l2tag1;
341 __le32 flow_id;
342
343 /* Qword 2 */
344 __le16 status_error1;
345 u8 flexi_flags2;
346 u8 ts_low;
347 __le16 l2tag2_1st;
348 __le16 l2tag2_2nd;
349
350 /* Qword 3 */
351 __le32 rss_hash;
352 union {
353 struct {
354 __le16 aux0;
355 __le16 aux1;
356 } flex;
357 __le32 ts_high;
358 } flex_ts;
359 };
360
361 /* Rx Flex Descriptor
362 * RxDID Profile ID 24 Inline IPsec
363 * Flex-field 0: RSS hash lower 16-bits
364 * Flex-field 1: RSS hash upper 16-bits
365 * Flex-field 2: Flow ID lower 16-bits
366 * Flex-field 3: Flow ID upper 16-bits
367 * Flex-field 4: Inline IPsec SAID lower 16-bits
368 * Flex-field 5: Inline IPsec SAID upper 16-bits
369 */
370 struct iavf_32b_rx_flex_desc_comms_ipsec {
371 /* Qword 0 */
372 u8 rxdid;
373 u8 mir_id_umb_cast;
374 __le16 ptype_flexi_flags0;
375 __le16 pkt_len;
376 __le16 hdr_len_sph_flex_flags1;
377
378 /* Qword 1 */
379 __le16 status_error0;
380 __le16 l2tag1;
381 __le32 rss_hash;
382
383 /* Qword 2 */
384 __le16 status_error1;
385 u8 flexi_flags2;
386 u8 ts_low;
387 __le16 l2tag2_1st;
388 __le16 l2tag2_2nd;
389
390 /* Qword 3 */
391 __le32 flow_id;
392 __le32 ipsec_said;
393 };
394
395 /* Receive Flex Descriptor profile IDs: There are a total
396 * of 64 profiles where profile IDs 0/1 are for legacy; and
397 * profiles 2-63 are flex profiles that can be programmed
398 * with a specific metadata (profile 7 reserved for HW)
399 */
400 enum iavf_rxdid {
401 IAVF_RXDID_LEGACY_0 = 0,
402 IAVF_RXDID_LEGACY_1 = 1,
403 IAVF_RXDID_FLEX_NIC = 2,
404 IAVF_RXDID_FLEX_NIC_2 = 6,
405 IAVF_RXDID_HW = 7,
406 IAVF_RXDID_COMMS_GENERIC = 16,
407 IAVF_RXDID_COMMS_AUX_VLAN = 17,
408 IAVF_RXDID_COMMS_AUX_IPV4 = 18,
409 IAVF_RXDID_COMMS_AUX_IPV6 = 19,
410 IAVF_RXDID_COMMS_AUX_IPV6_FLOW = 20,
411 IAVF_RXDID_COMMS_AUX_TCP = 21,
412 IAVF_RXDID_COMMS_OVS_1 = 22,
413 IAVF_RXDID_COMMS_OVS_2 = 23,
414 IAVF_RXDID_COMMS_IPSEC_CRYPTO = 24,
415 IAVF_RXDID_COMMS_AUX_IP_OFFSET = 25,
416 IAVF_RXDID_LAST = 63,
417 };
418
419 enum iavf_rx_flex_desc_status_error_0_bits {
420 /* Note: These are predefined bit offsets */
421 IAVF_RX_FLEX_DESC_STATUS0_DD_S = 0,
422 IAVF_RX_FLEX_DESC_STATUS0_EOF_S,
423 IAVF_RX_FLEX_DESC_STATUS0_HBO_S,
424 IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S,
425 IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
426 IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
427 IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
428 IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
429 IAVF_RX_FLEX_DESC_STATUS0_LPBK_S,
430 IAVF_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
431 IAVF_RX_FLEX_DESC_STATUS0_RXE_S,
432 IAVF_RX_FLEX_DESC_STATUS0_CRCP_S,
433 IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
434 IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
435 IAVF_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
436 IAVF_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
437 IAVF_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
438 };
439
440 enum iavf_rx_flex_desc_status_error_1_bits {
441 /* Note: These are predefined bit offsets */
442 /* Bits 3:0 are reserved for inline ipsec status */
443 IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_0 = 0,
444 IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_1,
445 IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_2,
446 IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_3,
447 IAVF_RX_FLEX_DESC_STATUS1_NAT_S,
448 IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_PROCESSED,
449 /* [10:6] reserved */
450 IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S = 11,
451 IAVF_RX_FLEX_DESC_STATUS1_XTRMD2_VALID_S = 12,
452 IAVF_RX_FLEX_DESC_STATUS1_XTRMD3_VALID_S = 13,
453 IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S = 14,
454 IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S = 15,
455 IAVF_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */
456 };
457
458 #define IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_STATUS_MASK ( \
459 BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_0) | \
460 BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_1) | \
461 BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_2) | \
462 BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_3))
463
464 enum iavf_rx_flex_desc_ipsec_crypto_status {
465 IAVF_IPSEC_CRYPTO_STATUS_SUCCESS = 0,
466 IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS,
467 IAVF_IPSEC_CRYPTO_STATUS_NOT_PROCESSED,
468 IAVF_IPSEC_CRYPTO_STATUS_ICV_CHECK_FAIL,
469 IAVF_IPSEC_CRYPTO_STATUS_LENGTH_ERR,
470 /* Reserved */
471 IAVF_IPSEC_CRYPTO_STATUS_MISC_ERR = 0xF
472 };
473
474
475
476 #define IAVF_TXD_DATA_QW1_DTYPE_SHIFT (0)
477 #define IAVF_TXD_DATA_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT)
478
479 #define IAVF_TXD_DATA_QW1_CMD_SHIFT (4)
480 #define IAVF_TXD_DATA_QW1_CMD_MASK (0x3FFUL << IAVF_TXD_DATA_QW1_CMD_SHIFT)
481
482 #define IAVF_TXD_DATA_QW1_OFFSET_SHIFT (16)
483 #define IAVF_TXD_DATA_QW1_OFFSET_MASK (0x3FFFFULL << \
484 IAVF_TXD_DATA_QW1_OFFSET_SHIFT)
485
486 #define IAVF_TXD_DATA_QW1_OFFSET_MACLEN_SHIFT (IAVF_TXD_DATA_QW1_OFFSET_SHIFT)
487 #define IAVF_TXD_DATA_QW1_OFFSET_MACLEN_MASK \
488 (0x7FUL << IAVF_TXD_DATA_QW1_OFFSET_MACLEN_SHIFT)
489
490 #define IAVF_TXD_DATA_QW1_OFFSET_IPLEN_SHIFT \
491 (IAVF_TXD_DATA_QW1_OFFSET_SHIFT + IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
492 #define IAVF_TXD_DATA_QW1_OFFSET_IPLEN_MASK \
493 (0x7FUL << IAVF_TXD_DATA_QW1_OFFSET_IPLEN_SHIFT)
494
495 #define IAVF_TXD_DATA_QW1_OFFSET_L4LEN_SHIFT \
496 (IAVF_TXD_DATA_QW1_OFFSET_SHIFT + IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
497 #define IAVF_TXD_DATA_QW1_OFFSET_L4LEN_MASK \
498 (0xFUL << IAVF_TXD_DATA_QW1_OFFSET_L4LEN_SHIFT)
499
500 #define IAVF_TXD_DATA_QW1_MACLEN_MASK \
501 (0x7FUL << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT)
502 #define IAVF_TXD_DATA_QW1_IPLEN_MASK \
503 (0x7FUL << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
504 #define IAVF_TXD_DATA_QW1_L4LEN_MASK \
505 (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
506 #define IAVF_TXD_DATA_QW1_FCLEN_MASK \
507 (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
508
509 #define IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT (34)
510 #define IAVF_TXD_DATA_QW1_TX_BUF_SZ_MASK \
511 (0x3FFFULL << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT)
512
513 #define IAVF_TXD_DATA_QW1_L2TAG1_SHIFT (48)
514 #define IAVF_TXD_DATA_QW1_L2TAG1_MASK \
515 (0xFFFFULL << IAVF_TXD_DATA_QW1_L2TAG1_SHIFT)
516
517 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT (11)
518 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_MASK \
519 (0x7UL << IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT)
520
521 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_SHIFT (14)
522 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_MASK \
523 (0xFUL << IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_SHIFT)
524
525 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT (30)
526 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_MASK \
527 (0x3FFFFUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT)
528
529 #define IAVF_TXD_CTX_QW1_TSYNC_PARAMS_TLEN_SHIFT (30)
530 #define IAVF_TXD_CTX_QW1_TSYNC_PARAMS_TLEN_MASK \
531 (0x3FUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT)
532
533 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_SHIFT (50)
534 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_MASK \
535 (0x3FFFUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_SHIFT)
536
537 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_SHIFT (0)
538 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_MASK (0x3UL)
539
540 enum iavf_tx_ctx_desc_tunnel_external_ip_type {
541 IAVF_TX_CTX_DESC_EIPT_NONE,
542 IAVF_TX_CTX_DESC_EIPT_IPV6,
543 IAVF_TX_CTX_DESC_EIPT_IPV4_NO_CHECKSUM_OFFLOAD,
544 IAVF_TX_CTX_DESC_EIPT_IPV4_CHECKSUM_OFFLOAD
545 };
546
547 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_SHIFT (2)
548 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_MASK (0x7FUL)
549
550 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNT_SHIFT (9)
551 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNT_MASK (0x3UL)
552
553 enum iavf_tx_ctx_desc_tunnel_l4_tunnel_type {
554 IAVF_TX_CTX_DESC_L4_TUN_TYP_NO_UDP_GRE,
555 IAVF_TX_CTX_DESC_L4_TUN_TYP_UDP,
556 IAVF_TX_CTX_DESC_L4_TUN_TYP_GRE
557 };
558
559 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_SHIFT (11)
560 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_MASK (0x1UL)
561
562 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNLEN_SHIFT (12)
563 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNLEN_MASK (0x7FUL)
564
565 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_DECTTL_SHIFT (19)
566 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_DECTTL_MASK (0xFUL)
567
568 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4T_CS_SHIFT (23)
569 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4T_CS_MASK (0x1UL)
570
571 #define IAVF_TXD_CTX_QW0_L2TAG2_PARAM (32)
572 #define IAVF_TXD_CTX_QW0_L2TAG2_MASK (0xFFFFUL)
573
574
575 #define IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_SAID_MASK (0xFFFFF)
576
577 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
578 #define IAVF_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */
579
580
581 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
582 #define IAVF_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */
583
584 /* for iavf_32b_rx_flex_desc.pkt_len member */
585 #define IAVF_RX_FLX_DESC_PKT_LEN_M (0x3FFF) /* 14-bits */
586
587 int iavf_dev_rx_queue_setup(struct rte_eth_dev *dev,
588 uint16_t queue_idx,
589 uint16_t nb_desc,
590 unsigned int socket_id,
591 const struct rte_eth_rxconf *rx_conf,
592 struct rte_mempool *mp);
593
594 int iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
595 int iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
596 void iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
597
598 int iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
599 uint16_t queue_idx,
600 uint16_t nb_desc,
601 unsigned int socket_id,
602 const struct rte_eth_txconf *tx_conf);
603 int iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
604 int iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
605 int iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt);
606 void iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
607 void iavf_stop_queues(struct rte_eth_dev *dev);
608 uint16_t iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
609 uint16_t nb_pkts);
610 uint16_t iavf_recv_pkts_flex_rxd(void *rx_queue,
611 struct rte_mbuf **rx_pkts,
612 uint16_t nb_pkts);
613 uint16_t iavf_recv_scattered_pkts(void *rx_queue,
614 struct rte_mbuf **rx_pkts,
615 uint16_t nb_pkts);
616 uint16_t iavf_recv_scattered_pkts_flex_rxd(void *rx_queue,
617 struct rte_mbuf **rx_pkts,
618 uint16_t nb_pkts);
619 uint16_t iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
620 uint16_t nb_pkts);
621 uint16_t iavf_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
622 uint16_t nb_pkts);
623 void iavf_set_rx_function(struct rte_eth_dev *dev);
624 void iavf_set_tx_function(struct rte_eth_dev *dev);
625 void iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
626 struct rte_eth_rxq_info *qinfo);
627 void iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
628 struct rte_eth_txq_info *qinfo);
629 uint32_t iavf_dev_rxq_count(void *rx_queue);
630 int iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset);
631 int iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset);
632
633 uint16_t iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
634 uint16_t nb_pkts);
635 uint16_t iavf_recv_pkts_vec_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
636 uint16_t nb_pkts);
637 uint16_t iavf_recv_scattered_pkts_vec(void *rx_queue,
638 struct rte_mbuf **rx_pkts,
639 uint16_t nb_pkts);
640 uint16_t iavf_recv_scattered_pkts_vec_flex_rxd(void *rx_queue,
641 struct rte_mbuf **rx_pkts,
642 uint16_t nb_pkts);
643 uint16_t iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
644 uint16_t nb_pkts);
645 uint16_t iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
646 uint16_t nb_pkts);
647 uint16_t iavf_recv_pkts_vec_avx2_flex_rxd(void *rx_queue,
648 struct rte_mbuf **rx_pkts,
649 uint16_t nb_pkts);
650 uint16_t iavf_recv_scattered_pkts_vec_avx2(void *rx_queue,
651 struct rte_mbuf **rx_pkts,
652 uint16_t nb_pkts);
653 uint16_t iavf_recv_scattered_pkts_vec_avx2_flex_rxd(void *rx_queue,
654 struct rte_mbuf **rx_pkts,
655 uint16_t nb_pkts);
656 uint16_t iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
657 uint16_t nb_pkts);
658 uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
659 uint16_t nb_pkts);
660 int iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);
661 int iavf_rx_vec_dev_check(struct rte_eth_dev *dev);
662 int iavf_tx_vec_dev_check(struct rte_eth_dev *dev);
663 int iavf_rxq_vec_setup(struct iavf_rx_queue *rxq);
664 int iavf_txq_vec_setup(struct iavf_tx_queue *txq);
665 uint16_t iavf_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
666 uint16_t nb_pkts);
667 uint16_t iavf_recv_pkts_vec_avx512_offload(void *rx_queue,
668 struct rte_mbuf **rx_pkts,
669 uint16_t nb_pkts);
670 uint16_t iavf_recv_pkts_vec_avx512_flex_rxd(void *rx_queue,
671 struct rte_mbuf **rx_pkts,
672 uint16_t nb_pkts);
673 uint16_t iavf_recv_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
674 struct rte_mbuf **rx_pkts,
675 uint16_t nb_pkts);
676 uint16_t iavf_recv_scattered_pkts_vec_avx512(void *rx_queue,
677 struct rte_mbuf **rx_pkts,
678 uint16_t nb_pkts);
679 uint16_t iavf_recv_scattered_pkts_vec_avx512_offload(void *rx_queue,
680 struct rte_mbuf **rx_pkts,
681 uint16_t nb_pkts);
682 uint16_t iavf_recv_scattered_pkts_vec_avx512_flex_rxd(void *rx_queue,
683 struct rte_mbuf **rx_pkts,
684 uint16_t nb_pkts);
685 uint16_t iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
686 struct rte_mbuf **rx_pkts,
687 uint16_t nb_pkts);
688 uint16_t iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
689 uint16_t nb_pkts);
690 uint16_t iavf_xmit_pkts_vec_avx512_offload(void *tx_queue,
691 struct rte_mbuf **tx_pkts,
692 uint16_t nb_pkts);
693 int iavf_txq_vec_setup_avx512(struct iavf_tx_queue *txq);
694
695 uint8_t iavf_proto_xtr_type_to_rxdid(uint8_t xtr_type);
696
697 void iavf_set_default_ptype_table(struct rte_eth_dev *dev);
698
699 static inline
iavf_dump_rx_descriptor(struct iavf_rx_queue * rxq,const volatile void * desc,uint16_t rx_id)700 void iavf_dump_rx_descriptor(struct iavf_rx_queue *rxq,
701 const volatile void *desc,
702 uint16_t rx_id)
703 {
704 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
705 const volatile union iavf_16byte_rx_desc *rx_desc = desc;
706
707 printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
708 rxq->queue_id, rx_id, rx_desc->read.pkt_addr,
709 rx_desc->read.hdr_addr);
710 #else
711 const volatile union iavf_32byte_rx_desc *rx_desc = desc;
712
713 printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64
714 " QW2: 0x%016"PRIx64" QW3: 0x%016"PRIx64"\n", rxq->queue_id,
715 rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,
716 rx_desc->read.rsvd1, rx_desc->read.rsvd2);
717 #endif
718 }
719
720 /* All the descriptors are 16 bytes, so just use one of them
721 * to print the qwords
722 */
723 static inline
iavf_dump_tx_descriptor(const struct iavf_tx_queue * txq,const volatile void * desc,uint16_t tx_id)724 void iavf_dump_tx_descriptor(const struct iavf_tx_queue *txq,
725 const volatile void *desc, uint16_t tx_id)
726 {
727 const char *name;
728 const volatile struct iavf_tx_desc *tx_desc = desc;
729 enum iavf_tx_desc_dtype_value type;
730
731
732 type = (enum iavf_tx_desc_dtype_value)
733 rte_le_to_cpu_64(tx_desc->cmd_type_offset_bsz &
734 rte_cpu_to_le_64(IAVF_TXD_DATA_QW1_DTYPE_MASK));
735 switch (type) {
736 case IAVF_TX_DESC_DTYPE_DATA:
737 name = "Tx_data_desc";
738 break;
739 case IAVF_TX_DESC_DTYPE_CONTEXT:
740 name = "Tx_context_desc";
741 break;
742 case IAVF_TX_DESC_DTYPE_IPSEC:
743 name = "Tx_IPsec_desc";
744 break;
745 default:
746 name = "unknown_desc";
747 break;
748 }
749
750 printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
751 txq->queue_id, name, tx_id, tx_desc->buffer_addr,
752 tx_desc->cmd_type_offset_bsz);
753 }
754
755 #define FDIR_PROC_ENABLE_PER_QUEUE(ad, on) do { \
756 int i; \
757 for (i = 0; i < (ad)->dev_data->nb_rx_queues; i++) { \
758 struct iavf_rx_queue *rxq = (ad)->dev_data->rx_queues[i]; \
759 if (!rxq) \
760 continue; \
761 rxq->fdir_enabled = on; \
762 } \
763 PMD_DRV_LOG(DEBUG, "FDIR processing on RX set to %d", on); \
764 } while (0)
765
766 /* Enable/disable flow director Rx processing in data path. */
767 static inline
iavf_fdir_rx_proc_enable(struct iavf_adapter * ad,bool on)768 void iavf_fdir_rx_proc_enable(struct iavf_adapter *ad, bool on)
769 {
770 if (on) {
771 /* enable flow director processing */
772 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
773 ad->fdir_ref_cnt++;
774 } else {
775 if (ad->fdir_ref_cnt >= 1) {
776 ad->fdir_ref_cnt--;
777
778 if (ad->fdir_ref_cnt == 0)
779 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
780 }
781 }
782 }
783
784 static inline
iavf_tstamp_convert_32b_64b(uint64_t time,uint32_t in_timestamp)785 uint64_t iavf_tstamp_convert_32b_64b(uint64_t time, uint32_t in_timestamp)
786 {
787 const uint64_t mask = 0xFFFFFFFF;
788 uint32_t delta;
789 uint64_t ns;
790
791 delta = (in_timestamp - (uint32_t)(time & mask));
792 if (delta > (mask / 2)) {
793 delta = ((uint32_t)(time & mask) - in_timestamp);
794 ns = time - delta;
795 } else {
796 ns = time + delta;
797 }
798
799 return ns;
800 }
801
802 #ifdef RTE_LIBRTE_IAVF_DEBUG_DUMP_DESC
803 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) \
804 iavf_dump_rx_descriptor(rxq, desc, rx_id)
805 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) \
806 iavf_dump_tx_descriptor(txq, desc, tx_id)
807 #else
808 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) do { } while (0)
809 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) do { } while (0)
810 #endif
811
812 #endif /* _IAVF_RXTX_H_ */
813