1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2020 Intel Corporation
3 */
4
5 #ifndef _FPGA_5GNR_FEC_H_
6 #define _FPGA_5GNR_FEC_H_
7
8 #include <stdint.h>
9 #include <stdbool.h>
10
11 /* Helper macro for logging */
12 #define rte_bbdev_log(level, fmt, ...) \
13 rte_log(RTE_LOG_ ## level, fpga_5gnr_fec_logtype, fmt "\n", \
14 ##__VA_ARGS__)
15
16 #ifdef RTE_LIBRTE_BBDEV_DEBUG
17 #define rte_bbdev_log_debug(fmt, ...) \
18 rte_bbdev_log(DEBUG, "fpga_5gnr_fec: " fmt, \
19 ##__VA_ARGS__)
20 #else
21 #define rte_bbdev_log_debug(fmt, ...)
22 #endif
23
24 /* FPGA 5GNR FEC driver names */
25 #define FPGA_5GNR_FEC_PF_DRIVER_NAME intel_fpga_5gnr_fec_pf
26 #define FPGA_5GNR_FEC_VF_DRIVER_NAME intel_fpga_5gnr_fec_vf
27
28 /* FPGA 5GNR FEC PCI vendor & device IDs */
29 #define FPGA_5GNR_FEC_VENDOR_ID (0x8086)
30 #define FPGA_5GNR_FEC_PF_DEVICE_ID (0x0D8F)
31 #define FPGA_5GNR_FEC_VF_DEVICE_ID (0x0D90)
32
33 /* Align DMA descriptors to 256 bytes - cache-aligned */
34 #define FPGA_RING_DESC_ENTRY_LENGTH (8)
35 /* Ring size is in 256 bits (32 bytes) units */
36 #define FPGA_RING_DESC_LEN_UNIT_BYTES (32)
37 /* Maximum size of queue */
38 #define FPGA_RING_MAX_SIZE (1024)
39 #define FPGA_FLR_TIMEOUT_UNIT (16.384)
40
41 #define FPGA_NUM_UL_QUEUES (32)
42 #define FPGA_NUM_DL_QUEUES (32)
43 #define FPGA_TOTAL_NUM_QUEUES (FPGA_NUM_UL_QUEUES + FPGA_NUM_DL_QUEUES)
44 #define FPGA_NUM_INTR_VEC (FPGA_TOTAL_NUM_QUEUES - RTE_INTR_VEC_RXTX_OFFSET)
45
46 #define FPGA_INVALID_HW_QUEUE_ID (0xFFFFFFFF)
47
48 #define FPGA_QUEUE_FLUSH_TIMEOUT_US (1000)
49 #define FPGA_HARQ_RDY_TIMEOUT (10)
50 #define FPGA_TIMEOUT_CHECK_INTERVAL (5)
51 #define FPGA_DDR_OVERFLOW (0x10)
52
53 #define FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES 8
54 #define FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES 8
55
56 /* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */
57 #define N_ZC_1 66 /* N = 66 Zc for BG 1 */
58 #define N_ZC_2 50 /* N = 50 Zc for BG 2 */
59 #define K0_1_1 17 /* K0 fraction numerator for rv 1 and BG 1 */
60 #define K0_1_2 13 /* K0 fraction numerator for rv 1 and BG 2 */
61 #define K0_2_1 33 /* K0 fraction numerator for rv 2 and BG 1 */
62 #define K0_2_2 25 /* K0 fraction numerator for rv 2 and BG 2 */
63 #define K0_3_1 56 /* K0 fraction numerator for rv 3 and BG 1 */
64 #define K0_3_2 43 /* K0 fraction numerator for rv 3 and BG 2 */
65
66 /* FPGA 5GNR FEC Register mapping on BAR0 */
67 enum {
68 FPGA_5GNR_FEC_VERSION_ID = 0x00000000, /* len: 4B */
69 FPGA_5GNR_FEC_CONFIGURATION = 0x00000004, /* len: 2B */
70 FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /* len: 1B */
71 FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000a, /* len: 2B */
72 FPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000c, /* len: 2B */
73 FPGA_5GNR_FEC_FLR_TIME_OUT = 0x0000000e, /* len: 2B */
74 FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /* len: 4B */
75 FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001c, /* len: 4B */
76 FPGA_5GNR_FEC_QUEUE_MAP = 0x00000040, /* len: 256B */
77 FPGA_5GNR_FEC_RING_CTRL_REGS = 0x00000200, /* len: 2048B */
78 FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS = 0x00000A00, /* len: 4B */
79 FPGA_5GNR_FEC_DDR4_WR_DATA_REGS = 0x00000A08, /* len: 8B */
80 FPGA_5GNR_FEC_DDR4_WR_DONE_REGS = 0x00000A10, /* len: 1B */
81 FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS = 0x00000A18, /* len: 4B */
82 FPGA_5GNR_FEC_DDR4_RD_DONE_REGS = 0x00000A20, /* len: 1B */
83 FPGA_5GNR_FEC_DDR4_RD_RDY_REGS = 0x00000A28, /* len: 1B */
84 FPGA_5GNR_FEC_DDR4_RD_DATA_REGS = 0x00000A30, /* len: 8B */
85 FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS = 0x00000A38, /* len: 1B */
86 FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS = 0x00000A40, /* len: 1B */
87 FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS = 0x00000A48 /* len: 4B */
88 };
89
90 /* FPGA 5GNR FEC Ring Control Registers */
91 enum {
92 FPGA_5GNR_FEC_RING_HEAD_ADDR = 0x00000008,
93 FPGA_5GNR_FEC_RING_SIZE = 0x00000010,
94 FPGA_5GNR_FEC_RING_MISC = 0x00000014,
95 FPGA_5GNR_FEC_RING_ENABLE = 0x00000015,
96 FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN = 0x00000016,
97 FPGA_5GNR_FEC_RING_SHADOW_TAIL = 0x00000018,
98 FPGA_5GNR_FEC_RING_HEAD_POINT = 0x0000001C
99 };
100
101 /* FPGA 5GNR FEC DESCRIPTOR ERROR */
102 enum {
103 DESC_ERR_NO_ERR = 0x0,
104 DESC_ERR_K_P_OUT_OF_RANGE = 0x1,
105 DESC_ERR_Z_C_NOT_LEGAL = 0x2,
106 DESC_ERR_DESC_OFFSET_ERR = 0x3,
107 DESC_ERR_DESC_READ_FAIL = 0x8,
108 DESC_ERR_DESC_READ_TIMEOUT = 0x9,
109 DESC_ERR_DESC_READ_TLP_POISONED = 0xA,
110 DESC_ERR_CB_READ_FAIL = 0xC,
111 DESC_ERR_CB_READ_TIMEOUT = 0xD,
112 DESC_ERR_CB_READ_TLP_POISONED = 0xE,
113 DESC_ERR_HBSTORE_ERR = 0xF
114 };
115
116
117 /* FPGA 5GNR FEC DMA Encoding Request Descriptor */
118 struct __rte_packed fpga_dma_enc_desc {
119 uint32_t done:1,
120 rsrvd0:7,
121 error:4,
122 rsrvd1:4,
123 num_null:10,
124 rsrvd2:6;
125 uint32_t ncb:15,
126 rsrvd3:1,
127 k0:16;
128 uint32_t irq_en:1,
129 crc_en:1,
130 rsrvd4:1,
131 qm_idx:3,
132 bg_idx:1,
133 zc:9,
134 desc_idx:10,
135 rsrvd5:6;
136 uint16_t rm_e;
137 uint16_t k_;
138 uint32_t out_addr_lw;
139 uint32_t out_addr_hi;
140 uint32_t in_addr_lw;
141 uint32_t in_addr_hi;
142
143 union {
144 struct {
145 /* Virtual addresses used to retrieve SW context info */
146 void *op_addr;
147 /* Stores information about total number of Code Blocks
148 * in currently processed Transport Block
149 */
150 uint64_t cbs_in_op;
151 };
152
153 uint8_t sw_ctxt[FPGA_RING_DESC_LEN_UNIT_BYTES *
154 (FPGA_RING_DESC_ENTRY_LENGTH - 1)];
155 };
156 };
157
158
159 /* FPGA 5GNR DPC FEC DMA Decoding Request Descriptor */
160 struct __rte_packed fpga_dma_dec_desc {
161 uint32_t done:1,
162 iter:5,
163 et_pass:1,
164 crcb_pass:1,
165 error:4,
166 qm_idx:3,
167 max_iter:5,
168 bg_idx:1,
169 rsrvd0:1,
170 harqin_en:1,
171 zc:9;
172 uint32_t hbstroe_offset:22,
173 num_null:10;
174 uint32_t irq_en:1,
175 ncb:15,
176 desc_idx:10,
177 drop_crc24b:1,
178 crc24b_ind:1,
179 rv:2,
180 et_dis:1,
181 rsrvd2:1;
182 uint32_t harq_input_length:16,
183 rm_e:16;/*the inbound data byte length*/
184 uint32_t out_addr_lw;
185 uint32_t out_addr_hi;
186 uint32_t in_addr_lw;
187 uint32_t in_addr_hi;
188
189 union {
190 struct {
191 /* Virtual addresses used to retrieve SW context info */
192 void *op_addr;
193 /* Stores information about total number of Code Blocks
194 * in currently processed Transport Block
195 */
196 uint8_t cbs_in_op;
197 };
198
199 uint32_t sw_ctxt[8 * (FPGA_RING_DESC_ENTRY_LENGTH - 1)];
200 };
201 };
202
203 /* FPGA 5GNR DMA Descriptor */
204 union fpga_dma_desc {
205 struct fpga_dma_enc_desc enc_req;
206 struct fpga_dma_dec_desc dec_req;
207 };
208
209 /* FPGA 5GNR FEC Ring Control Register */
210 struct __rte_packed fpga_ring_ctrl_reg {
211 uint64_t ring_base_addr;
212 uint64_t ring_head_addr;
213 uint16_t ring_size:11;
214 uint16_t rsrvd0;
215 union { /* Miscellaneous register */
216 uint8_t misc;
217 uint8_t max_ul_dec:5,
218 max_ul_dec_en:1,
219 rsrvd1:2;
220 };
221 uint8_t enable;
222 uint8_t flush_queue_en;
223 uint8_t rsrvd2;
224 uint16_t shadow_tail;
225 uint16_t rsrvd3;
226 uint16_t head_point;
227 uint16_t rsrvd4;
228
229 };
230
231 /* Private data structure for each FPGA FEC device */
232 struct fpga_5gnr_fec_device {
233 /** Base address of MMIO registers (BAR0) */
234 void *mmio_base;
235 /** Base address of memory for sw rings */
236 void *sw_rings;
237 /** Physical address of sw_rings */
238 rte_iova_t sw_rings_phys;
239 /** Number of bytes available for each queue in device. */
240 uint32_t sw_ring_size;
241 /** Max number of entries available for each queue in device */
242 uint32_t sw_ring_max_depth;
243 /** Base address of response tail pointer buffer */
244 uint32_t *tail_ptrs;
245 /** Physical address of tail pointers */
246 rte_iova_t tail_ptr_phys;
247 /** Queues flush completion flag */
248 uint64_t *flush_queue_status;
249 /* Bitmap capturing which Queues are bound to the PF/VF */
250 uint64_t q_bound_bit_map;
251 /* Bitmap capturing which Queues have already been assigned */
252 uint64_t q_assigned_bit_map;
253 /** True if this is a PF FPGA FEC device */
254 bool pf_device;
255 };
256
257 /* Structure associated with each queue. */
258 struct __rte_cache_aligned fpga_queue {
259 struct fpga_ring_ctrl_reg ring_ctrl_reg; /* Ring Control Register */
260 union fpga_dma_desc *ring_addr; /* Virtual address of software ring */
261 uint64_t *ring_head_addr; /* Virtual address of completion_head */
262 uint64_t shadow_completion_head; /* Shadow completion head value */
263 uint16_t head_free_desc; /* Ring head */
264 uint16_t tail; /* Ring tail */
265 /* Mask used to wrap enqueued descriptors on the sw ring */
266 uint32_t sw_ring_wrap_mask;
267 uint32_t irq_enable; /* Enable ops dequeue interrupts if set to 1 */
268 uint8_t q_idx; /* Queue index */
269 struct fpga_5gnr_fec_device *d;
270 /* MMIO register of shadow_tail used to enqueue descriptors */
271 void *shadow_tail_addr;
272 };
273
274 /* Write to 16 bit MMIO register address */
275 static inline void
mmio_write_16(void * addr,uint16_t value)276 mmio_write_16(void *addr, uint16_t value)
277 {
278 *((volatile uint16_t *)(addr)) = rte_cpu_to_le_16(value);
279 }
280
281 /* Write to 32 bit MMIO register address */
282 static inline void
mmio_write_32(void * addr,uint32_t value)283 mmio_write_32(void *addr, uint32_t value)
284 {
285 *((volatile uint32_t *)(addr)) = rte_cpu_to_le_32(value);
286 }
287
288 /* Write to 64 bit MMIO register address */
289 static inline void
mmio_write_64(void * addr,uint64_t value)290 mmio_write_64(void *addr, uint64_t value)
291 {
292 *((volatile uint64_t *)(addr)) = rte_cpu_to_le_64(value);
293 }
294
295 /* Write a 8 bit register of a FPGA 5GNR FEC device */
296 static inline void
fpga_reg_write_8(void * mmio_base,uint32_t offset,uint8_t payload)297 fpga_reg_write_8(void *mmio_base, uint32_t offset, uint8_t payload)
298 {
299 void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
300 *((volatile uint8_t *)(reg_addr)) = payload;
301 }
302
303 /* Write a 16 bit register of a FPGA 5GNR FEC device */
304 static inline void
fpga_reg_write_16(void * mmio_base,uint32_t offset,uint16_t payload)305 fpga_reg_write_16(void *mmio_base, uint32_t offset, uint16_t payload)
306 {
307 void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
308 mmio_write_16(reg_addr, payload);
309 }
310
311 /* Write a 32 bit register of a FPGA 5GNR FEC device */
312 static inline void
fpga_reg_write_32(void * mmio_base,uint32_t offset,uint32_t payload)313 fpga_reg_write_32(void *mmio_base, uint32_t offset, uint32_t payload)
314 {
315 void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
316 mmio_write_32(reg_addr, payload);
317 }
318
319 /* Write a 64 bit register of a FPGA 5GNR FEC device */
320 static inline void
fpga_reg_write_64(void * mmio_base,uint32_t offset,uint64_t payload)321 fpga_reg_write_64(void *mmio_base, uint32_t offset, uint64_t payload)
322 {
323 void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
324 mmio_write_64(reg_addr, payload);
325 }
326
327 /* Write a ring control register of a FPGA 5GNR FEC device */
328 static inline void
fpga_ring_reg_write(void * mmio_base,uint32_t offset,struct fpga_ring_ctrl_reg payload)329 fpga_ring_reg_write(void *mmio_base, uint32_t offset,
330 struct fpga_ring_ctrl_reg payload)
331 {
332 fpga_reg_write_64(mmio_base, offset, payload.ring_base_addr);
333 fpga_reg_write_64(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_ADDR,
334 payload.ring_head_addr);
335 fpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SIZE,
336 payload.ring_size);
337 fpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_POINT,
338 payload.head_point);
339 fpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN,
340 payload.flush_queue_en);
341 fpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL,
342 payload.shadow_tail);
343 fpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_MISC,
344 payload.misc);
345 fpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE,
346 payload.enable);
347 }
348
349 /* Read a register of FPGA 5GNR FEC device */
350 static inline uint32_t
fpga_reg_read_32(void * mmio_base,uint32_t offset)351 fpga_reg_read_32(void *mmio_base, uint32_t offset)
352 {
353 void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
354 uint32_t ret = *((volatile uint32_t *)(reg_addr));
355 return rte_le_to_cpu_32(ret);
356 }
357
358 #ifdef RTE_LIBRTE_BBDEV_DEBUG
359
360 /* Read a register of FPGA 5GNR FEC device */
361 static inline uint16_t
fpga_reg_read_16(void * mmio_base,uint32_t offset)362 fpga_reg_read_16(void *mmio_base, uint32_t offset)
363 {
364 void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
365 uint16_t ret = *((volatile uint16_t *)(reg_addr));
366 return rte_le_to_cpu_16(ret);
367 }
368
369 #endif
370
371 /* Read a register of FPGA 5GNR FEC device */
372 static inline uint8_t
fpga_reg_read_8(void * mmio_base,uint32_t offset)373 fpga_reg_read_8(void *mmio_base, uint32_t offset)
374 {
375 void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
376 return *((volatile uint8_t *)(reg_addr));
377 }
378
379 /* Read a register of FPGA 5GNR FEC device */
380 static inline uint64_t
fpga_reg_read_64(void * mmio_base,uint32_t offset)381 fpga_reg_read_64(void *mmio_base, uint32_t offset)
382 {
383 void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
384 uint64_t ret = *((volatile uint64_t *)(reg_addr));
385 return rte_le_to_cpu_64(ret);
386 }
387
388 #endif /* _FPGA_5GNR_FEC_H_ */
389