1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1994 Charles Hannum. 5 * Copyright (c) 1994 Jarle Greipsland. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Jarle Greipsland 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 */ 36 37 #define SCSISEQ 0x00 /* SCSI sequence control */ 38 #define SXFRCTL0 0x01 /* SCSI transfer control 0 */ 39 #define SXFRCTL1 0x02 /* SCSI transfer control 1 */ 40 #define SCSISIGI 0x03 /* SCSI signal in */ 41 #define SCSISIGO 0x03 /* SCSI signal out */ 42 #define SCSIRATE 0x04 /* SCSI rate control */ 43 #define SCSIID 0x05 /* SCSI ID */ 44 #define SELID 0x05 /* Selection/Reselection ID */ 45 #define SCSIDAT 0x06 /* SCSI Latched Data */ 46 #define SCSIBUS 0x07 /* SCSI Data Bus*/ 47 #define STCNT0 0x08 /* SCSI transfer count */ 48 #define STCNT1 0x09 49 #define STCNT2 0x0a 50 #define CLRSINT0 0x0b /* Clear SCSI interrupts 0 */ 51 #define SSTAT0 0x0b /* SCSI interrupt status 0 */ 52 #define CLRSINT1 0x0c /* Clear SCSI interrupts 1 */ 53 #define SSTAT1 0x0c /* SCSI status 1 */ 54 #define SSTAT2 0x0d /* SCSI status 2 */ 55 #define SCSITEST 0x0e /* SCSI test control */ 56 #define SSTAT3 0x0e /* SCSI status 3 */ 57 #define CLRSERR 0x0f /* Clear SCSI errors */ 58 #define SSTAT4 0x0f /* SCSI status 4 */ 59 #define SIMODE0 0x10 /* SCSI interrupt mode 0 */ 60 #define SIMODE1 0x11 /* SCSI interrupt mode 1 */ 61 #define DMACNTRL0 0x12 /* DMA control 0 */ 62 #define DMACNTRL1 0x13 /* DMA control 1 */ 63 #define DMASTAT 0x14 /* DMA status */ 64 #define FIFOSTAT 0x15 /* FIFO status */ 65 #define DMADATA 0x16 /* DMA data */ 66 #define DMADATAL 0x16 /* DMA data low byte */ 67 #define DMADATAH 0x17 /* DMA data high byte */ 68 #define BRSTCNTRL 0x18 /* Burst Control */ 69 #define DMADATALONG 0x18 70 #define PORTA 0x1a /* Port A */ 71 #define PORTB 0x1b /* Port B */ 72 #define REV 0x1c /* Revision (001 for 6360) */ 73 #define STACK 0x1d /* Stack */ 74 #define TEST 0x1e /* Test register */ 75 #define ID 0x1f /* ID register */ 76 77 #define IDSTRING_AIC6360 "(C)1991ADAPTECAIC6360 " 78 #define IDSTRING_AIC6370 "(C)1994ADAPTECAIC6370" 79 #define IDSTRING_GM82C700 "(C)1993 GoldStarGM82C700 " 80 81 /* What all the bits do */ 82 83 /* SCSISEQ */ 84 #define TEMODEO 0x80 85 #define ENSELO 0x40 86 #define ENSELI 0x20 87 #define ENRESELI 0x10 88 #define ENAUTOATNO 0x08 89 #define ENAUTOATNI 0x04 90 #define ENAUTOATNP 0x02 91 #define SCSIRSTO 0x01 92 93 /* SXFRCTL0 */ 94 #define SCSIEN 0x80 95 #define DMAEN 0x40 96 #define CHEN 0x20 97 #define CLRSTCNT 0x10 98 #define SPIOEN 0x08 99 #define CLRCH 0x02 100 101 /* SXFRCTL1 */ 102 #define BITBUCKET 0x80 103 #define SWRAPEN 0x40 104 #define ENSPCHK 0x20 105 #define STIMESEL1 0x10 106 #define STIMESEL0 0x08 107 #define STIMO_256ms 0x00 108 #define STIMO_128ms 0x08 109 #define STIMO_64ms 0x10 110 #define STIMO_32ms 0x18 111 #define ENSTIMER 0x04 112 #define BYTEALIGN 0x02 113 114 /* SCSISIGI */ 115 #define CDI 0x80 116 #define IOI 0x40 117 #define MSGI 0x20 118 #define ATNI 0x10 119 #define SELI 0x08 120 #define BSYI 0x04 121 #define REQI 0x02 122 #define ACKI 0x01 123 124 /* Important! The 3 most significant bits of this register, in initiator mode, 125 * represents the "expected" SCSI bus phase and can be used to trigger phase 126 * mismatch and phase change interrupts. But more important: If there is a 127 * phase mismatch the chip will not transfer any data! This is actually a nice 128 * feature as it gives us a bit more control over what is happening when we are 129 * bursting data (in) through the FIFOs and the phase suddenly changes from 130 * DATA IN to STATUS or MESSAGE IN. The transfer will stop and wait for the 131 * proper phase to be set in this register instead of dumping the bits into the 132 * FIFOs. 133 */ 134 /* SCSISIGO */ 135 #define CDO 0x80 136 #define IOO 0x40 137 #define MSGO 0x20 138 #define ATNO 0x10 139 #define SELO 0x08 140 #define BSYO 0x04 141 #define REQO 0x02 142 #define ACKO 0x01 143 144 /* Information transfer phases */ 145 #define PH_DATAOUT (0) 146 #define PH_DATAIN (IOI) 147 #define PH_CMD (CDI) 148 #define PH_STAT (CDI|IOI) 149 #define PH_MSGOUT (MSGI|CDI) 150 #define PH_MSGIN (MSGI|CDI|IOI) 151 #define PH_MASK (MSGI|CDI|IOI) 152 153 /* SCSIRATE */ 154 #define SXFR2 0x40 155 #define SXFR1 0x20 156 #define SXFR0 0x10 157 #define SOFS3 0x08 158 #define SOFS2 0x04 159 #define SOFS1 0x02 160 #define SOFS0 0x01 161 162 /* SCSI ID */ 163 #define OID2 0x40 164 #define OID1 0x20 165 #define OID0 0x10 166 #define OID_S 4 /* shift value */ 167 #define TID2 0x04 168 #define TID1 0x02 169 #define TID0 0x01 170 #define SCSI_ID_MASK 0x7 171 172 /* SCSI selection/reselection ID (both target *and* initiator) */ 173 #define SELID7 0x80 174 #define SELID6 0x40 175 #define SELID5 0x20 176 #define SELID4 0x10 177 #define SELID3 0x08 178 #define SELID2 0x04 179 #define SELID1 0x02 180 #define SELID0 0x01 181 182 /* CLRSINT0 Clears what? (interrupt and/or status bit) */ 183 #define SETSDONE 0x80 184 #define CLRSELDO 0x40 /* I */ 185 #define CLRSELDI 0x20 /* I+ */ 186 #define CLRSELINGO 0x10 /* I */ 187 #define CLRSWRAP 0x08 /* I+S */ 188 #define CLRSDONE 0x04 /* I+S */ 189 #define CLRSPIORDY 0x02 /* I */ 190 #define CLRDMADONE 0x01 /* I */ 191 192 /* SSTAT0 Howto clear */ 193 #define TARGET 0x80 194 #define SELDO 0x40 /* Selfclearing */ 195 #define SELDI 0x20 /* Selfclearing when CLRSELDI is set */ 196 #define SELINGO 0x10 /* Selfclearing */ 197 #define SWRAP 0x08 /* CLRSWAP */ 198 #define SDONE 0x04 /* Not used in initiator mode */ 199 #define SPIORDY 0x02 /* Selfclearing (op on SCSIDAT) */ 200 #define DMADONE 0x01 /* Selfclearing (all FIFOs empty & T/C */ 201 202 /* CLRSINT1 Clears what? */ 203 #define CLRSELTIMO 0x80 /* I+S */ 204 #define CLRATNO 0x40 205 #define CLRSCSIRSTI 0x20 /* I+S */ 206 #define CLRBUSFREE 0x08 /* I+S */ 207 #define CLRSCSIPERR 0x04 /* I+S */ 208 #define CLRPHASECHG 0x02 /* I+S */ 209 #define CLRREQINIT 0x01 /* I+S */ 210 211 /* SSTAT1 How to clear? When set?*/ 212 #define SELTO 0x80 /* C select out timeout */ 213 #define ATNTARG 0x40 /* Not used in initiator mode */ 214 #define SCSIRSTI 0x20 /* C RST asserted */ 215 #define PHASEMIS 0x10 /* Selfclearing */ 216 #define BUSFREE 0x08 /* C bus free condition */ 217 #define SCSIPERR 0x04 /* C parity error on inbound data */ 218 #define PHASECHG 0x02 /* C phase in SCSISIGI doesn't match */ 219 #define REQINIT 0x01 /* C or ACK asserting edge of REQ */ 220 221 /* SSTAT2 */ 222 #define SOFFSET 0x20 223 #define SEMPTY 0x10 224 #define SFULL 0x08 225 #define SFCNT2 0x04 226 #define SFCNT1 0x02 227 #define SFCNT0 0x01 228 229 /* SCSITEST */ 230 #define SCTESTU 0x08 231 #define SCTESTD 0x04 232 #define STCTEST 0x01 233 234 /* SSTAT3 */ 235 #define SCSICNT3 0x80 236 #define SCSICNT2 0x40 237 #define SCSICNT1 0x20 238 #define SCSICNT0 0x10 239 #define OFFCNT3 0x08 240 #define OFFCNT2 0x04 241 #define OFFCNT1 0x02 242 #define OFFCNT0 0x01 243 244 /* CLRSERR */ 245 #define CLRSYNCERR 0x04 246 #define CLRFWERR 0x02 247 #define CLRFRERR 0x01 248 249 /* SSTAT4 */ 250 #define SYNCERR 0x04 251 #define FWERR 0x02 252 #define FRERR 0x01 253 254 /* SIMODE0 */ 255 #define ENSELDO 0x40 256 #define ENSELDI 0x20 257 #define ENSELINGO 0x10 258 #define ENSWRAP 0x08 259 #define ENSDONE 0x04 260 #define ENSPIORDY 0x02 261 #define ENDMADONE 0x01 262 263 /* SIMODE1 */ 264 #define ENSELTIMO 0x80 265 #define ENATNTARG 0x40 266 #define ENSCSIRST 0x20 267 #define ENPHASEMIS 0x10 268 #define ENBUSFREE 0x08 269 #define ENSCSIPERR 0x04 270 #define ENPHASECHG 0x02 271 #define ENREQINIT 0x01 272 273 /* DMACNTRL0 */ 274 #define ENDMA 0x80 275 #define B8MODE 0x40 276 #define DMA 0x20 277 #define DWORDPIO 0x10 278 #define WRITE 0x08 279 #define INTEN 0x04 280 #define RSTFIFO 0x02 281 #define SWINT 0x01 282 283 /* DMACNTRL1 */ 284 #define PWRDWN 0x80 285 #define ENSTK32 0x40 286 #define STK4 0x10 287 #define STK3 0x08 288 #define STK2 0x04 289 #define STK1 0x02 290 #define STK0 0x01 291 292 /* DMASTAT */ 293 #define ATDONE 0x80 294 #define WORDRDY 0x40 295 #define INTSTAT 0x20 296 #define DFIFOFULL 0x10 297 #define DFIFOEMP 0x08 298 #define DFIFOHF 0x04 299 #define DWORDRDY 0x02 300 301 /* BRSTCNTRL */ 302 #define BON3 0x80 303 #define BON2 0x40 304 #define BON1 0x20 305 #define BON0 0x10 306 #define BOFF3 0x08 307 #define BOFF2 0x04 308 #define BOFF1 0x02 309 #define BOFF0 0x01 310 311 /* TEST */ 312 #define BOFFTMR 0x40 313 #define BONTMR 0x20 314 #define STCNTH 0x10 315 #define STCNTM 0x08 316 #define STCNTL 0x04 317 #define SCSIBLK 0x02 318 #define DMABLK 0x01 319 320 /* PORTA */ 321 #define PORTA_ID(a) ((a) & 7) 322 #define PORTA_IRQ(a) ((((a) >> 3) & 3) + 9) 323 #define PORTA_DRQ(a) ((((a) >> 5) & 3) ? (((a) >> 5) & 3) + 4 : 0) 324 #define PORTA_PARITY(a) ((a) & 0x80) 325 326 /* PORTB */ 327 #define PORTB_EXTTRAN(b)((b) & 1) 328 #define PORTB_DISC(b) ((b) & 4) 329 #define PORTB_SYNC(b) ((b) & 8) 330 #define PORTB_FSYNC(b) ((b) & 0x10) 331 #define PORTB_BOOT(b) ((b) & 0x40) 332 #define PORTB_DMA(b) ((b) & 0x80) 333 334 /* How to behave on the (E)ISA bus when/if DMAing (on<<4) + off in us */ 335 #define EISA_BRST_TIM ((15<<4) + 1) /* 15us on, 1us off */ 336 337 #define FIFOSIZE 128 338