1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(C) 2021 Marvell.
3  */
4 
5 #ifndef _ROC_BPHY_CGX_PRIV_H_
6 #define _ROC_BPHY_CGX_PRIV_H_
7 
8 /* LINK speed types */
9 enum eth_link_speed {
10 	ETH_LINK_NONE,
11 	ETH_LINK_10M,
12 	ETH_LINK_100M,
13 	ETH_LINK_1G,
14 	ETH_LINK_2HG, /* 2.5 Gbps */
15 	ETH_LINK_5G,
16 	ETH_LINK_10G,
17 	ETH_LINK_20G,
18 	ETH_LINK_25G,
19 	ETH_LINK_40G,
20 	ETH_LINK_50G,
21 	ETH_LINK_80G,
22 	ETH_LINK_100G,
23 	ETH_LINK_MAX,
24 };
25 
26 /* Supported LINK MODE enums
27  * Each link mode is a bit mask of these
28  * enums which are represented as bits
29  */
30 enum eth_mode {
31 	ETH_MODE_SGMII_BIT = 0,
32 	ETH_MODE_1000_BASEX_BIT,
33 	ETH_MODE_QSGMII_BIT,
34 	ETH_MODE_10G_C2C_BIT,
35 	ETH_MODE_10G_C2M_BIT,
36 	ETH_MODE_10G_KR_BIT, /* = 5 */
37 	ETH_MODE_20G_C2C_BIT,
38 	ETH_MODE_25G_C2C_BIT,
39 	ETH_MODE_25G_C2M_BIT,
40 	ETH_MODE_25G_2_C2C_BIT,
41 	ETH_MODE_25G_CR_BIT, /* = 10 */
42 	ETH_MODE_25G_KR_BIT,
43 	ETH_MODE_40G_C2C_BIT,
44 	ETH_MODE_40G_C2M_BIT,
45 	ETH_MODE_40G_CR4_BIT,
46 	ETH_MODE_40G_KR4_BIT, /* = 15 */
47 	ETH_MODE_40GAUI_C2C_BIT,
48 	ETH_MODE_50G_C2C_BIT,
49 	ETH_MODE_50G_C2M_BIT,
50 	ETH_MODE_50G_4_C2C_BIT,
51 	ETH_MODE_50G_CR_BIT, /* = 20 */
52 	ETH_MODE_50G_KR_BIT,
53 	ETH_MODE_80GAUI_C2C_BIT,
54 	ETH_MODE_100G_C2C_BIT,
55 	ETH_MODE_100G_C2M_BIT,
56 	ETH_MODE_100G_CR4_BIT, /* = 25 */
57 	ETH_MODE_100G_KR4_BIT,
58 	ETH_MODE_MAX_BIT /* = 27 */
59 };
60 
61 /* REQUEST ID types. Input to firmware */
62 enum eth_cmd_id {
63 	ETH_CMD_GET_LINK_STS = 4,
64 	ETH_CMD_LINK_BRING_UP = 5,
65 	ETH_CMD_LINK_BRING_DOWN = 6,
66 	ETH_CMD_INTERNAL_LBK = 7,
67 	ETH_CMD_MODE_CHANGE = 11, /* hot plug support */
68 	ETH_CMD_INTF_SHUTDOWN = 12,
69 	ETH_CMD_GET_SUPPORTED_FEC = 18,
70 	ETH_CMD_SET_FEC = 19,
71 	ETH_CMD_SET_PTP_MODE = 34,
72 };
73 
74 /* event types - cause of interrupt */
75 enum eth_evt_type {
76 	ETH_EVT_ASYNC,
77 	ETH_EVT_CMD_RESP,
78 };
79 
80 enum eth_stat {
81 	ETH_STAT_SUCCESS,
82 	ETH_STAT_FAIL,
83 };
84 
85 enum eth_cmd_own {
86 	/* default ownership with kernel/uefi/u-boot */
87 	ETH_OWN_NON_SECURE_SW,
88 	/* set by kernel/uefi/u-boot after posting a new request to ATF */
89 	ETH_OWN_FIRMWARE,
90 };
91 
92 /* scratchx(0) CSR used for ATF->non-secure SW communication.
93  * This acts as the status register
94  * Provides details on command ack/status, link status, error details
95  */
96 
97 /* struct eth_evt_sts_s */
98 #define SCR0_ETH_EVT_STS_S_ACK	    BIT_ULL(0)
99 #define SCR0_ETH_EVT_STS_S_EVT_TYPE BIT_ULL(1)
100 #define SCR0_ETH_EVT_STS_S_STAT	    BIT_ULL(2)
101 #define SCR0_ETH_EVT_STS_S_ID	    GENMASK_ULL(8, 3)
102 
103 /* struct eth_lnk_sts_s */
104 #define SCR0_ETH_LNK_STS_S_LINK_UP     BIT_ULL(9)
105 #define SCR0_ETH_LNK_STS_S_FULL_DUPLEX BIT_ULL(10)
106 #define SCR0_ETH_LNK_STS_S_SPEED       GENMASK_ULL(14, 11)
107 #define SCR0_ETH_LNK_STS_S_ERR_TYPE    GENMASK_ULL(24, 15)
108 #define SCR0_ETH_LNK_STS_S_AN	       BIT_ULL(25)
109 #define SCR0_ETH_LNK_STS_S_FEC	       GENMASK_ULL(27, 26)
110 #define SCR0_ETH_LNK_STS_S_LMAC_TYPE   GENMASK_ULL(35, 28)
111 #define SCR0_ETH_LNK_STS_S_MODE	       GENMASK_ULL(43, 36)
112 
113 /* struct eth_fec_types_s */
114 #define SCR0_ETH_FEC_TYPES_S_FEC GENMASK_ULL(10, 9)
115 
116 /* scratchx(1) CSR used for non-secure SW->ATF communication
117  * This CSR acts as a command register
118  */
119 
120 /* struct eth_cmd */
121 #define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2)
122 
123 /* struct eth_ctl_args */
124 #define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8)
125 
126 /* struct eth_mode_change_args */
127 #define SCR1_ETH_MODE_CHANGE_ARGS_SPEED	 GENMASK_ULL(11, 8)
128 #define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12)
129 #define SCR1_ETH_MODE_CHANGE_ARGS_AN	 BIT_ULL(13)
130 #define SCR1_ETH_MODE_CHANGE_ARGS_PORT	 GENMASK_ULL(21, 14)
131 #define SCR1_ETH_MODE_CHANGE_ARGS_MODE	 GENMASK_ULL(63, 22)
132 
133 /* struct eth_set_fec_args */
134 #define SCR1_ETH_SET_FEC_ARGS GENMASK_ULL(9, 8)
135 
136 #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
137 
138 #endif /* _ROC_BPHY_CGX_PRIV_H_ */
139