1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _E1000_DEFINES_H_ 6 #define _E1000_DEFINES_H_ 7 8 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 9 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 10 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 11 12 /* Definitions for power management and wakeup registers */ 13 /* Wake Up Control */ 14 #define E1000_WUC_APME 0x00000001 /* APM Enable */ 15 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 16 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 17 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 18 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 19 20 /* Wake Up Filter Control */ 21 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 22 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 23 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 24 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 25 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 26 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 27 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 28 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 29 30 /* Wake Up Status */ 31 #define E1000_WUS_LNKC E1000_WUFC_LNKC 32 #define E1000_WUS_MAG E1000_WUFC_MAG 33 #define E1000_WUS_EX E1000_WUFC_EX 34 #define E1000_WUS_MC E1000_WUFC_MC 35 #define E1000_WUS_BC E1000_WUFC_BC 36 37 /* Extended Device Control */ 38 #define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ 39 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */ 40 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */ 41 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */ 42 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */ 43 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 44 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 45 #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */ 46 #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ 47 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 48 /* Physical Func Reset Done Indication */ 49 #define E1000_CTRL_EXT_PFRSTD 0x00004000 50 #define E1000_CTRL_EXT_SDLPE 0X00040000 /* SerDes Low Power Enable */ 51 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 52 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 53 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */ 54 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 55 /* Offset of the link mode field in Ctrl Ext register */ 56 #define E1000_CTRL_EXT_LINK_MODE_OFFSET 22 57 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 58 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 59 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 60 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 61 #define E1000_CTRL_EXT_EIAME 0x01000000 62 #define E1000_CTRL_EXT_IRCA 0x00000001 63 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */ 64 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ 65 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 66 #define E1000_CTRL_EXT_LSECCK 0x00001000 67 #define E1000_CTRL_EXT_PHYPDEN 0x00100000 68 #define E1000_I2CCMD_REG_ADDR_SHIFT 16 69 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24 70 #define E1000_I2CCMD_OPCODE_READ 0x08000000 71 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000 72 #define E1000_I2CCMD_READY 0x20000000 73 #define E1000_I2CCMD_ERROR 0x80000000 74 #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a)) 75 #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a)) 76 #define E1000_MAX_SGMII_PHY_REG_ADDR 255 77 #define E1000_I2CCMD_PHY_TIMEOUT 200 78 #define E1000_IVAR_VALID 0x80 79 #define E1000_GPIE_NSICR 0x00000001 80 #define E1000_GPIE_MSIX_MODE 0x00000010 81 #define E1000_GPIE_EIAME 0x40000000 82 #define E1000_GPIE_PBA 0x80000000 83 84 /* Receive Descriptor bit definitions */ 85 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 86 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 87 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 88 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 89 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 90 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 91 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 92 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 93 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 94 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 95 #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 96 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 97 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 98 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 99 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 100 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 101 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 102 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 103 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 104 105 #define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */ 106 #define E1000_RXDEXT_STATERR_LB 0x00040000 107 #define E1000_RXDEXT_STATERR_CE 0x01000000 108 #define E1000_RXDEXT_STATERR_SE 0x02000000 109 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 110 #define E1000_RXDEXT_STATERR_CXE 0x10000000 111 #define E1000_RXDEXT_STATERR_TCPE 0x20000000 112 #define E1000_RXDEXT_STATERR_IPE 0x40000000 113 #define E1000_RXDEXT_STATERR_RXE 0x80000000 114 115 /* mask to determine if packets should be dropped due to frame errors */ 116 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 117 E1000_RXD_ERR_CE | \ 118 E1000_RXD_ERR_SE | \ 119 E1000_RXD_ERR_SEQ | \ 120 E1000_RXD_ERR_CXE | \ 121 E1000_RXD_ERR_RXE) 122 123 /* Same mask, but for extended and packet split descriptors */ 124 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 125 E1000_RXDEXT_STATERR_CE | \ 126 E1000_RXDEXT_STATERR_SE | \ 127 E1000_RXDEXT_STATERR_SEQ | \ 128 E1000_RXDEXT_STATERR_CXE | \ 129 E1000_RXDEXT_STATERR_RXE) 130 131 #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 132 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 133 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 134 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 135 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 136 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 137 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 138 139 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 140 141 /* Management Control */ 142 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 143 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 144 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 145 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 146 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 147 /* Enable MAC address filtering */ 148 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 149 /* Enable MNG packets to host memory */ 150 #define E1000_MANC_EN_MNG2HOST 0x00200000 151 152 #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ 153 #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ 154 #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */ 155 #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */ 156 157 /* Receive Control */ 158 #define E1000_RCTL_RST 0x00000001 /* Software reset */ 159 #define E1000_RCTL_EN 0x00000002 /* enable */ 160 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 161 #define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */ 162 #define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */ 163 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 164 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 165 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 166 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 167 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 168 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ 169 #define E1000_RCTL_RDMTS_HEX 0x00010000 170 #define E1000_RCTL_RDMTS1_HEX E1000_RCTL_RDMTS_HEX 171 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 172 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 173 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 174 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 175 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 176 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 177 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 178 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 179 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 180 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ 181 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ 182 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ 183 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 184 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 185 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 186 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 187 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 188 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 189 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 190 191 /* Use byte values for the following shift parameters 192 * Usage: 193 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 194 * E1000_PSRCTL_BSIZE0_MASK) | 195 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 196 * E1000_PSRCTL_BSIZE1_MASK) | 197 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 198 * E1000_PSRCTL_BSIZE2_MASK) | 199 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 200 * E1000_PSRCTL_BSIZE3_MASK)) 201 * where value0 = [128..16256], default=256 202 * value1 = [1024..64512], default=4096 203 * value2 = [0..64512], default=4096 204 * value3 = [0..64512], default=0 205 */ 206 207 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 208 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 209 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 210 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 211 212 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 213 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 214 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 215 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 216 217 /* SWFW_SYNC Definitions */ 218 #define E1000_SWFW_EEP_SM 0x01 219 #define E1000_SWFW_PHY0_SM 0x02 220 #define E1000_SWFW_PHY1_SM 0x04 221 #define E1000_SWFW_CSR_SM 0x08 222 #define E1000_SWFW_PHY2_SM 0x20 223 #define E1000_SWFW_PHY3_SM 0x40 224 #define E1000_SWFW_SW_MNG_SM 0x400 225 226 /* Device Control */ 227 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 228 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 229 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */ 230 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 231 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 232 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 233 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 234 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 235 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 236 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 237 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 238 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 239 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 240 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ 241 #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ 242 #define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ 243 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 244 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 245 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 246 #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ 247 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */ 248 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 249 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 250 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 251 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 252 #define E1000_CTRL_DEV_RST 0x20000000 /* Device reset */ 253 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 254 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 255 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 256 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 257 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 258 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ 259 260 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 261 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 262 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 263 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 264 265 #define E1000_CONNSW_ENRGSRC 0x4 266 #define E1000_CONNSW_PHYSD 0x400 267 #define E1000_CONNSW_PHY_PDN 0x800 268 #define E1000_CONNSW_SERDESD 0x200 269 #define E1000_CONNSW_AUTOSENSE_CONF 0x2 270 #define E1000_CONNSW_AUTOSENSE_EN 0x1 271 #define E1000_PCS_CFG_PCS_EN 8 272 #define E1000_PCS_LCTL_FLV_LINK_UP 1 273 #define E1000_PCS_LCTL_FSV_10 0 274 #define E1000_PCS_LCTL_FSV_100 2 275 #define E1000_PCS_LCTL_FSV_1000 4 276 #define E1000_PCS_LCTL_FDV_FULL 8 277 #define E1000_PCS_LCTL_FSD 0x10 278 #define E1000_PCS_LCTL_FORCE_LINK 0x20 279 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 280 #define E1000_PCS_LCTL_AN_ENABLE 0x10000 281 #define E1000_PCS_LCTL_AN_RESTART 0x20000 282 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 283 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410 284 285 #define E1000_PCS_LSTS_LINK_OK 1 286 #define E1000_PCS_LSTS_SPEED_100 2 287 #define E1000_PCS_LSTS_SPEED_1000 4 288 #define E1000_PCS_LSTS_DUPLEX_FULL 8 289 #define E1000_PCS_LSTS_SYNK_OK 0x10 290 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 291 292 /* Device Status */ 293 #define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */ 294 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 295 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 296 #define E1000_STATUS_FUNC_SHIFT 2 297 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 298 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 299 #define E1000_STATUS_SPEED_MASK 0x000000C0 300 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 301 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 302 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 303 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */ 304 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 305 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ 306 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 307 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 308 #define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */ 309 #define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */ 310 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 311 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 312 313 /* Constants used to interpret the masked PCI-X bus speed. */ 314 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */ 315 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */ 316 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/ 317 #define E1000_STATUS_PCIM_STATE 0x40000000 /* PCIm function state */ 318 319 #define SPEED_10 10 320 #define SPEED_100 100 321 #define SPEED_1000 1000 322 #define SPEED_2500 2500 323 #define HALF_DUPLEX 1 324 #define FULL_DUPLEX 2 325 326 #define PHY_FORCE_TIME 20 327 328 #define ADVERTISE_10_HALF 0x0001 329 #define ADVERTISE_10_FULL 0x0002 330 #define ADVERTISE_100_HALF 0x0004 331 #define ADVERTISE_100_FULL 0x0008 332 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 333 #define ADVERTISE_1000_FULL 0x0020 334 335 /* 1000/H is not supported, nor spec-compliant. */ 336 #define E1000_ALL_SPEED_DUPLEX ( \ 337 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 338 ADVERTISE_100_FULL | ADVERTISE_1000_FULL) 339 #define E1000_ALL_NOT_GIG ( \ 340 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 341 ADVERTISE_100_FULL) 342 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 343 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 344 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 345 346 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 347 348 /* LED Control */ 349 #define E1000_PHY_LED0_MODE_MASK 0x00000007 350 #define E1000_PHY_LED0_IVRT 0x00000008 351 #define E1000_PHY_LED0_MASK 0x0000001F 352 353 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 354 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 355 #define E1000_LEDCTL_LED0_IVRT 0x00000040 356 #define E1000_LEDCTL_LED0_BLINK 0x00000080 357 358 #define E1000_LEDCTL_MODE_LINK_UP 0x2 359 #define E1000_LEDCTL_MODE_LED_ON 0xE 360 #define E1000_LEDCTL_MODE_LED_OFF 0xF 361 362 /* Transmit Descriptor bit definitions */ 363 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 364 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 365 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 366 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 367 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 368 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 369 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 370 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 371 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 372 #define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 373 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 374 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 375 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 376 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 377 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 378 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 379 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 380 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 381 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 382 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 383 #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ 384 385 /* Transmit Control */ 386 #define E1000_TCTL_EN 0x00000002 /* enable Tx */ 387 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 388 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 389 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 390 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 391 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 392 393 /* Transmit Arbitration Count */ 394 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */ 395 396 /* SerDes Control */ 397 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 398 #define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410 399 400 /* Receive Checksum Control */ 401 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 402 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 403 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 404 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 405 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 406 407 /* Header split receive */ 408 #define E1000_RFCTL_NFSW_DIS 0x00000040 409 #define E1000_RFCTL_NFSR_DIS 0x00000080 410 #define E1000_RFCTL_ACK_DIS 0x00001000 411 #define E1000_RFCTL_EXTEN 0x00008000 412 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 413 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 414 #define E1000_RFCTL_LEF 0x00040000 415 416 /* Collision related configuration parameters */ 417 #define E1000_CT_SHIFT 4 418 #define E1000_COLLISION_THRESHOLD 15 419 #define E1000_COLLISION_DISTANCE 63 420 #define E1000_COLD_SHIFT 12 421 422 /* Default values for the transmit IPG register */ 423 #define DEFAULT_82542_TIPG_IPGT 10 424 #define DEFAULT_82543_TIPG_IPGT_FIBER 9 425 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 426 427 #define E1000_TIPG_IPGT_MASK 0x000003FF 428 429 #define DEFAULT_82542_TIPG_IPGR1 2 430 #define DEFAULT_82543_TIPG_IPGR1 8 431 #define E1000_TIPG_IPGR1_SHIFT 10 432 433 #define DEFAULT_82542_TIPG_IPGR2 10 434 #define DEFAULT_82543_TIPG_IPGR2 6 435 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 436 #define E1000_TIPG_IPGR2_SHIFT 20 437 438 /* Ethertype field values */ 439 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 440 441 #define ETHERNET_FCS_SIZE 4 442 #define MAX_JUMBO_FRAME_SIZE 0x3F00 443 /* The datasheet maximum supported RX size is 9.5KB (9728 bytes) */ 444 #define MAX_RX_JUMBO_FRAME_SIZE 0x2600 445 #define E1000_TX_PTR_GAP 0x1F 446 447 /* Extended Configuration Control and Size */ 448 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 449 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 450 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 451 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 452 #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 453 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 454 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 455 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 456 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 457 458 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 459 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 460 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 461 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 462 463 #define E1000_KABGTXD_BGSQLBIAS 0x00050000 464 465 /* Low Power IDLE Control */ 466 #define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */ 467 468 /* PBA constants */ 469 #define E1000_PBA_8K 0x0008 /* 8KB */ 470 #define E1000_PBA_10K 0x000A /* 10KB */ 471 #define E1000_PBA_12K 0x000C /* 12KB */ 472 #define E1000_PBA_14K 0x000E /* 14KB */ 473 #define E1000_PBA_16K 0x0010 /* 16KB */ 474 #define E1000_PBA_18K 0x0012 475 #define E1000_PBA_20K 0x0014 476 #define E1000_PBA_22K 0x0016 477 #define E1000_PBA_24K 0x0018 478 #define E1000_PBA_26K 0x001A 479 #define E1000_PBA_30K 0x001E 480 #define E1000_PBA_32K 0x0020 481 #define E1000_PBA_34K 0x0022 482 #define E1000_PBA_35K 0x0023 483 #define E1000_PBA_38K 0x0026 484 #define E1000_PBA_40K 0x0028 485 #define E1000_PBA_48K 0x0030 /* 48KB */ 486 #define E1000_PBA_64K 0x0040 /* 64KB */ 487 488 #define E1000_PBA_RXA_MASK 0xFFFF 489 490 #define E1000_PBS_16K E1000_PBA_16K 491 492 /* Uncorrectable/correctable ECC Error counts and enable bits */ 493 #define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF 494 #define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00 495 #define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8 496 #define E1000_PBECCSTS_ECC_ENABLE 0x00010000 497 498 #define IFS_MAX 80 499 #define IFS_MIN 40 500 #define IFS_RATIO 4 501 #define IFS_STEP 10 502 #define MIN_NUM_XMITS 1000 503 504 /* SW Semaphore Register */ 505 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 506 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 507 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 508 509 #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 510 511 /* Interrupt Cause Read */ 512 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 513 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 514 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 515 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ 516 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ 517 #define E1000_ICR_RXO 0x00000040 /* Rx overrun */ 518 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ 519 #define E1000_ICR_VMMB 0x00000100 /* VM MB event */ 520 #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ 521 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 522 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 523 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 524 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 525 #define E1000_ICR_TXD_LOW 0x00008000 526 #define E1000_ICR_MNG 0x00040000 /* Manageability event */ 527 #define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ 528 #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */ 529 #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ 530 /* If this bit asserted, the driver should claim the interrupt */ 531 #define E1000_ICR_INT_ASSERTED 0x80000000 532 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 533 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 534 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 535 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 536 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 537 #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ 538 #define E1000_ICR_FER 0x00400000 /* Fatal Error */ 539 540 #define E1000_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/ 541 #define E1000_ICR_MDDET 0x10000000 /* Malicious Driver Detect */ 542 543 /* PBA ECC Register */ 544 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 545 #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 546 #define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ 547 #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 548 #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ 549 550 /* Extended Interrupt Cause Read */ 551 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 552 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 553 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 554 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 555 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 556 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 557 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 558 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 559 #define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 560 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 561 /* TCP Timer */ 562 #define E1000_TCPTIMER_KS 0x00000100 /* KickStart */ 563 #define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */ 564 #define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */ 565 #define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */ 566 567 /* This defines the bits that are set in the Interrupt Mask 568 * Set/Read Register. Each bit is documented below: 569 * o RXT0 = Receiver Timer Interrupt (ring 0) 570 * o TXDW = Transmit Descriptor Written Back 571 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 572 * o RXSEQ = Receive Sequence Error 573 * o LSC = Link Status Change 574 */ 575 #define IMS_ENABLE_MASK ( \ 576 E1000_IMS_RXT0 | \ 577 E1000_IMS_TXDW | \ 578 E1000_IMS_RXDMT0 | \ 579 E1000_IMS_RXSEQ | \ 580 E1000_IMS_LSC) 581 582 /* Interrupt Mask Set */ 583 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */ 584 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 585 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 586 #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ 587 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 588 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 589 #define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */ 590 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ 591 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 592 #define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */ 593 #define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */ 594 #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ 595 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 596 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 597 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 598 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 599 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 600 #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ 601 #define E1000_IMS_FER E1000_ICR_FER /* Fatal Error */ 602 603 #define E1000_IMS_THS E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/ 604 #define E1000_IMS_MDDET E1000_ICR_MDDET /* Malicious Driver Detect */ 605 /* Extended Interrupt Mask Set */ 606 #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 607 #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 608 #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 609 #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 610 #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 611 #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 612 #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 613 #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 614 #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 615 #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 616 617 /* Interrupt Cause Set */ 618 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 619 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 620 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 621 622 /* Extended Interrupt Cause Set */ 623 #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 624 #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 625 #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 626 #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 627 #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 628 #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 629 #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 630 #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 631 #define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 632 #define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 633 634 #define E1000_EITR_ITR_INT_MASK 0x0000FFFF 635 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */ 636 #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 637 #define E1000_EITR_INTERVAL 0x00007FFC 638 639 /* Transmit Descriptor Control */ 640 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 641 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 642 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 643 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 644 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 645 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 646 /* Enable the counting of descriptors still to be processed. */ 647 #define E1000_TXDCTL_COUNT_DESC 0x00400000 648 649 /* Flow Control Constants */ 650 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 651 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 652 #define FLOW_CONTROL_TYPE 0x8808 653 654 /* 802.1q VLAN Packet Size */ 655 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 656 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 657 658 /* Receive Address 659 * Number of high/low register pairs in the RAR. The RAR (Receive Address 660 * Registers) holds the directed and multicast addresses that we monitor. 661 * Technically, we have 16 spots. However, we reserve one of these spots 662 * (RAR[15]) for our directed address used by controllers with 663 * manageability enabled, allowing us room for 15 multicast addresses. 664 */ 665 #define E1000_RAR_ENTRIES 15 666 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 667 #define E1000_RAL_MAC_ADDR_LEN 4 668 #define E1000_RAH_MAC_ADDR_LEN 2 669 #define E1000_RAH_QUEUE_MASK_82575 0x000C0000 670 #define E1000_RAH_POOL_1 0x00040000 671 672 /* Error Codes */ 673 #define E1000_SUCCESS 0 674 #define E1000_ERR_NVM 1 675 #define E1000_ERR_PHY 2 676 #define E1000_ERR_CONFIG 3 677 #define E1000_ERR_PARAM 4 678 #define E1000_ERR_MAC_INIT 5 679 #define E1000_ERR_PHY_TYPE 6 680 #define E1000_ERR_RESET 9 681 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 682 #define E1000_ERR_HOST_INTERFACE_COMMAND 11 683 #define E1000_BLK_PHY_RESET 12 684 #define E1000_ERR_SWFW_SYNC 13 685 #define E1000_NOT_IMPLEMENTED 14 686 #define E1000_ERR_MBX 15 687 #define E1000_ERR_INVALID_ARGUMENT 16 688 #define E1000_ERR_NO_SPACE 17 689 #define E1000_ERR_NVM_PBA_SECTION 18 690 #define E1000_ERR_I2C 19 691 #define E1000_ERR_INVM_VALUE_NOT_FOUND 20 692 693 /* Loop limit on how long we wait for auto-negotiation to complete */ 694 #define FIBER_LINK_UP_LIMIT 50 695 #define COPPER_LINK_UP_LIMIT 10 696 #define PHY_AUTO_NEG_LIMIT 45 697 #define PHY_FORCE_LIMIT 20 698 /* Number of 100 microseconds we wait for PCI Express master disable */ 699 #define MASTER_DISABLE_TIMEOUT 800 700 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 701 #define PHY_CFG_TIMEOUT 100 702 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 703 #define MDIO_OWNERSHIP_TIMEOUT 10 704 /* Number of milliseconds for NVM auto read done after MAC reset. */ 705 #define AUTO_READ_DONE_TIMEOUT 10 706 707 /* Flow Control */ 708 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 709 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 710 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 711 712 /* Transmit Configuration Word */ 713 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 714 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 715 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 716 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 717 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 718 719 /* Receive Configuration Word */ 720 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 721 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 722 #define E1000_RXCW_C 0x20000000 /* Receive config */ 723 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 724 725 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 726 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ 727 728 /* HH Time Sync */ 729 #define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */ 730 #define E1000_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000 /* sync err */ 731 #define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */ 732 #define E1000_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */ 733 734 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 735 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 736 #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 737 #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 738 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 739 #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 740 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 741 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ 742 #define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ 743 744 #define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000 745 #define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000 746 747 #define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000 748 #define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000 749 750 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 751 #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 752 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 753 #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 754 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 755 #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 756 757 #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 758 #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 759 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 760 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 761 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 762 #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 763 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 764 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 765 #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 766 #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 767 #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 768 769 #define E1000_TIMINCA_16NS_SHIFT 24 770 #define E1000_TIMINCA_INCPERIOD_SHIFT 24 771 #define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF 772 773 /* ETQF register bit definitions */ 774 #define E1000_ETQF_1588 (1 << 30) 775 #define E1000_FTQF_VF_BP 0x00008000 776 #define E1000_FTQF_1588_TIME_STAMP 0x08000000 777 #define E1000_FTQF_MASK 0xF0000000 778 #define E1000_FTQF_MASK_PROTO_BP 0x10000000 779 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 780 #define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */ 781 #define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 782 783 #define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */ 784 #define E1000_TSICR_TXTS 0x00000002 785 #define E1000_TSIM_TXTS 0x00000002 786 /* TUPLE Filtering Configuration */ 787 #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */ 788 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */ 789 #define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */ 790 /* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */ 791 #define E1000_TTQF_PROTOCOL_TCP 0x0 792 /* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */ 793 #define E1000_TTQF_PROTOCOL_UDP 0x1 794 /* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */ 795 #define E1000_TTQF_PROTOCOL_SCTP 0x2 796 #define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */ 797 #define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */ 798 #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */ 799 #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */ 800 #define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */ 801 #define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */ 802 #define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */ 803 #define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */ 804 805 #define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ 806 #define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ 807 #define E1000_MDICNFG_PHY_MASK 0x03E00000 808 #define E1000_MDICNFG_PHY_SHIFT 21 809 810 #define E1000_MEDIA_PORT_COPPER 1 811 #define E1000_MEDIA_PORT_OTHER 2 812 #define E1000_M88E1112_AUTO_COPPER_SGMII 0x2 813 #define E1000_M88E1112_AUTO_COPPER_BASEX 0x3 814 #define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */ 815 #define E1000_M88E1112_MAC_CTRL_1 0x10 816 #define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */ 817 #define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7 818 #define E1000_M88E1112_PAGE_ADDR 0x16 819 #define E1000_M88E1112_STATUS 0x01 820 821 #define E1000_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */ 822 #define E1000_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */ 823 #define E1000_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */ 824 #define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */ 825 #define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */ 826 827 /* I350 EEE defines */ 828 #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ 829 #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ 830 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ 831 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ 832 #define E1000_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ 833 /* EEE status */ 834 #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ 835 #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */ 836 #define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */ 837 #define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */ 838 #define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */ 839 #define E1000_M88E1543_EEE_CTRL_1 0x0 840 #define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */ 841 #define E1000_M88E1543_FIBER_CTRL 0x0 /* Fiber Control Register */ 842 #define E1000_EEE_ADV_DEV_I354 7 843 #define E1000_EEE_ADV_ADDR_I354 60 844 #define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */ 845 #define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */ 846 #define E1000_PCS_STATUS_DEV_I354 3 847 #define E1000_PCS_STATUS_ADDR_I354 1 848 #define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400 849 #define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800 850 #define E1000_M88E1512_CFG_REG_1 0x0010 851 #define E1000_M88E1512_CFG_REG_2 0x0011 852 #define E1000_M88E1512_CFG_REG_3 0x0007 853 #define E1000_M88E1512_MODE 0x0014 854 #define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */ 855 #define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */ 856 #define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */ 857 /* PCI Express Control */ 858 #define E1000_GCR_RXD_NO_SNOOP 0x00000001 859 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 860 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 861 #define E1000_GCR_TXD_NO_SNOOP 0x00000008 862 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 863 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 864 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 865 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 866 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 867 #define E1000_GCR_CAP_VER2 0x00040000 868 869 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 870 E1000_GCR_RXDSCW_NO_SNOOP | \ 871 E1000_GCR_RXDSCR_NO_SNOOP | \ 872 E1000_GCR_TXD_NO_SNOOP | \ 873 E1000_GCR_TXDSCW_NO_SNOOP | \ 874 E1000_GCR_TXDSCR_NO_SNOOP) 875 876 #define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */ 877 878 /* mPHY address control and data registers */ 879 #define E1000_MPHY_ADDR_CTL 0x0024 /* Address Control Reg */ 880 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000 881 #define E1000_MPHY_DATA 0x0E10 /* Data Register */ 882 883 /* AFE CSR Offset for PCS CLK */ 884 #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 885 /* Override for near end digital loopback. */ 886 #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10 887 888 /* PHY Control Register */ 889 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 890 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 891 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 892 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 893 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 894 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 895 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 896 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 897 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 898 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 899 #define MII_CR_SPEED_1000 0x0040 900 #define MII_CR_SPEED_100 0x2000 901 #define MII_CR_SPEED_10 0x0000 902 903 /* PHY Status Register */ 904 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 905 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 906 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 907 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 908 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 909 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 910 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 911 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 912 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 913 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 914 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 915 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 916 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 917 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 918 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 919 920 /* Autoneg Advertisement Register */ 921 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 922 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 923 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 924 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 925 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 926 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 927 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 928 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 929 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 930 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 931 932 /* Link Partner Ability Register (Base Page) */ 933 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 934 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */ 935 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */ 936 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */ 937 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */ 938 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 939 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 940 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */ 941 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */ 942 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */ 943 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 944 945 /* Autoneg Expansion Register */ 946 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 947 #define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */ 948 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */ 949 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */ 950 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */ 951 952 /* 1000BASE-T Control Register */ 953 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 954 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 955 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 956 /* 1=Repeater/switch device port 0=DTE device */ 957 #define CR_1000T_REPEATER_DTE 0x0400 958 /* 1=Configure PHY as Master 0=Configure PHY as Slave */ 959 #define CR_1000T_MS_VALUE 0x0800 960 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ 961 #define CR_1000T_MS_ENABLE 0x1000 962 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 963 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 964 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 965 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 966 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 967 968 /* 1000BASE-T Status Register */ 969 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle err since last rd */ 970 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */ 971 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 972 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 973 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 974 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 975 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */ 976 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 977 978 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 979 980 /* PHY 1000 MII Register/Bit Definitions */ 981 /* PHY Registers defined by IEEE */ 982 #define PHY_CONTROL 0x00 /* Control Register */ 983 #define PHY_STATUS 0x01 /* Status Register */ 984 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 985 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 986 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 987 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 988 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 989 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */ 990 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 991 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 992 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 993 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 994 995 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ 996 997 /* NVM Control */ 998 #define E1000_EECD_SK 0x00000001 /* NVM Clock */ 999 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 1000 #define E1000_EECD_DI 0x00000004 /* NVM Data In */ 1001 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 1002 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 1003 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 1004 #define E1000_EECD_PRES 0x00000100 /* NVM Present */ 1005 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 1006 #define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */ 1007 #define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */ 1008 #define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */ 1009 #define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */ 1010 /* NVM Addressing bits based on type 0=small, 1=large */ 1011 #define E1000_EECD_ADDR_BITS 0x00000400 1012 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ 1013 #ifndef E1000_NVM_GRANT_ATTEMPTS 1014 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 1015 #endif 1016 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 1017 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 1018 #define E1000_EECD_SIZE_EX_SHIFT 11 1019 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 1020 #define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ 1021 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1022 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 1023 #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 1024 #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done */ 1025 #define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */ 1026 #define E1000_EECD_SEC1VAL_I210 0x02000000 /* Sector One Valid */ 1027 #define E1000_FLUDONE_ATTEMPTS 20000 1028 #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 1029 #define E1000_I210_FIFO_SEL_RX 0x00 1030 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) 1031 #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) 1032 #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 1033 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 1034 1035 #define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */ 1036 /* Secure FLASH mode requires removing MSb */ 1037 #define E1000_I210_FW_PTR_MASK 0x7FFF 1038 /* Firmware code revision field word offset*/ 1039 #define E1000_I210_FW_VER_OFFSET 328 1040 1041 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ 1042 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 1043 #define E1000_NVM_RW_REG_START 1 /* Start operation */ 1044 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1045 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 1046 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 1047 #define E1000_FLASH_UPDATES 2000 1048 1049 /* NVM Word Offsets */ 1050 #define NVM_COMPAT 0x0003 1051 #define NVM_ID_LED_SETTINGS 0x0004 1052 #define NVM_VERSION 0x0005 1053 #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ 1054 #define NVM_PHY_CLASS_WORD 0x0007 1055 #define E1000_I210_NVM_FW_MODULE_PTR 0x0010 1056 #define E1000_I350_NVM_FW_MODULE_PTR 0x0051 1057 #define NVM_FUTURE_INIT_WORD1 0x0019 1058 #define NVM_ETRACK_WORD 0x0042 1059 #define NVM_ETRACK_HIWORD 0x0043 1060 #define NVM_COMB_VER_OFF 0x0083 1061 #define NVM_COMB_VER_PTR 0x003d 1062 1063 /* NVM version defines */ 1064 #define NVM_MAJOR_MASK 0xF000 1065 #define NVM_MINOR_MASK 0x0FF0 1066 #define NVM_IMAGE_ID_MASK 0x000F 1067 #define NVM_COMB_VER_MASK 0x00FF 1068 #define NVM_MAJOR_SHIFT 12 1069 #define NVM_MINOR_SHIFT 4 1070 #define NVM_COMB_VER_SHFT 8 1071 #define NVM_VER_INVALID 0xFFFF 1072 #define NVM_ETRACK_SHIFT 16 1073 #define NVM_ETRACK_VALID 0x8000 1074 #define NVM_NEW_DEC_MASK 0x0F00 1075 #define NVM_HEX_CONV 16 1076 #define NVM_HEX_TENS 10 1077 1078 /* FW version defines */ 1079 /* Offset of "Loader patch ptr" in Firmware Header */ 1080 #define E1000_I350_NVM_FW_LOADER_PATCH_PTR_OFFSET 0x01 1081 /* Patch generation hour & minutes */ 1082 #define E1000_I350_NVM_FW_VER_WORD1_OFFSET 0x04 1083 /* Patch generation month & day */ 1084 #define E1000_I350_NVM_FW_VER_WORD2_OFFSET 0x05 1085 /* Patch generation year */ 1086 #define E1000_I350_NVM_FW_VER_WORD3_OFFSET 0x06 1087 /* Patch major & minor numbers */ 1088 #define E1000_I350_NVM_FW_VER_WORD4_OFFSET 0x07 1089 1090 #define NVM_MAC_ADDR 0x0000 1091 #define NVM_SUB_DEV_ID 0x000B 1092 #define NVM_SUB_VEN_ID 0x000C 1093 #define NVM_DEV_ID 0x000D 1094 #define NVM_VEN_ID 0x000E 1095 #define NVM_INIT_CTRL_2 0x000F 1096 #define NVM_INIT_CTRL_4 0x0013 1097 #define NVM_LED_1_CFG 0x001C 1098 #define NVM_LED_0_2_CFG 0x001F 1099 1100 #define NVM_COMPAT_VALID_CSUM 0x0001 1101 #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 1102 1103 #define NVM_INIT_CONTROL2_REG 0x000F 1104 #define NVM_INIT_CONTROL3_PORT_B 0x0014 1105 #define NVM_INIT_3GIO_3 0x001A 1106 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 1107 #define NVM_INIT_CONTROL3_PORT_A 0x0024 1108 #define NVM_CFG 0x0012 1109 #define NVM_ALT_MAC_ADDR_PTR 0x0037 1110 #define NVM_CHECKSUM_REG 0x003F 1111 #define NVM_COMPATIBILITY_REG_3 0x0003 1112 #define NVM_COMPATIBILITY_BIT_MASK 0x8000 1113 1114 #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 1115 #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 1116 #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ 1117 #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ 1118 1119 #define NVM_82580_LAN_FUNC_OFFSET(a) ((a) ? (0x40 + (0x40 * (a))) : 0) 1120 1121 /* Mask bits for fields in Word 0x24 of the NVM */ 1122 #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ 1123 #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed extrnl */ 1124 /* Offset of Link Mode bits for 82575/82576 */ 1125 #define NVM_WORD24_LNK_MODE_OFFSET 8 1126 /* Offset of Link Mode bits for 82580 up */ 1127 #define NVM_WORD24_82580_LNK_MODE_OFFSET 4 1128 1129 1130 /* Mask bits for fields in Word 0x0f of the NVM */ 1131 #define NVM_WORD0F_PAUSE_MASK 0x3000 1132 #define NVM_WORD0F_PAUSE 0x1000 1133 #define NVM_WORD0F_ASM_DIR 0x2000 1134 #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 1135 1136 /* Mask bits for fields in Word 0x1a of the NVM */ 1137 #define NVM_WORD1A_ASPM_MASK 0x000C 1138 1139 /* Mask bits for fields in Word 0x03 of the EEPROM */ 1140 #define NVM_COMPAT_LOM 0x0800 1141 1142 /* length of string needed to store PBA number */ 1143 #define E1000_PBANUM_LENGTH 11 1144 1145 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 1146 #define NVM_SUM 0xBABA 1147 1148 /* PBA (printed board assembly) number words */ 1149 #define NVM_PBA_OFFSET_0 8 1150 #define NVM_PBA_OFFSET_1 9 1151 #define NVM_PBA_PTR_GUARD 0xFAFA 1152 #define NVM_RESERVED_WORD 0xFFFF 1153 #define NVM_PHY_CLASS_A 0x8000 1154 #define NVM_SERDES_AMPLITUDE_MASK 0x000F 1155 #define NVM_SIZE_MASK 0x1C00 1156 #define NVM_SIZE_SHIFT 10 1157 #define NVM_WORD_SIZE_BASE_SHIFT 6 1158 #define NVM_SWDPIO_EXT_SHIFT 4 1159 1160 /* NVM Commands - Microwire */ 1161 #define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */ 1162 #define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */ 1163 #define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */ 1164 #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */ 1165 #define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */ 1166 1167 /* NVM Commands - SPI */ 1168 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 1169 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 1170 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 1171 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 1172 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 1173 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 1174 1175 /* SPI NVM Status Register */ 1176 #define NVM_STATUS_RDY_SPI 0x01 1177 1178 /* Word definitions for ID LED Settings */ 1179 #define ID_LED_RESERVED_0000 0x0000 1180 #define ID_LED_RESERVED_FFFF 0xFFFF 1181 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 1182 (ID_LED_OFF1_OFF2 << 8) | \ 1183 (ID_LED_DEF1_DEF2 << 4) | \ 1184 (ID_LED_DEF1_DEF2)) 1185 #define ID_LED_DEF1_DEF2 0x1 1186 #define ID_LED_DEF1_ON2 0x2 1187 #define ID_LED_DEF1_OFF2 0x3 1188 #define ID_LED_ON1_DEF2 0x4 1189 #define ID_LED_ON1_ON2 0x5 1190 #define ID_LED_ON1_OFF2 0x6 1191 #define ID_LED_OFF1_DEF2 0x7 1192 #define ID_LED_OFF1_ON2 0x8 1193 #define ID_LED_OFF1_OFF2 0x9 1194 1195 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 1196 #define IGP_ACTIVITY_LED_ENABLE 0x0300 1197 #define IGP_LED3_MODE 0x07000000 1198 1199 /* PCI/PCI-X/PCI-EX Config space */ 1200 #define PCIX_COMMAND_REGISTER 0xE6 1201 #define PCIX_STATUS_REGISTER_LO 0xE8 1202 #define PCIX_STATUS_REGISTER_HI 0xEA 1203 #define PCI_HEADER_TYPE_REGISTER 0x0E 1204 #define PCIE_LINK_STATUS 0x12 1205 #define PCIE_DEVICE_CONTROL2 0x28 1206 1207 #define PCIX_COMMAND_MMRBC_MASK 0x000C 1208 #define PCIX_COMMAND_MMRBC_SHIFT 0x2 1209 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 1210 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 1211 #define PCIX_STATUS_HI_MMRBC_4K 0x3 1212 #define PCIX_STATUS_HI_MMRBC_2K 0x2 1213 #define PCIX_STATUS_LO_FUNC_MASK 0x7 1214 #define PCI_HEADER_TYPE_MULTIFUNC 0x80 1215 #define PCIE_LINK_WIDTH_MASK 0x3F0 1216 #define PCIE_LINK_WIDTH_SHIFT 4 1217 #define PCIE_LINK_SPEED_MASK 0x0F 1218 #define PCIE_LINK_SPEED_2500 0x01 1219 #define PCIE_LINK_SPEED_5000 0x02 1220 #define PCIE_DEVICE_CONTROL2_16ms 0x0005 1221 1222 #define ETH_ADDR_LEN 6 1223 1224 #define PHY_REVISION_MASK 0xFFFFFFF0 1225 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 1226 #define MAX_PHY_MULTI_PAGE_REG 0xF 1227 1228 /* Bit definitions for valid PHY IDs. 1229 * I = Integrated 1230 * E = External 1231 */ 1232 #define M88E1000_E_PHY_ID 0x01410C50 1233 #define M88E1000_I_PHY_ID 0x01410C30 1234 #define M88E1011_I_PHY_ID 0x01410C20 1235 #define IGP01E1000_I_PHY_ID 0x02A80380 1236 #define M88E1111_I_PHY_ID 0x01410CC0 1237 #define M88E1543_E_PHY_ID 0x01410EA0 1238 #define M88E1512_E_PHY_ID 0x01410DD0 1239 #define M88E1112_E_PHY_ID 0x01410C90 1240 #define I347AT4_E_PHY_ID 0x01410DC0 1241 #define M88E1340M_E_PHY_ID 0x01410DF0 1242 #define GG82563_E_PHY_ID 0x01410CA0 1243 #define IGP03E1000_E_PHY_ID 0x02A80390 1244 #define IFE_E_PHY_ID 0x02A80330 1245 #define IFE_PLUS_E_PHY_ID 0x02A80320 1246 #define IFE_C_E_PHY_ID 0x02A80310 1247 #define BME1000_E_PHY_ID 0x01410CB0 1248 #define BME1000_E_PHY_ID_R2 0x01410CB1 1249 #define I82577_E_PHY_ID 0x01540050 1250 #define I82578_E_PHY_ID 0x004DD040 1251 #define I82579_E_PHY_ID 0x01540090 1252 #define I217_E_PHY_ID 0x015400A0 1253 #define I82580_I_PHY_ID 0x015403A0 1254 #define I350_I_PHY_ID 0x015403B0 1255 #define I210_I_PHY_ID 0x01410C00 1256 #define IGP04E1000_E_PHY_ID 0x02A80391 1257 #define BCM54616_E_PHY_ID 0x03625D10 1258 #define M88_VENDOR 0x0141 1259 1260 /* M88E1000 Specific Registers */ 1261 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */ 1262 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */ 1263 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */ 1264 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 1265 1266 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 1267 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */ 1268 #define M88E1000_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */ 1269 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 1270 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 1271 1272 /* M88E1000 PHY Specific Control Register */ 1273 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */ 1274 /* MDI Crossover Mode bits 6:5 Manual MDI configuration */ 1275 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 1276 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 1277 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 1278 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 1279 /* Auto crossover enabled all speeds */ 1280 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 1281 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */ 1282 1283 /* M88E1000 PHY Specific Status Register */ 1284 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 1285 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 1286 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 1287 /* 0 = <50M 1288 * 1 = 50-80M 1289 * 2 = 80-110M 1290 * 3 = 110-140M 1291 * 4 = >140M 1292 */ 1293 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 1294 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 1295 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 1296 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 1297 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 1298 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 1299 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 1300 1301 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 1302 1303 /* Number of times we will attempt to autonegotiate before downshifting if we 1304 * are the master 1305 */ 1306 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 1307 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 1308 /* Number of times we will attempt to autonegotiate before downshifting if we 1309 * are the slave 1310 */ 1311 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 1312 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 1313 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 1314 1315 /* Intel I347AT4 Registers */ 1316 #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */ 1317 #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */ 1318 #define I347AT4_PAGE_SELECT 0x16 1319 1320 /* I347AT4 Extended PHY Specific Control Register */ 1321 1322 /* Number of times we will attempt to autonegotiate before downshifting if we 1323 * are the master 1324 */ 1325 #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800 1326 #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000 1327 #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000 1328 #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000 1329 #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000 1330 #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000 1331 #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000 1332 #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000 1333 #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000 1334 #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000 1335 1336 /* I347AT4 PHY Cable Diagnostics Control */ 1337 #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */ 1338 1339 /* M88E1112 only registers */ 1340 #define M88E1112_VCT_DSP_DISTANCE 0x001A 1341 1342 /* M88EC018 Rev 2 specific DownShift settings */ 1343 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 1344 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 1345 1346 #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 1347 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C 1348 1349 /* BME1000 PHY Specific Control Register */ 1350 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 1351 1352 /* Bits... 1353 * 15-5: page 1354 * 4-0: register offset 1355 */ 1356 #define GG82563_PAGE_SHIFT 5 1357 #define GG82563_REG(page, reg) \ 1358 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 1359 #define GG82563_MIN_ALT_REG 30 1360 1361 /* GG82563 Specific Registers */ 1362 #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */ 1363 #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */ 1364 #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */ 1365 #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */ 1366 1367 /* MAC Specific Control Register */ 1368 #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) 1369 1370 #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */ 1371 1372 /* Page 193 - Port Control Registers */ 1373 /* Kumeran Mode Control */ 1374 #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) 1375 #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */ 1376 1377 /* Page 194 - KMRN Registers */ 1378 #define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */ 1379 1380 /* MDI Control */ 1381 #define E1000_MDIC_REG_MASK 0x001F0000 1382 #define E1000_MDIC_REG_SHIFT 16 1383 #define E1000_MDIC_PHY_MASK 0x03E00000 1384 #define E1000_MDIC_PHY_SHIFT 21 1385 #define E1000_MDIC_OP_WRITE 0x04000000 1386 #define E1000_MDIC_OP_READ 0x08000000 1387 #define E1000_MDIC_READY 0x10000000 1388 #define E1000_MDIC_ERROR 0x40000000 1389 #define E1000_MDIC_DEST 0x80000000 1390 1391 #define E1000_VFTA_BLOCK_SIZE 8 1392 /* SerDes Control */ 1393 #define E1000_GEN_CTL_READY 0x80000000 1394 #define E1000_GEN_CTL_ADDRESS_SHIFT 8 1395 #define E1000_GEN_POLL_TIMEOUT 640 1396 1397 /* LinkSec register fields */ 1398 #define E1000_LSECTXCAP_SUM_MASK 0x00FF0000 1399 #define E1000_LSECTXCAP_SUM_SHIFT 16 1400 #define E1000_LSECRXCAP_SUM_MASK 0x00FF0000 1401 #define E1000_LSECRXCAP_SUM_SHIFT 16 1402 1403 #define E1000_LSECTXCTRL_EN_MASK 0x00000003 1404 #define E1000_LSECTXCTRL_DISABLE 0x0 1405 #define E1000_LSECTXCTRL_AUTH 0x1 1406 #define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2 1407 #define E1000_LSECTXCTRL_AISCI 0x00000020 1408 #define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 1409 #define E1000_LSECTXCTRL_RSV_MASK 0x000000D8 1410 1411 #define E1000_LSECRXCTRL_EN_MASK 0x0000000C 1412 #define E1000_LSECRXCTRL_EN_SHIFT 2 1413 #define E1000_LSECRXCTRL_DISABLE 0x0 1414 #define E1000_LSECRXCTRL_CHECK 0x1 1415 #define E1000_LSECRXCTRL_STRICT 0x2 1416 #define E1000_LSECRXCTRL_DROP 0x3 1417 #define E1000_LSECRXCTRL_PLSH 0x00000040 1418 #define E1000_LSECRXCTRL_RP 0x00000080 1419 #define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33 1420 1421 /* Tx Rate-Scheduler Config fields */ 1422 #define E1000_RTTBCNRC_RS_ENA 0x80000000 1423 #define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF 1424 #define E1000_RTTBCNRC_RF_INT_SHIFT 14 1425 #define E1000_RTTBCNRC_RF_INT_MASK \ 1426 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT) 1427 1428 /* DMA Coalescing register fields */ 1429 /* DMA Coalescing Watchdog Timer */ 1430 #define E1000_DMACR_DMACWT_MASK 0x00003FFF 1431 /* DMA Coalescing Rx Threshold */ 1432 #define E1000_DMACR_DMACTHR_MASK 0x00FF0000 1433 #define E1000_DMACR_DMACTHR_SHIFT 16 1434 /* Lx when no PCIe transactions */ 1435 #define E1000_DMACR_DMAC_LX_MASK 0x30000000 1436 #define E1000_DMACR_DMAC_LX_SHIFT 28 1437 #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ 1438 /* DMA Coalescing BMC-to-OS Watchdog Enable */ 1439 #define E1000_DMACR_DC_BMC2OSW_EN 0x00008000 1440 1441 /* DMA Coalescing Transmit Threshold */ 1442 #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF 1443 1444 #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ 1445 1446 /* Rx Traffic Rate Threshold */ 1447 #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF 1448 /* Rx packet rate in current window */ 1449 #define E1000_DMCRTRH_LRPRCW 0x80000000 1450 1451 /* DMA Coal Rx Traffic Current Count */ 1452 #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF 1453 1454 /* Flow ctrl Rx Threshold High val */ 1455 #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 1456 #define E1000_FCRTC_RTH_COAL_SHIFT 4 1457 /* Lx power decision based on DMA coal */ 1458 #define E1000_PCIEMISC_LX_DECISION 0x00000080 1459 1460 #define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */ 1461 #define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */ 1462 #define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */ 1463 #define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ 1464 #define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ 1465 1466 1467 /* Proxy Filter Control */ 1468 #define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */ 1469 #define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */ 1470 #define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */ 1471 #define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */ 1472 #define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */ 1473 #define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */ 1474 #define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */ 1475 #define E1000_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */ 1476 #define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */ 1477 /* Proxy Status */ 1478 #define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */ 1479 1480 /* Firmware Status */ 1481 #define E1000_FWSTS_FWRI 0x80000000 /* FW Reset Indication */ 1482 /* VF Control */ 1483 #define E1000_VTCTRL_RST 0x04000000 /* Reset VF */ 1484 1485 #define E1000_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */ 1486 /* Lan ID bit field offset in status register */ 1487 #define E1000_STATUS_LAN_ID_OFFSET 2 1488 #define E1000_VFTA_ENTRIES 128 1489 1490 #define E1000_UNUSEDARG 1491 #define ERROR_REPORT(fmt) do { } while (0) 1492 #endif /* _E1000_DEFINES_H_ */ 1493