| /freebsd-12.1/contrib/llvm/lib/Target/Lanai/ |
| H A D | LanaiCondCode.h | 10 enum CondCode { enum
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| H A D | LanaiInstrInfo.cpp | 523 unsigned CondCode = MI.getOperand(3).getImm(); in optimizeSelect() local
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| /freebsd-12.1/contrib/llvm/lib/Target/ARC/MCTargetDesc/ |
| H A D | ARCInfo.h | 25 enum CondCode { enum
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64SpeculationHardening.cpp | 226 MachineBasicBlock &SplitEdgeBB, AArch64CC::CondCode &CondCode, in insertTrackingCode()
247 AArch64CC::CondCode CondCode; in instrumentControlFlow() local
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| H A D | AArch64InstructionSelector.cpp | 542 AArch64CC::CondCode &CondCode, in changeFCMPPredToAArch64CC()
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| H A D | AArch64ISelLowering.cpp | 1242 unsigned CondCode = MI.getOperand(3).getImm(); in EmitF128CSEL() local
1354 AArch64CC::CondCode &CondCode, in changeFPCCToAArch64CC()
1417 AArch64CC::CondCode &CondCode, in changeFPCCToANDAArch64CC()
1447 AArch64CC::CondCode &CondCode, in changeVectorFPCCToAArch64CC()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/InstPrinter/ |
| H A D | MipsInstPrinter.h | 33 enum CondCode { enum
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 41 enum CondCode { enum
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| H A D | X86ISelLowering.cpp | 19767 X86::CondCode CondCode = TranslateX86CC(CC, dl, IsFP, Op0, Op1, DAG); in emitFlagsForSetcc() local
20034 unsigned CondCode = in LowerSELECT() local
20176 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); in LowerSELECT() local
33539 ISD::CondCode CondCode; in combineHorizontalPredicateResult() local
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| /freebsd-12.1/contrib/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.cpp | 38 enum CondCode { enum
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| /freebsd-12.1/contrib/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 1052 LPCC::CondCode CondCode = in splitMnemonic() local
1072 LPCC::CondCode CondCode = LPCC::suffixToLanaiCondCode(Mnemonic); in splitMnemonic() local
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 193 enum CondCode { // Meaning (integer) Meaning (floating-point) enum
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| /freebsd-12.1/contrib/llvm/lib/Target/MSP430/AsmParser/ |
| H A D | MSP430AsmParser.cpp | 318 unsigned CondCode; in parseJccInstruction() local
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 959 enum CondCode { enum
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| /freebsd-12.1/contrib/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelDAGToDAG.cpp | 536 static unsigned getPTXCmpMode(const CondCodeSDNode &CondCode, bool FTZ) { in getPTXCmpMode()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1546 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, in FPCCToARMCC()
3871 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); in getARMCmp() local
4151 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode, in checkVSELConstraints()
4477 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); in LowerSELECT_CC() local
4491 ARMCC::CondCodes CondCode, CondCode2; in LowerSELECT_CC() local
4634 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); in OptimizeVFPBrcond() local
4668 ARMCC::CondCodes CondCode = in LowerBRCOND() local
4721 ARMCC::CondCodes CondCode = in LowerBR_CC() local
4747 ARMCC::CondCodes CondCode, CondCode2; in LowerBR_CC() local
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| H A D | ARMBaseInstrInfo.cpp | 2132 unsigned CondCode = MI.getOperand(3).getImm(); in optimizeSelect() local
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 3753 int CondCode = CD->getSExtValue(); in lowerICMPIntrinsic() local
3787 int CondCode = CD->getSExtValue(); in lowerFCMPIntrinsic() local
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 5012 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); in Select() local
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 411 struct CondCodeOp CondCode; member
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