1 /***********************license start***************
2 * Copyright (c) 2003-2012 Cavium Inc. ([email protected]). All rights
3 * reserved.
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17
18 * * Neither the name of Cavium Inc. nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
21 * permission.
22
23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
25 * regulations, and may be subject to export or import regulations in other
26 * countries.
27
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
39
40
41 /**
42 * cvmx-iob-defs.h
43 *
44 * Configuration and status register (CSR) type definitions for
45 * Octeon iob.
46 *
47 * This file is auto generated. Do not edit.
48 *
49 * <hr>$Revision$<hr>
50 *
51 */
52 #ifndef __CVMX_IOB_DEFS_H__
53 #define __CVMX_IOB_DEFS_H__
54
55 #define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull))
56 #define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull))
57 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
58 #define CVMX_IOB_DWB_PRI_CNT CVMX_IOB_DWB_PRI_CNT_FUNC()
CVMX_IOB_DWB_PRI_CNT_FUNC(void)59 static inline uint64_t CVMX_IOB_DWB_PRI_CNT_FUNC(void)
60 {
61 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
62 cvmx_warn("CVMX_IOB_DWB_PRI_CNT not supported on this chip\n");
63 return CVMX_ADD_IO_SEG(0x00011800F0000028ull);
64 }
65 #else
66 #define CVMX_IOB_DWB_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000028ull))
67 #endif
68 #define CVMX_IOB_FAU_TIMEOUT (CVMX_ADD_IO_SEG(0x00011800F0000000ull))
69 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
70 #define CVMX_IOB_I2C_PRI_CNT CVMX_IOB_I2C_PRI_CNT_FUNC()
CVMX_IOB_I2C_PRI_CNT_FUNC(void)71 static inline uint64_t CVMX_IOB_I2C_PRI_CNT_FUNC(void)
72 {
73 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
74 cvmx_warn("CVMX_IOB_I2C_PRI_CNT not supported on this chip\n");
75 return CVMX_ADD_IO_SEG(0x00011800F0000010ull);
76 }
77 #else
78 #define CVMX_IOB_I2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000010ull))
79 #endif
80 #define CVMX_IOB_INB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000078ull))
81 #define CVMX_IOB_INB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000088ull))
82 #define CVMX_IOB_INB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000070ull))
83 #define CVMX_IOB_INB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000080ull))
84 #define CVMX_IOB_INT_ENB (CVMX_ADD_IO_SEG(0x00011800F0000060ull))
85 #define CVMX_IOB_INT_SUM (CVMX_ADD_IO_SEG(0x00011800F0000058ull))
86 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
87 #define CVMX_IOB_N2C_L2C_PRI_CNT CVMX_IOB_N2C_L2C_PRI_CNT_FUNC()
CVMX_IOB_N2C_L2C_PRI_CNT_FUNC(void)88 static inline uint64_t CVMX_IOB_N2C_L2C_PRI_CNT_FUNC(void)
89 {
90 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
91 cvmx_warn("CVMX_IOB_N2C_L2C_PRI_CNT not supported on this chip\n");
92 return CVMX_ADD_IO_SEG(0x00011800F0000020ull);
93 }
94 #else
95 #define CVMX_IOB_N2C_L2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000020ull))
96 #endif
97 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
98 #define CVMX_IOB_N2C_RSP_PRI_CNT CVMX_IOB_N2C_RSP_PRI_CNT_FUNC()
CVMX_IOB_N2C_RSP_PRI_CNT_FUNC(void)99 static inline uint64_t CVMX_IOB_N2C_RSP_PRI_CNT_FUNC(void)
100 {
101 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
102 cvmx_warn("CVMX_IOB_N2C_RSP_PRI_CNT not supported on this chip\n");
103 return CVMX_ADD_IO_SEG(0x00011800F0000008ull);
104 }
105 #else
106 #define CVMX_IOB_N2C_RSP_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000008ull))
107 #endif
108 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
109 #define CVMX_IOB_OUTB_COM_PRI_CNT CVMX_IOB_OUTB_COM_PRI_CNT_FUNC()
CVMX_IOB_OUTB_COM_PRI_CNT_FUNC(void)110 static inline uint64_t CVMX_IOB_OUTB_COM_PRI_CNT_FUNC(void)
111 {
112 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
113 cvmx_warn("CVMX_IOB_OUTB_COM_PRI_CNT not supported on this chip\n");
114 return CVMX_ADD_IO_SEG(0x00011800F0000040ull);
115 }
116 #else
117 #define CVMX_IOB_OUTB_COM_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000040ull))
118 #endif
119 #define CVMX_IOB_OUTB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000098ull))
120 #define CVMX_IOB_OUTB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A8ull))
121 #define CVMX_IOB_OUTB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000090ull))
122 #define CVMX_IOB_OUTB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A0ull))
123 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
124 #define CVMX_IOB_OUTB_FPA_PRI_CNT CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC()
CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC(void)125 static inline uint64_t CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC(void)
126 {
127 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
128 cvmx_warn("CVMX_IOB_OUTB_FPA_PRI_CNT not supported on this chip\n");
129 return CVMX_ADD_IO_SEG(0x00011800F0000048ull);
130 }
131 #else
132 #define CVMX_IOB_OUTB_FPA_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000048ull))
133 #endif
134 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
135 #define CVMX_IOB_OUTB_REQ_PRI_CNT CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC()
CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC(void)136 static inline uint64_t CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC(void)
137 {
138 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
139 cvmx_warn("CVMX_IOB_OUTB_REQ_PRI_CNT not supported on this chip\n");
140 return CVMX_ADD_IO_SEG(0x00011800F0000038ull);
141 }
142 #else
143 #define CVMX_IOB_OUTB_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000038ull))
144 #endif
145 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
146 #define CVMX_IOB_P2C_REQ_PRI_CNT CVMX_IOB_P2C_REQ_PRI_CNT_FUNC()
CVMX_IOB_P2C_REQ_PRI_CNT_FUNC(void)147 static inline uint64_t CVMX_IOB_P2C_REQ_PRI_CNT_FUNC(void)
148 {
149 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
150 cvmx_warn("CVMX_IOB_P2C_REQ_PRI_CNT not supported on this chip\n");
151 return CVMX_ADD_IO_SEG(0x00011800F0000018ull);
152 }
153 #else
154 #define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull))
155 #endif
156 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
157 #define CVMX_IOB_PKT_ERR CVMX_IOB_PKT_ERR_FUNC()
CVMX_IOB_PKT_ERR_FUNC(void)158 static inline uint64_t CVMX_IOB_PKT_ERR_FUNC(void)
159 {
160 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
161 cvmx_warn("CVMX_IOB_PKT_ERR not supported on this chip\n");
162 return CVMX_ADD_IO_SEG(0x00011800F0000068ull);
163 }
164 #else
165 #define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull))
166 #endif
167 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
168 #define CVMX_IOB_TO_CMB_CREDITS CVMX_IOB_TO_CMB_CREDITS_FUNC()
CVMX_IOB_TO_CMB_CREDITS_FUNC(void)169 static inline uint64_t CVMX_IOB_TO_CMB_CREDITS_FUNC(void)
170 {
171 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
172 cvmx_warn("CVMX_IOB_TO_CMB_CREDITS not supported on this chip\n");
173 return CVMX_ADD_IO_SEG(0x00011800F00000B0ull);
174 }
175 #else
176 #define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull))
177 #endif
178 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
179 #define CVMX_IOB_TO_NCB_DID_00_CREDITS CVMX_IOB_TO_NCB_DID_00_CREDITS_FUNC()
CVMX_IOB_TO_NCB_DID_00_CREDITS_FUNC(void)180 static inline uint64_t CVMX_IOB_TO_NCB_DID_00_CREDITS_FUNC(void)
181 {
182 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
183 cvmx_warn("CVMX_IOB_TO_NCB_DID_00_CREDITS not supported on this chip\n");
184 return CVMX_ADD_IO_SEG(0x00011800F0000800ull);
185 }
186 #else
187 #define CVMX_IOB_TO_NCB_DID_00_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000800ull))
188 #endif
189 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
190 #define CVMX_IOB_TO_NCB_DID_111_CREDITS CVMX_IOB_TO_NCB_DID_111_CREDITS_FUNC()
CVMX_IOB_TO_NCB_DID_111_CREDITS_FUNC(void)191 static inline uint64_t CVMX_IOB_TO_NCB_DID_111_CREDITS_FUNC(void)
192 {
193 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
194 cvmx_warn("CVMX_IOB_TO_NCB_DID_111_CREDITS not supported on this chip\n");
195 return CVMX_ADD_IO_SEG(0x00011800F0000B78ull);
196 }
197 #else
198 #define CVMX_IOB_TO_NCB_DID_111_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B78ull))
199 #endif
200 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
201 #define CVMX_IOB_TO_NCB_DID_223_CREDITS CVMX_IOB_TO_NCB_DID_223_CREDITS_FUNC()
CVMX_IOB_TO_NCB_DID_223_CREDITS_FUNC(void)202 static inline uint64_t CVMX_IOB_TO_NCB_DID_223_CREDITS_FUNC(void)
203 {
204 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
205 cvmx_warn("CVMX_IOB_TO_NCB_DID_223_CREDITS not supported on this chip\n");
206 return CVMX_ADD_IO_SEG(0x00011800F0000EF8ull);
207 }
208 #else
209 #define CVMX_IOB_TO_NCB_DID_223_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000EF8ull))
210 #endif
211 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
212 #define CVMX_IOB_TO_NCB_DID_24_CREDITS CVMX_IOB_TO_NCB_DID_24_CREDITS_FUNC()
CVMX_IOB_TO_NCB_DID_24_CREDITS_FUNC(void)213 static inline uint64_t CVMX_IOB_TO_NCB_DID_24_CREDITS_FUNC(void)
214 {
215 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
216 cvmx_warn("CVMX_IOB_TO_NCB_DID_24_CREDITS not supported on this chip\n");
217 return CVMX_ADD_IO_SEG(0x00011800F00008C0ull);
218 }
219 #else
220 #define CVMX_IOB_TO_NCB_DID_24_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00008C0ull))
221 #endif
222 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
223 #define CVMX_IOB_TO_NCB_DID_32_CREDITS CVMX_IOB_TO_NCB_DID_32_CREDITS_FUNC()
CVMX_IOB_TO_NCB_DID_32_CREDITS_FUNC(void)224 static inline uint64_t CVMX_IOB_TO_NCB_DID_32_CREDITS_FUNC(void)
225 {
226 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
227 cvmx_warn("CVMX_IOB_TO_NCB_DID_32_CREDITS not supported on this chip\n");
228 return CVMX_ADD_IO_SEG(0x00011800F0000900ull);
229 }
230 #else
231 #define CVMX_IOB_TO_NCB_DID_32_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000900ull))
232 #endif
233 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
234 #define CVMX_IOB_TO_NCB_DID_40_CREDITS CVMX_IOB_TO_NCB_DID_40_CREDITS_FUNC()
CVMX_IOB_TO_NCB_DID_40_CREDITS_FUNC(void)235 static inline uint64_t CVMX_IOB_TO_NCB_DID_40_CREDITS_FUNC(void)
236 {
237 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
238 cvmx_warn("CVMX_IOB_TO_NCB_DID_40_CREDITS not supported on this chip\n");
239 return CVMX_ADD_IO_SEG(0x00011800F0000940ull);
240 }
241 #else
242 #define CVMX_IOB_TO_NCB_DID_40_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000940ull))
243 #endif
244 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
245 #define CVMX_IOB_TO_NCB_DID_55_CREDITS CVMX_IOB_TO_NCB_DID_55_CREDITS_FUNC()
CVMX_IOB_TO_NCB_DID_55_CREDITS_FUNC(void)246 static inline uint64_t CVMX_IOB_TO_NCB_DID_55_CREDITS_FUNC(void)
247 {
248 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
249 cvmx_warn("CVMX_IOB_TO_NCB_DID_55_CREDITS not supported on this chip\n");
250 return CVMX_ADD_IO_SEG(0x00011800F00009B8ull);
251 }
252 #else
253 #define CVMX_IOB_TO_NCB_DID_55_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00009B8ull))
254 #endif
255 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
256 #define CVMX_IOB_TO_NCB_DID_64_CREDITS CVMX_IOB_TO_NCB_DID_64_CREDITS_FUNC()
CVMX_IOB_TO_NCB_DID_64_CREDITS_FUNC(void)257 static inline uint64_t CVMX_IOB_TO_NCB_DID_64_CREDITS_FUNC(void)
258 {
259 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
260 cvmx_warn("CVMX_IOB_TO_NCB_DID_64_CREDITS not supported on this chip\n");
261 return CVMX_ADD_IO_SEG(0x00011800F0000A00ull);
262 }
263 #else
264 #define CVMX_IOB_TO_NCB_DID_64_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A00ull))
265 #endif
266 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
267 #define CVMX_IOB_TO_NCB_DID_79_CREDITS CVMX_IOB_TO_NCB_DID_79_CREDITS_FUNC()
CVMX_IOB_TO_NCB_DID_79_CREDITS_FUNC(void)268 static inline uint64_t CVMX_IOB_TO_NCB_DID_79_CREDITS_FUNC(void)
269 {
270 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
271 cvmx_warn("CVMX_IOB_TO_NCB_DID_79_CREDITS not supported on this chip\n");
272 return CVMX_ADD_IO_SEG(0x00011800F0000A78ull);
273 }
274 #else
275 #define CVMX_IOB_TO_NCB_DID_79_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A78ull))
276 #endif
277 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
278 #define CVMX_IOB_TO_NCB_DID_96_CREDITS CVMX_IOB_TO_NCB_DID_96_CREDITS_FUNC()
CVMX_IOB_TO_NCB_DID_96_CREDITS_FUNC(void)279 static inline uint64_t CVMX_IOB_TO_NCB_DID_96_CREDITS_FUNC(void)
280 {
281 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
282 cvmx_warn("CVMX_IOB_TO_NCB_DID_96_CREDITS not supported on this chip\n");
283 return CVMX_ADD_IO_SEG(0x00011800F0000B00ull);
284 }
285 #else
286 #define CVMX_IOB_TO_NCB_DID_96_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B00ull))
287 #endif
288 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
289 #define CVMX_IOB_TO_NCB_DID_98_CREDITS CVMX_IOB_TO_NCB_DID_98_CREDITS_FUNC()
CVMX_IOB_TO_NCB_DID_98_CREDITS_FUNC(void)290 static inline uint64_t CVMX_IOB_TO_NCB_DID_98_CREDITS_FUNC(void)
291 {
292 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
293 cvmx_warn("CVMX_IOB_TO_NCB_DID_98_CREDITS not supported on this chip\n");
294 return CVMX_ADD_IO_SEG(0x00011800F0000B10ull);
295 }
296 #else
297 #define CVMX_IOB_TO_NCB_DID_98_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B10ull))
298 #endif
299
300 /**
301 * cvmx_iob_bist_status
302 *
303 * IOB_BIST_STATUS = BIST Status of IOB Memories
304 *
305 * The result of the BIST run on the IOB memories.
306 */
307 union cvmx_iob_bist_status {
308 uint64_t u64;
309 struct cvmx_iob_bist_status_s {
310 #ifdef __BIG_ENDIAN_BITFIELD
311 uint64_t reserved_2_63 : 62;
312 uint64_t ibd : 1; /**< ibd_bist_mem0_status */
313 uint64_t icd : 1; /**< icd_ncb_fifo_bist_status */
314 #else
315 uint64_t icd : 1;
316 uint64_t ibd : 1;
317 uint64_t reserved_2_63 : 62;
318 #endif
319 } s;
320 struct cvmx_iob_bist_status_cn30xx {
321 #ifdef __BIG_ENDIAN_BITFIELD
322 uint64_t reserved_18_63 : 46;
323 uint64_t icnrcb : 1; /**< Reserved */
324 uint64_t icr0 : 1; /**< Reserved */
325 uint64_t icr1 : 1; /**< Reserved */
326 uint64_t icnr1 : 1; /**< Reserved */
327 uint64_t icnr0 : 1; /**< icnr_reg_mem0_bist_status */
328 uint64_t ibdr0 : 1; /**< ibdr_bist_req_fifo0_status */
329 uint64_t ibdr1 : 1; /**< ibdr_bist_req_fifo1_status */
330 uint64_t ibr0 : 1; /**< ibr_bist_rsp_fifo0_status */
331 uint64_t ibr1 : 1; /**< ibr_bist_rsp_fifo1_status */
332 uint64_t icnrt : 1; /**< Reserved */
333 uint64_t ibrq0 : 1; /**< ibrq_bist_req_fifo0_status */
334 uint64_t ibrq1 : 1; /**< ibrq_bist_req_fifo1_status */
335 uint64_t icrn0 : 1; /**< icr_ncb_bist_mem0_status */
336 uint64_t icrn1 : 1; /**< icr_ncb_bist_mem1_status */
337 uint64_t icrp0 : 1; /**< icr_pko_bist_mem0_status */
338 uint64_t icrp1 : 1; /**< icr_pko_bist_mem1_status */
339 uint64_t ibd : 1; /**< ibd_bist_mem0_status */
340 uint64_t icd : 1; /**< icd_ncb_fifo_bist_status */
341 #else
342 uint64_t icd : 1;
343 uint64_t ibd : 1;
344 uint64_t icrp1 : 1;
345 uint64_t icrp0 : 1;
346 uint64_t icrn1 : 1;
347 uint64_t icrn0 : 1;
348 uint64_t ibrq1 : 1;
349 uint64_t ibrq0 : 1;
350 uint64_t icnrt : 1;
351 uint64_t ibr1 : 1;
352 uint64_t ibr0 : 1;
353 uint64_t ibdr1 : 1;
354 uint64_t ibdr0 : 1;
355 uint64_t icnr0 : 1;
356 uint64_t icnr1 : 1;
357 uint64_t icr1 : 1;
358 uint64_t icr0 : 1;
359 uint64_t icnrcb : 1;
360 uint64_t reserved_18_63 : 46;
361 #endif
362 } cn30xx;
363 struct cvmx_iob_bist_status_cn30xx cn31xx;
364 struct cvmx_iob_bist_status_cn30xx cn38xx;
365 struct cvmx_iob_bist_status_cn30xx cn38xxp2;
366 struct cvmx_iob_bist_status_cn30xx cn50xx;
367 struct cvmx_iob_bist_status_cn30xx cn52xx;
368 struct cvmx_iob_bist_status_cn30xx cn52xxp1;
369 struct cvmx_iob_bist_status_cn30xx cn56xx;
370 struct cvmx_iob_bist_status_cn30xx cn56xxp1;
371 struct cvmx_iob_bist_status_cn30xx cn58xx;
372 struct cvmx_iob_bist_status_cn30xx cn58xxp1;
373 struct cvmx_iob_bist_status_cn61xx {
374 #ifdef __BIG_ENDIAN_BITFIELD
375 uint64_t reserved_23_63 : 41;
376 uint64_t xmdfif : 1; /**< xmdfif_bist_status */
377 uint64_t xmcfif : 1; /**< xmcfif_bist_status */
378 uint64_t iorfif : 1; /**< iorfif_bist_status */
379 uint64_t rsdfif : 1; /**< rsdfif_bist_status */
380 uint64_t iocfif : 1; /**< iocfif_bist_status */
381 uint64_t icnrcb : 1; /**< icnr_cb_reg_fifo_bist_status */
382 uint64_t icr0 : 1; /**< icr_bist_req_fifo0_status */
383 uint64_t icr1 : 1; /**< icr_bist_req_fifo1_status */
384 uint64_t icnr1 : 1; /**< Reserved */
385 uint64_t icnr0 : 1; /**< icnr_reg_mem0_bist_status */
386 uint64_t ibdr0 : 1; /**< ibdr_bist_req_fifo0_status */
387 uint64_t ibdr1 : 1; /**< ibdr_bist_req_fifo1_status */
388 uint64_t ibr0 : 1; /**< ibr_bist_rsp_fifo0_status */
389 uint64_t ibr1 : 1; /**< ibr_bist_rsp_fifo1_status */
390 uint64_t icnrt : 1; /**< icnr_tag_cb_reg_fifo_bist_status */
391 uint64_t ibrq0 : 1; /**< ibrq_bist_req_fifo0_status */
392 uint64_t ibrq1 : 1; /**< ibrq_bist_req_fifo1_status */
393 uint64_t icrn0 : 1; /**< icr_ncb_bist_mem0_status */
394 uint64_t icrn1 : 1; /**< icr_ncb_bist_mem1_status */
395 uint64_t icrp0 : 1; /**< icr_pko_bist_mem0_status */
396 uint64_t icrp1 : 1; /**< icr_pko_bist_mem1_status */
397 uint64_t ibd : 1; /**< ibd_bist_mem0_status */
398 uint64_t icd : 1; /**< icd_ncb_fifo_bist_status */
399 #else
400 uint64_t icd : 1;
401 uint64_t ibd : 1;
402 uint64_t icrp1 : 1;
403 uint64_t icrp0 : 1;
404 uint64_t icrn1 : 1;
405 uint64_t icrn0 : 1;
406 uint64_t ibrq1 : 1;
407 uint64_t ibrq0 : 1;
408 uint64_t icnrt : 1;
409 uint64_t ibr1 : 1;
410 uint64_t ibr0 : 1;
411 uint64_t ibdr1 : 1;
412 uint64_t ibdr0 : 1;
413 uint64_t icnr0 : 1;
414 uint64_t icnr1 : 1;
415 uint64_t icr1 : 1;
416 uint64_t icr0 : 1;
417 uint64_t icnrcb : 1;
418 uint64_t iocfif : 1;
419 uint64_t rsdfif : 1;
420 uint64_t iorfif : 1;
421 uint64_t xmcfif : 1;
422 uint64_t xmdfif : 1;
423 uint64_t reserved_23_63 : 41;
424 #endif
425 } cn61xx;
426 struct cvmx_iob_bist_status_cn61xx cn63xx;
427 struct cvmx_iob_bist_status_cn61xx cn63xxp1;
428 struct cvmx_iob_bist_status_cn61xx cn66xx;
429 struct cvmx_iob_bist_status_cn68xx {
430 #ifdef __BIG_ENDIAN_BITFIELD
431 uint64_t reserved_18_63 : 46;
432 uint64_t xmdfif : 1; /**< xmdfif_bist_status */
433 uint64_t xmcfif : 1; /**< xmcfif_bist_status */
434 uint64_t iorfif : 1; /**< iorfif_bist_status */
435 uint64_t rsdfif : 1; /**< rsdfif_bist_status */
436 uint64_t iocfif : 1; /**< iocfif_bist_status */
437 uint64_t icnrcb : 1; /**< icnr_cb_reg_fifo_bist_status */
438 uint64_t icr0 : 1; /**< icr_bist_req_fifo0_status */
439 uint64_t icr1 : 1; /**< icr_bist_req_fifo1_status */
440 uint64_t icnr0 : 1; /**< icnr_reg_mem0_bist_status */
441 uint64_t ibr0 : 1; /**< ibr_bist_rsp_fifo0_status */
442 uint64_t ibr1 : 1; /**< ibr_bist_rsp_fifo1_status */
443 uint64_t icnrt : 1; /**< icnr_tag_cb_reg_fifo_bist_status */
444 uint64_t ibrq0 : 1; /**< ibrq_bist_req_fifo0_status */
445 uint64_t ibrq1 : 1; /**< ibrq_bist_req_fifo1_status */
446 uint64_t icrn0 : 1; /**< icr_ncb_bist_mem0_status */
447 uint64_t icrn1 : 1; /**< icr_ncb_bist_mem1_status */
448 uint64_t ibd : 1; /**< ibd_bist_mem0_status */
449 uint64_t icd : 1; /**< icd_ncb_fifo_bist_status */
450 #else
451 uint64_t icd : 1;
452 uint64_t ibd : 1;
453 uint64_t icrn1 : 1;
454 uint64_t icrn0 : 1;
455 uint64_t ibrq1 : 1;
456 uint64_t ibrq0 : 1;
457 uint64_t icnrt : 1;
458 uint64_t ibr1 : 1;
459 uint64_t ibr0 : 1;
460 uint64_t icnr0 : 1;
461 uint64_t icr1 : 1;
462 uint64_t icr0 : 1;
463 uint64_t icnrcb : 1;
464 uint64_t iocfif : 1;
465 uint64_t rsdfif : 1;
466 uint64_t iorfif : 1;
467 uint64_t xmcfif : 1;
468 uint64_t xmdfif : 1;
469 uint64_t reserved_18_63 : 46;
470 #endif
471 } cn68xx;
472 struct cvmx_iob_bist_status_cn68xx cn68xxp1;
473 struct cvmx_iob_bist_status_cn61xx cnf71xx;
474 };
475 typedef union cvmx_iob_bist_status cvmx_iob_bist_status_t;
476
477 /**
478 * cvmx_iob_ctl_status
479 *
480 * IOB Control Status = IOB Control and Status Register
481 *
482 * Provides control for IOB functions.
483 */
484 union cvmx_iob_ctl_status {
485 uint64_t u64;
486 struct cvmx_iob_ctl_status_s {
487 #ifdef __BIG_ENDIAN_BITFIELD
488 uint64_t reserved_11_63 : 53;
489 uint64_t fif_dly : 1; /**< Delay async FIFO counts to be used when clock ratio
490 is greater then 3:1. Writes should be followed by an
491 immediate read. */
492 uint64_t xmc_per : 4; /**< IBC XMC PUSH EARLY */
493 uint64_t reserved_5_5 : 1;
494 uint64_t outb_mat : 1; /**< Was a match on the outbound bus to the inb pattern
495 matchers. PASS2 FIELD. */
496 uint64_t inb_mat : 1; /**< Was a match on the inbound bus to the inb pattern
497 matchers. PASS2 FIELD. */
498 uint64_t pko_enb : 1; /**< Toggles the endian style of the FAU for the PKO.
499 '0' is for big-endian and '1' is for little-endian. */
500 uint64_t dwb_enb : 1; /**< Enables the DWB function of the IOB. */
501 uint64_t fau_end : 1; /**< Toggles the endian style of the FAU. '0' is for
502 big-endian and '1' is for little-endian. */
503 #else
504 uint64_t fau_end : 1;
505 uint64_t dwb_enb : 1;
506 uint64_t pko_enb : 1;
507 uint64_t inb_mat : 1;
508 uint64_t outb_mat : 1;
509 uint64_t reserved_5_5 : 1;
510 uint64_t xmc_per : 4;
511 uint64_t fif_dly : 1;
512 uint64_t reserved_11_63 : 53;
513 #endif
514 } s;
515 struct cvmx_iob_ctl_status_cn30xx {
516 #ifdef __BIG_ENDIAN_BITFIELD
517 uint64_t reserved_5_63 : 59;
518 uint64_t outb_mat : 1; /**< Was a match on the outbound bus to the inb pattern
519 matchers. */
520 uint64_t inb_mat : 1; /**< Was a match on the inbound bus to the inb pattern
521 matchers. */
522 uint64_t pko_enb : 1; /**< Toggles the endian style of the FAU for the PKO.
523 '0' is for big-endian and '1' is for little-endian. */
524 uint64_t dwb_enb : 1; /**< Enables the DWB function of the IOB. */
525 uint64_t fau_end : 1; /**< Toggles the endian style of the FAU. '0' is for
526 big-endian and '1' is for little-endian. */
527 #else
528 uint64_t fau_end : 1;
529 uint64_t dwb_enb : 1;
530 uint64_t pko_enb : 1;
531 uint64_t inb_mat : 1;
532 uint64_t outb_mat : 1;
533 uint64_t reserved_5_63 : 59;
534 #endif
535 } cn30xx;
536 struct cvmx_iob_ctl_status_cn30xx cn31xx;
537 struct cvmx_iob_ctl_status_cn30xx cn38xx;
538 struct cvmx_iob_ctl_status_cn30xx cn38xxp2;
539 struct cvmx_iob_ctl_status_cn30xx cn50xx;
540 struct cvmx_iob_ctl_status_cn52xx {
541 #ifdef __BIG_ENDIAN_BITFIELD
542 uint64_t reserved_6_63 : 58;
543 uint64_t rr_mode : 1; /**< When set to '1' will enable Round-Robin mode of next
544 transaction that could arbitrate for the XMB. */
545 uint64_t outb_mat : 1; /**< Was a match on the outbound bus to the inb pattern
546 matchers. PASS2 FIELD. */
547 uint64_t inb_mat : 1; /**< Was a match on the inbound bus to the inb pattern
548 matchers. PASS2 FIELD. */
549 uint64_t pko_enb : 1; /**< Toggles the endian style of the FAU for the PKO.
550 '0' is for big-endian and '1' is for little-endian. */
551 uint64_t dwb_enb : 1; /**< Enables the DWB function of the IOB. */
552 uint64_t fau_end : 1; /**< Toggles the endian style of the FAU. '0' is for
553 big-endian and '1' is for little-endian. */
554 #else
555 uint64_t fau_end : 1;
556 uint64_t dwb_enb : 1;
557 uint64_t pko_enb : 1;
558 uint64_t inb_mat : 1;
559 uint64_t outb_mat : 1;
560 uint64_t rr_mode : 1;
561 uint64_t reserved_6_63 : 58;
562 #endif
563 } cn52xx;
564 struct cvmx_iob_ctl_status_cn30xx cn52xxp1;
565 struct cvmx_iob_ctl_status_cn30xx cn56xx;
566 struct cvmx_iob_ctl_status_cn30xx cn56xxp1;
567 struct cvmx_iob_ctl_status_cn30xx cn58xx;
568 struct cvmx_iob_ctl_status_cn30xx cn58xxp1;
569 struct cvmx_iob_ctl_status_cn61xx {
570 #ifdef __BIG_ENDIAN_BITFIELD
571 uint64_t reserved_11_63 : 53;
572 uint64_t fif_dly : 1; /**< Delay async FIFO counts to be used when clock ratio
573 is greater then 3:1. Writes should be followed by an
574 immediate read. */
575 uint64_t xmc_per : 4; /**< IBC XMC PUSH EARLY */
576 uint64_t rr_mode : 1; /**< When set to '1' will enable Round-Robin mode of next
577 transaction that could arbitrate for the XMB. */
578 uint64_t outb_mat : 1; /**< Was a match on the outbound bus to the inb pattern
579 matchers. PASS2 FIELD. */
580 uint64_t inb_mat : 1; /**< Was a match on the inbound bus to the inb pattern
581 matchers. PASS2 FIELD. */
582 uint64_t pko_enb : 1; /**< Toggles the endian style of the FAU for the PKO.
583 '0' is for big-endian and '1' is for little-endian. */
584 uint64_t dwb_enb : 1; /**< Enables the DWB function of the IOB. */
585 uint64_t fau_end : 1; /**< Toggles the endian style of the FAU. '0' is for
586 big-endian and '1' is for little-endian. */
587 #else
588 uint64_t fau_end : 1;
589 uint64_t dwb_enb : 1;
590 uint64_t pko_enb : 1;
591 uint64_t inb_mat : 1;
592 uint64_t outb_mat : 1;
593 uint64_t rr_mode : 1;
594 uint64_t xmc_per : 4;
595 uint64_t fif_dly : 1;
596 uint64_t reserved_11_63 : 53;
597 #endif
598 } cn61xx;
599 struct cvmx_iob_ctl_status_cn63xx {
600 #ifdef __BIG_ENDIAN_BITFIELD
601 uint64_t reserved_10_63 : 54;
602 uint64_t xmc_per : 4; /**< IBC XMC PUSH EARLY */
603 uint64_t rr_mode : 1; /**< When set to '1' will enable Round-Robin mode of next
604 transaction that could arbitrate for the XMB. */
605 uint64_t outb_mat : 1; /**< Was a match on the outbound bus to the inb pattern
606 matchers. PASS2 FIELD. */
607 uint64_t inb_mat : 1; /**< Was a match on the inbound bus to the inb pattern
608 matchers. PASS2 FIELD. */
609 uint64_t pko_enb : 1; /**< Toggles the endian style of the FAU for the PKO.
610 '0' is for big-endian and '1' is for little-endian. */
611 uint64_t dwb_enb : 1; /**< Enables the DWB function of the IOB. */
612 uint64_t fau_end : 1; /**< Toggles the endian style of the FAU. '0' is for
613 big-endian and '1' is for little-endian. */
614 #else
615 uint64_t fau_end : 1;
616 uint64_t dwb_enb : 1;
617 uint64_t pko_enb : 1;
618 uint64_t inb_mat : 1;
619 uint64_t outb_mat : 1;
620 uint64_t rr_mode : 1;
621 uint64_t xmc_per : 4;
622 uint64_t reserved_10_63 : 54;
623 #endif
624 } cn63xx;
625 struct cvmx_iob_ctl_status_cn63xx cn63xxp1;
626 struct cvmx_iob_ctl_status_cn61xx cn66xx;
627 struct cvmx_iob_ctl_status_cn68xx {
628 #ifdef __BIG_ENDIAN_BITFIELD
629 uint64_t reserved_11_63 : 53;
630 uint64_t fif_dly : 1; /**< Delay async FIFO counts to be used when clock ratio
631 is greater then 3:1. Writes should be followed by an
632 immediate read. */
633 uint64_t xmc_per : 4; /**< IBC XMC PUSH EARLY */
634 uint64_t rsvr5 : 1; /**< Reserved */
635 uint64_t outb_mat : 1; /**< Was a match on the outbound bus to the inb pattern
636 matchers. */
637 uint64_t inb_mat : 1; /**< Was a match on the inbound bus to the inb pattern
638 matchers. */
639 uint64_t pko_enb : 1; /**< Toggles the endian style of the FAU for the PKO.
640 '0' is for big-endian and '1' is for little-endian. */
641 uint64_t dwb_enb : 1; /**< Enables the DWB function of the IOB. */
642 uint64_t fau_end : 1; /**< Toggles the endian style of the FAU. '0' is for
643 big-endian and '1' is for little-endian. */
644 #else
645 uint64_t fau_end : 1;
646 uint64_t dwb_enb : 1;
647 uint64_t pko_enb : 1;
648 uint64_t inb_mat : 1;
649 uint64_t outb_mat : 1;
650 uint64_t rsvr5 : 1;
651 uint64_t xmc_per : 4;
652 uint64_t fif_dly : 1;
653 uint64_t reserved_11_63 : 53;
654 #endif
655 } cn68xx;
656 struct cvmx_iob_ctl_status_cn68xx cn68xxp1;
657 struct cvmx_iob_ctl_status_cn61xx cnf71xx;
658 };
659 typedef union cvmx_iob_ctl_status cvmx_iob_ctl_status_t;
660
661 /**
662 * cvmx_iob_dwb_pri_cnt
663 *
664 * DWB To CMB Priority Counter = Don't Write Back to CMB Priority Counter Enable and Timer Value
665 *
666 * Enables and supplies the timeout count for raising the priority of Don't Write Back request to the L2C.
667 */
668 union cvmx_iob_dwb_pri_cnt {
669 uint64_t u64;
670 struct cvmx_iob_dwb_pri_cnt_s {
671 #ifdef __BIG_ENDIAN_BITFIELD
672 uint64_t reserved_16_63 : 48;
673 uint64_t cnt_enb : 1; /**< Enables the raising of CMB access priority
674 when CNT_VAL is reached. */
675 uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising
676 the priority for access to CMB. */
677 #else
678 uint64_t cnt_val : 15;
679 uint64_t cnt_enb : 1;
680 uint64_t reserved_16_63 : 48;
681 #endif
682 } s;
683 struct cvmx_iob_dwb_pri_cnt_s cn38xx;
684 struct cvmx_iob_dwb_pri_cnt_s cn38xxp2;
685 struct cvmx_iob_dwb_pri_cnt_s cn52xx;
686 struct cvmx_iob_dwb_pri_cnt_s cn52xxp1;
687 struct cvmx_iob_dwb_pri_cnt_s cn56xx;
688 struct cvmx_iob_dwb_pri_cnt_s cn56xxp1;
689 struct cvmx_iob_dwb_pri_cnt_s cn58xx;
690 struct cvmx_iob_dwb_pri_cnt_s cn58xxp1;
691 struct cvmx_iob_dwb_pri_cnt_s cn61xx;
692 struct cvmx_iob_dwb_pri_cnt_s cn63xx;
693 struct cvmx_iob_dwb_pri_cnt_s cn63xxp1;
694 struct cvmx_iob_dwb_pri_cnt_s cn66xx;
695 struct cvmx_iob_dwb_pri_cnt_s cnf71xx;
696 };
697 typedef union cvmx_iob_dwb_pri_cnt cvmx_iob_dwb_pri_cnt_t;
698
699 /**
700 * cvmx_iob_fau_timeout
701 *
702 * FAU Timeout = Fetch and Add Unit Tag-Switch Timeout
703 *
704 * How many clokc ticks the FAU unit will wait for a tag-switch before timeing out.
705 * for Queue 0.
706 */
707 union cvmx_iob_fau_timeout {
708 uint64_t u64;
709 struct cvmx_iob_fau_timeout_s {
710 #ifdef __BIG_ENDIAN_BITFIELD
711 uint64_t reserved_13_63 : 51;
712 uint64_t tout_enb : 1; /**< The enable for the FAU timeout feature.
713 '1' will enable the timeout, '0' will disable. */
714 uint64_t tout_val : 12; /**< When a tag request arrives from the PP a timer is
715 started associate with that PP. The timer which
716 increments every 256 eclks is compared to TOUT_VAL.
717 When the two are equal the IOB will flag the tag
718 request to complete as a time-out tag operation.
719 The 256 count timer used to increment the PP
720 associated timer is always running so the first
721 increment of the PP associated timer may occur any
722 where within the first 256 eclks. Note that '0'
723 is an illegal value. */
724 #else
725 uint64_t tout_val : 12;
726 uint64_t tout_enb : 1;
727 uint64_t reserved_13_63 : 51;
728 #endif
729 } s;
730 struct cvmx_iob_fau_timeout_s cn30xx;
731 struct cvmx_iob_fau_timeout_s cn31xx;
732 struct cvmx_iob_fau_timeout_s cn38xx;
733 struct cvmx_iob_fau_timeout_s cn38xxp2;
734 struct cvmx_iob_fau_timeout_s cn50xx;
735 struct cvmx_iob_fau_timeout_s cn52xx;
736 struct cvmx_iob_fau_timeout_s cn52xxp1;
737 struct cvmx_iob_fau_timeout_s cn56xx;
738 struct cvmx_iob_fau_timeout_s cn56xxp1;
739 struct cvmx_iob_fau_timeout_s cn58xx;
740 struct cvmx_iob_fau_timeout_s cn58xxp1;
741 struct cvmx_iob_fau_timeout_s cn61xx;
742 struct cvmx_iob_fau_timeout_s cn63xx;
743 struct cvmx_iob_fau_timeout_s cn63xxp1;
744 struct cvmx_iob_fau_timeout_s cn66xx;
745 struct cvmx_iob_fau_timeout_s cn68xx;
746 struct cvmx_iob_fau_timeout_s cn68xxp1;
747 struct cvmx_iob_fau_timeout_s cnf71xx;
748 };
749 typedef union cvmx_iob_fau_timeout cvmx_iob_fau_timeout_t;
750
751 /**
752 * cvmx_iob_i2c_pri_cnt
753 *
754 * IPD To CMB Store Priority Counter = IPD to CMB Store Priority Counter Enable and Timer Value
755 *
756 * Enables and supplies the timeout count for raising the priority of IPD Store access to the CMB.
757 */
758 union cvmx_iob_i2c_pri_cnt {
759 uint64_t u64;
760 struct cvmx_iob_i2c_pri_cnt_s {
761 #ifdef __BIG_ENDIAN_BITFIELD
762 uint64_t reserved_16_63 : 48;
763 uint64_t cnt_enb : 1; /**< Enables the raising of CMB access priority
764 when CNT_VAL is reached. */
765 uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising
766 the priority for access to CMB. */
767 #else
768 uint64_t cnt_val : 15;
769 uint64_t cnt_enb : 1;
770 uint64_t reserved_16_63 : 48;
771 #endif
772 } s;
773 struct cvmx_iob_i2c_pri_cnt_s cn38xx;
774 struct cvmx_iob_i2c_pri_cnt_s cn38xxp2;
775 struct cvmx_iob_i2c_pri_cnt_s cn52xx;
776 struct cvmx_iob_i2c_pri_cnt_s cn52xxp1;
777 struct cvmx_iob_i2c_pri_cnt_s cn56xx;
778 struct cvmx_iob_i2c_pri_cnt_s cn56xxp1;
779 struct cvmx_iob_i2c_pri_cnt_s cn58xx;
780 struct cvmx_iob_i2c_pri_cnt_s cn58xxp1;
781 struct cvmx_iob_i2c_pri_cnt_s cn61xx;
782 struct cvmx_iob_i2c_pri_cnt_s cn63xx;
783 struct cvmx_iob_i2c_pri_cnt_s cn63xxp1;
784 struct cvmx_iob_i2c_pri_cnt_s cn66xx;
785 struct cvmx_iob_i2c_pri_cnt_s cnf71xx;
786 };
787 typedef union cvmx_iob_i2c_pri_cnt cvmx_iob_i2c_pri_cnt_t;
788
789 /**
790 * cvmx_iob_inb_control_match
791 *
792 * IOB_INB_CONTROL_MATCH = IOB Inbound Control Match
793 *
794 * Match pattern for the inbound control to set the INB_MATCH_BIT. PASS-2 Register
795 */
796 union cvmx_iob_inb_control_match {
797 uint64_t u64;
798 struct cvmx_iob_inb_control_match_s {
799 #ifdef __BIG_ENDIAN_BITFIELD
800 uint64_t reserved_29_63 : 35;
801 uint64_t mask : 8; /**< Pattern to match on the inbound NCB. */
802 uint64_t opc : 4; /**< Pattern to match on the inbound NCB. */
803 uint64_t dst : 9; /**< Pattern to match on the inbound NCB. */
804 uint64_t src : 8; /**< Pattern to match on the inbound NCB. */
805 #else
806 uint64_t src : 8;
807 uint64_t dst : 9;
808 uint64_t opc : 4;
809 uint64_t mask : 8;
810 uint64_t reserved_29_63 : 35;
811 #endif
812 } s;
813 struct cvmx_iob_inb_control_match_s cn30xx;
814 struct cvmx_iob_inb_control_match_s cn31xx;
815 struct cvmx_iob_inb_control_match_s cn38xx;
816 struct cvmx_iob_inb_control_match_s cn38xxp2;
817 struct cvmx_iob_inb_control_match_s cn50xx;
818 struct cvmx_iob_inb_control_match_s cn52xx;
819 struct cvmx_iob_inb_control_match_s cn52xxp1;
820 struct cvmx_iob_inb_control_match_s cn56xx;
821 struct cvmx_iob_inb_control_match_s cn56xxp1;
822 struct cvmx_iob_inb_control_match_s cn58xx;
823 struct cvmx_iob_inb_control_match_s cn58xxp1;
824 struct cvmx_iob_inb_control_match_s cn61xx;
825 struct cvmx_iob_inb_control_match_s cn63xx;
826 struct cvmx_iob_inb_control_match_s cn63xxp1;
827 struct cvmx_iob_inb_control_match_s cn66xx;
828 struct cvmx_iob_inb_control_match_s cn68xx;
829 struct cvmx_iob_inb_control_match_s cn68xxp1;
830 struct cvmx_iob_inb_control_match_s cnf71xx;
831 };
832 typedef union cvmx_iob_inb_control_match cvmx_iob_inb_control_match_t;
833
834 /**
835 * cvmx_iob_inb_control_match_enb
836 *
837 * IOB_INB_CONTROL_MATCH_ENB = IOB Inbound Control Match Enable
838 *
839 * Enables the match of the corresponding bit in the IOB_INB_CONTROL_MATCH reister. PASS-2 Register
840 */
841 union cvmx_iob_inb_control_match_enb {
842 uint64_t u64;
843 struct cvmx_iob_inb_control_match_enb_s {
844 #ifdef __BIG_ENDIAN_BITFIELD
845 uint64_t reserved_29_63 : 35;
846 uint64_t mask : 8; /**< Pattern to match on the inbound NCB. */
847 uint64_t opc : 4; /**< Pattern to match on the inbound NCB. */
848 uint64_t dst : 9; /**< Pattern to match on the inbound NCB. */
849 uint64_t src : 8; /**< Pattern to match on the inbound NCB. */
850 #else
851 uint64_t src : 8;
852 uint64_t dst : 9;
853 uint64_t opc : 4;
854 uint64_t mask : 8;
855 uint64_t reserved_29_63 : 35;
856 #endif
857 } s;
858 struct cvmx_iob_inb_control_match_enb_s cn30xx;
859 struct cvmx_iob_inb_control_match_enb_s cn31xx;
860 struct cvmx_iob_inb_control_match_enb_s cn38xx;
861 struct cvmx_iob_inb_control_match_enb_s cn38xxp2;
862 struct cvmx_iob_inb_control_match_enb_s cn50xx;
863 struct cvmx_iob_inb_control_match_enb_s cn52xx;
864 struct cvmx_iob_inb_control_match_enb_s cn52xxp1;
865 struct cvmx_iob_inb_control_match_enb_s cn56xx;
866 struct cvmx_iob_inb_control_match_enb_s cn56xxp1;
867 struct cvmx_iob_inb_control_match_enb_s cn58xx;
868 struct cvmx_iob_inb_control_match_enb_s cn58xxp1;
869 struct cvmx_iob_inb_control_match_enb_s cn61xx;
870 struct cvmx_iob_inb_control_match_enb_s cn63xx;
871 struct cvmx_iob_inb_control_match_enb_s cn63xxp1;
872 struct cvmx_iob_inb_control_match_enb_s cn66xx;
873 struct cvmx_iob_inb_control_match_enb_s cn68xx;
874 struct cvmx_iob_inb_control_match_enb_s cn68xxp1;
875 struct cvmx_iob_inb_control_match_enb_s cnf71xx;
876 };
877 typedef union cvmx_iob_inb_control_match_enb cvmx_iob_inb_control_match_enb_t;
878
879 /**
880 * cvmx_iob_inb_data_match
881 *
882 * IOB_INB_DATA_MATCH = IOB Inbound Data Match
883 *
884 * Match pattern for the inbound data to set the INB_MATCH_BIT. PASS-2 Register
885 */
886 union cvmx_iob_inb_data_match {
887 uint64_t u64;
888 struct cvmx_iob_inb_data_match_s {
889 #ifdef __BIG_ENDIAN_BITFIELD
890 uint64_t data : 64; /**< Pattern to match on the inbound NCB. */
891 #else
892 uint64_t data : 64;
893 #endif
894 } s;
895 struct cvmx_iob_inb_data_match_s cn30xx;
896 struct cvmx_iob_inb_data_match_s cn31xx;
897 struct cvmx_iob_inb_data_match_s cn38xx;
898 struct cvmx_iob_inb_data_match_s cn38xxp2;
899 struct cvmx_iob_inb_data_match_s cn50xx;
900 struct cvmx_iob_inb_data_match_s cn52xx;
901 struct cvmx_iob_inb_data_match_s cn52xxp1;
902 struct cvmx_iob_inb_data_match_s cn56xx;
903 struct cvmx_iob_inb_data_match_s cn56xxp1;
904 struct cvmx_iob_inb_data_match_s cn58xx;
905 struct cvmx_iob_inb_data_match_s cn58xxp1;
906 struct cvmx_iob_inb_data_match_s cn61xx;
907 struct cvmx_iob_inb_data_match_s cn63xx;
908 struct cvmx_iob_inb_data_match_s cn63xxp1;
909 struct cvmx_iob_inb_data_match_s cn66xx;
910 struct cvmx_iob_inb_data_match_s cn68xx;
911 struct cvmx_iob_inb_data_match_s cn68xxp1;
912 struct cvmx_iob_inb_data_match_s cnf71xx;
913 };
914 typedef union cvmx_iob_inb_data_match cvmx_iob_inb_data_match_t;
915
916 /**
917 * cvmx_iob_inb_data_match_enb
918 *
919 * IOB_INB_DATA_MATCH_ENB = IOB Inbound Data Match Enable
920 *
921 * Enables the match of the corresponding bit in the IOB_INB_DATA_MATCH reister. PASS-2 Register
922 */
923 union cvmx_iob_inb_data_match_enb {
924 uint64_t u64;
925 struct cvmx_iob_inb_data_match_enb_s {
926 #ifdef __BIG_ENDIAN_BITFIELD
927 uint64_t data : 64; /**< Bit to enable match of. */
928 #else
929 uint64_t data : 64;
930 #endif
931 } s;
932 struct cvmx_iob_inb_data_match_enb_s cn30xx;
933 struct cvmx_iob_inb_data_match_enb_s cn31xx;
934 struct cvmx_iob_inb_data_match_enb_s cn38xx;
935 struct cvmx_iob_inb_data_match_enb_s cn38xxp2;
936 struct cvmx_iob_inb_data_match_enb_s cn50xx;
937 struct cvmx_iob_inb_data_match_enb_s cn52xx;
938 struct cvmx_iob_inb_data_match_enb_s cn52xxp1;
939 struct cvmx_iob_inb_data_match_enb_s cn56xx;
940 struct cvmx_iob_inb_data_match_enb_s cn56xxp1;
941 struct cvmx_iob_inb_data_match_enb_s cn58xx;
942 struct cvmx_iob_inb_data_match_enb_s cn58xxp1;
943 struct cvmx_iob_inb_data_match_enb_s cn61xx;
944 struct cvmx_iob_inb_data_match_enb_s cn63xx;
945 struct cvmx_iob_inb_data_match_enb_s cn63xxp1;
946 struct cvmx_iob_inb_data_match_enb_s cn66xx;
947 struct cvmx_iob_inb_data_match_enb_s cn68xx;
948 struct cvmx_iob_inb_data_match_enb_s cn68xxp1;
949 struct cvmx_iob_inb_data_match_enb_s cnf71xx;
950 };
951 typedef union cvmx_iob_inb_data_match_enb cvmx_iob_inb_data_match_enb_t;
952
953 /**
954 * cvmx_iob_int_enb
955 *
956 * IOB_INT_ENB = IOB's Interrupt Enable
957 *
958 * The IOB's interrupt enable register. This is a PASS-2 register.
959 */
960 union cvmx_iob_int_enb {
961 uint64_t u64;
962 struct cvmx_iob_int_enb_s {
963 #ifdef __BIG_ENDIAN_BITFIELD
964 uint64_t reserved_6_63 : 58;
965 uint64_t p_dat : 1; /**< When set (1) and bit 5 of the IOB_INT_SUM
966 register is asserted the IOB will assert an
967 interrupt. */
968 uint64_t np_dat : 1; /**< When set (1) and bit 4 of the IOB_INT_SUM
969 register is asserted the IOB will assert an
970 interrupt. */
971 uint64_t p_eop : 1; /**< When set (1) and bit 3 of the IOB_INT_SUM
972 register is asserted the IOB will assert an
973 interrupt. */
974 uint64_t p_sop : 1; /**< When set (1) and bit 2 of the IOB_INT_SUM
975 register is asserted the IOB will assert an
976 interrupt. */
977 uint64_t np_eop : 1; /**< When set (1) and bit 1 of the IOB_INT_SUM
978 register is asserted the IOB will assert an
979 interrupt. */
980 uint64_t np_sop : 1; /**< When set (1) and bit 0 of the IOB_INT_SUM
981 register is asserted the IOB will assert an
982 interrupt. */
983 #else
984 uint64_t np_sop : 1;
985 uint64_t np_eop : 1;
986 uint64_t p_sop : 1;
987 uint64_t p_eop : 1;
988 uint64_t np_dat : 1;
989 uint64_t p_dat : 1;
990 uint64_t reserved_6_63 : 58;
991 #endif
992 } s;
993 struct cvmx_iob_int_enb_cn30xx {
994 #ifdef __BIG_ENDIAN_BITFIELD
995 uint64_t reserved_4_63 : 60;
996 uint64_t p_eop : 1; /**< When set (1) and bit 3 of the IOB_INT_SUM
997 register is asserted the IOB will assert an
998 interrupt. */
999 uint64_t p_sop : 1; /**< When set (1) and bit 2 of the IOB_INT_SUM
1000 register is asserted the IOB will assert an
1001 interrupt. */
1002 uint64_t np_eop : 1; /**< When set (1) and bit 1 of the IOB_INT_SUM
1003 register is asserted the IOB will assert an
1004 interrupt. */
1005 uint64_t np_sop : 1; /**< When set (1) and bit 0 of the IOB_INT_SUM
1006 register is asserted the IOB will assert an
1007 interrupt. */
1008 #else
1009 uint64_t np_sop : 1;
1010 uint64_t np_eop : 1;
1011 uint64_t p_sop : 1;
1012 uint64_t p_eop : 1;
1013 uint64_t reserved_4_63 : 60;
1014 #endif
1015 } cn30xx;
1016 struct cvmx_iob_int_enb_cn30xx cn31xx;
1017 struct cvmx_iob_int_enb_cn30xx cn38xx;
1018 struct cvmx_iob_int_enb_cn30xx cn38xxp2;
1019 struct cvmx_iob_int_enb_s cn50xx;
1020 struct cvmx_iob_int_enb_s cn52xx;
1021 struct cvmx_iob_int_enb_s cn52xxp1;
1022 struct cvmx_iob_int_enb_s cn56xx;
1023 struct cvmx_iob_int_enb_s cn56xxp1;
1024 struct cvmx_iob_int_enb_s cn58xx;
1025 struct cvmx_iob_int_enb_s cn58xxp1;
1026 struct cvmx_iob_int_enb_s cn61xx;
1027 struct cvmx_iob_int_enb_s cn63xx;
1028 struct cvmx_iob_int_enb_s cn63xxp1;
1029 struct cvmx_iob_int_enb_s cn66xx;
1030 struct cvmx_iob_int_enb_cn68xx {
1031 #ifdef __BIG_ENDIAN_BITFIELD
1032 uint64_t reserved_0_63 : 64;
1033 #else
1034 uint64_t reserved_0_63 : 64;
1035 #endif
1036 } cn68xx;
1037 struct cvmx_iob_int_enb_cn68xx cn68xxp1;
1038 struct cvmx_iob_int_enb_s cnf71xx;
1039 };
1040 typedef union cvmx_iob_int_enb cvmx_iob_int_enb_t;
1041
1042 /**
1043 * cvmx_iob_int_sum
1044 *
1045 * IOB_INT_SUM = IOB's Interrupt Summary Register
1046 *
1047 * Contains the diffrent interrupt summary bits of the IOB. This is a PASS-2 register.
1048 */
1049 union cvmx_iob_int_sum {
1050 uint64_t u64;
1051 struct cvmx_iob_int_sum_s {
1052 #ifdef __BIG_ENDIAN_BITFIELD
1053 uint64_t reserved_6_63 : 58;
1054 uint64_t p_dat : 1; /**< Set when a data arrives before a SOP for the same
1055 port for a passthrough packet.
1056 The first detected error associated with bits [5:0]
1057 of this register will only be set here. A new bit
1058 can be set when the previous reported bit is cleared. */
1059 uint64_t np_dat : 1; /**< Set when a data arrives before a SOP for the same
1060 port for a non-passthrough packet.
1061 The first detected error associated with bits [5:0]
1062 of this register will only be set here. A new bit
1063 can be set when the previous reported bit is cleared. */
1064 uint64_t p_eop : 1; /**< Set when a EOP is followed by an EOP for the same
1065 port for a passthrough packet.
1066 The first detected error associated with bits [5:0]
1067 of this register will only be set here. A new bit
1068 can be set when the previous reported bit is cleared. */
1069 uint64_t p_sop : 1; /**< Set when a SOP is followed by an SOP for the same
1070 port for a passthrough packet.
1071 The first detected error associated with bits [5:0]
1072 of this register will only be set here. A new bit
1073 can be set when the previous reported bit is cleared. */
1074 uint64_t np_eop : 1; /**< Set when a EOP is followed by an EOP for the same
1075 port for a non-passthrough packet.
1076 The first detected error associated with bits [5:0]
1077 of this register will only be set here. A new bit
1078 can be set when the previous reported bit is cleared. */
1079 uint64_t np_sop : 1; /**< Set when a SOP is followed by an SOP for the same
1080 port for a non-passthrough packet.
1081 The first detected error associated with bits [5:0]
1082 of this register will only be set here. A new bit
1083 can be set when the previous reported bit is cleared. */
1084 #else
1085 uint64_t np_sop : 1;
1086 uint64_t np_eop : 1;
1087 uint64_t p_sop : 1;
1088 uint64_t p_eop : 1;
1089 uint64_t np_dat : 1;
1090 uint64_t p_dat : 1;
1091 uint64_t reserved_6_63 : 58;
1092 #endif
1093 } s;
1094 struct cvmx_iob_int_sum_cn30xx {
1095 #ifdef __BIG_ENDIAN_BITFIELD
1096 uint64_t reserved_4_63 : 60;
1097 uint64_t p_eop : 1; /**< Set when a EOP is followed by an EOP for the same
1098 port for a passthrough packet.
1099 The first detected error associated with bits [3:0]
1100 of this register will only be set here. A new bit
1101 can be set when the previous reported bit is cleared. */
1102 uint64_t p_sop : 1; /**< Set when a SOP is followed by an SOP for the same
1103 port for a passthrough packet.
1104 The first detected error associated with bits [3:0]
1105 of this register will only be set here. A new bit
1106 can be set when the previous reported bit is cleared. */
1107 uint64_t np_eop : 1; /**< Set when a EOP is followed by an EOP for the same
1108 port for a non-passthrough packet.
1109 The first detected error associated with bits [3:0]
1110 of this register will only be set here. A new bit
1111 can be set when the previous reported bit is cleared. */
1112 uint64_t np_sop : 1; /**< Set when a SOP is followed by an SOP for the same
1113 port for a non-passthrough packet.
1114 The first detected error associated with bits [3:0]
1115 of this register will only be set here. A new bit
1116 can be set when the previous reported bit is cleared. */
1117 #else
1118 uint64_t np_sop : 1;
1119 uint64_t np_eop : 1;
1120 uint64_t p_sop : 1;
1121 uint64_t p_eop : 1;
1122 uint64_t reserved_4_63 : 60;
1123 #endif
1124 } cn30xx;
1125 struct cvmx_iob_int_sum_cn30xx cn31xx;
1126 struct cvmx_iob_int_sum_cn30xx cn38xx;
1127 struct cvmx_iob_int_sum_cn30xx cn38xxp2;
1128 struct cvmx_iob_int_sum_s cn50xx;
1129 struct cvmx_iob_int_sum_s cn52xx;
1130 struct cvmx_iob_int_sum_s cn52xxp1;
1131 struct cvmx_iob_int_sum_s cn56xx;
1132 struct cvmx_iob_int_sum_s cn56xxp1;
1133 struct cvmx_iob_int_sum_s cn58xx;
1134 struct cvmx_iob_int_sum_s cn58xxp1;
1135 struct cvmx_iob_int_sum_s cn61xx;
1136 struct cvmx_iob_int_sum_s cn63xx;
1137 struct cvmx_iob_int_sum_s cn63xxp1;
1138 struct cvmx_iob_int_sum_s cn66xx;
1139 struct cvmx_iob_int_sum_cn68xx {
1140 #ifdef __BIG_ENDIAN_BITFIELD
1141 uint64_t reserved_0_63 : 64;
1142 #else
1143 uint64_t reserved_0_63 : 64;
1144 #endif
1145 } cn68xx;
1146 struct cvmx_iob_int_sum_cn68xx cn68xxp1;
1147 struct cvmx_iob_int_sum_s cnf71xx;
1148 };
1149 typedef union cvmx_iob_int_sum cvmx_iob_int_sum_t;
1150
1151 /**
1152 * cvmx_iob_n2c_l2c_pri_cnt
1153 *
1154 * NCB To CMB L2C Priority Counter = NCB to CMB L2C Priority Counter Enable and Timer Value
1155 *
1156 * Enables and supplies the timeout count for raising the priority of NCB Store/Load access to the CMB.
1157 */
1158 union cvmx_iob_n2c_l2c_pri_cnt {
1159 uint64_t u64;
1160 struct cvmx_iob_n2c_l2c_pri_cnt_s {
1161 #ifdef __BIG_ENDIAN_BITFIELD
1162 uint64_t reserved_16_63 : 48;
1163 uint64_t cnt_enb : 1; /**< Enables the raising of CMB access priority
1164 when CNT_VAL is reached. */
1165 uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising
1166 the priority for access to CMB. */
1167 #else
1168 uint64_t cnt_val : 15;
1169 uint64_t cnt_enb : 1;
1170 uint64_t reserved_16_63 : 48;
1171 #endif
1172 } s;
1173 struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xx;
1174 struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xxp2;
1175 struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xx;
1176 struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xxp1;
1177 struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xx;
1178 struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1;
1179 struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx;
1180 struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1;
1181 struct cvmx_iob_n2c_l2c_pri_cnt_s cn61xx;
1182 struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xx;
1183 struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xxp1;
1184 struct cvmx_iob_n2c_l2c_pri_cnt_s cn66xx;
1185 struct cvmx_iob_n2c_l2c_pri_cnt_s cnf71xx;
1186 };
1187 typedef union cvmx_iob_n2c_l2c_pri_cnt cvmx_iob_n2c_l2c_pri_cnt_t;
1188
1189 /**
1190 * cvmx_iob_n2c_rsp_pri_cnt
1191 *
1192 * NCB To CMB Response Priority Counter = NCB to CMB Response Priority Counter Enable and Timer Value
1193 *
1194 * Enables and supplies the timeout count for raising the priority of NCB Responses access to the CMB.
1195 */
1196 union cvmx_iob_n2c_rsp_pri_cnt {
1197 uint64_t u64;
1198 struct cvmx_iob_n2c_rsp_pri_cnt_s {
1199 #ifdef __BIG_ENDIAN_BITFIELD
1200 uint64_t reserved_16_63 : 48;
1201 uint64_t cnt_enb : 1; /**< Enables the raising of CMB access priority
1202 when CNT_VAL is reached. */
1203 uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising
1204 the priority for access to CMB. */
1205 #else
1206 uint64_t cnt_val : 15;
1207 uint64_t cnt_enb : 1;
1208 uint64_t reserved_16_63 : 48;
1209 #endif
1210 } s;
1211 struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xx;
1212 struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xxp2;
1213 struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xx;
1214 struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xxp1;
1215 struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xx;
1216 struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1;
1217 struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx;
1218 struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1;
1219 struct cvmx_iob_n2c_rsp_pri_cnt_s cn61xx;
1220 struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xx;
1221 struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xxp1;
1222 struct cvmx_iob_n2c_rsp_pri_cnt_s cn66xx;
1223 struct cvmx_iob_n2c_rsp_pri_cnt_s cnf71xx;
1224 };
1225 typedef union cvmx_iob_n2c_rsp_pri_cnt cvmx_iob_n2c_rsp_pri_cnt_t;
1226
1227 /**
1228 * cvmx_iob_outb_com_pri_cnt
1229 *
1230 * Commit To NCB Priority Counter = Commit to NCB Priority Counter Enable and Timer Value
1231 *
1232 * Enables and supplies the timeout count for raising the priority of Commit request to the Outbound NCB.
1233 */
1234 union cvmx_iob_outb_com_pri_cnt {
1235 uint64_t u64;
1236 struct cvmx_iob_outb_com_pri_cnt_s {
1237 #ifdef __BIG_ENDIAN_BITFIELD
1238 uint64_t reserved_16_63 : 48;
1239 uint64_t cnt_enb : 1; /**< Enables the raising of NCB access priority
1240 when CNT_VAL is reached. */
1241 uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising
1242 the priority for access to NCB. */
1243 #else
1244 uint64_t cnt_val : 15;
1245 uint64_t cnt_enb : 1;
1246 uint64_t reserved_16_63 : 48;
1247 #endif
1248 } s;
1249 struct cvmx_iob_outb_com_pri_cnt_s cn38xx;
1250 struct cvmx_iob_outb_com_pri_cnt_s cn38xxp2;
1251 struct cvmx_iob_outb_com_pri_cnt_s cn52xx;
1252 struct cvmx_iob_outb_com_pri_cnt_s cn52xxp1;
1253 struct cvmx_iob_outb_com_pri_cnt_s cn56xx;
1254 struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1;
1255 struct cvmx_iob_outb_com_pri_cnt_s cn58xx;
1256 struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1;
1257 struct cvmx_iob_outb_com_pri_cnt_s cn61xx;
1258 struct cvmx_iob_outb_com_pri_cnt_s cn63xx;
1259 struct cvmx_iob_outb_com_pri_cnt_s cn63xxp1;
1260 struct cvmx_iob_outb_com_pri_cnt_s cn66xx;
1261 struct cvmx_iob_outb_com_pri_cnt_s cn68xx;
1262 struct cvmx_iob_outb_com_pri_cnt_s cn68xxp1;
1263 struct cvmx_iob_outb_com_pri_cnt_s cnf71xx;
1264 };
1265 typedef union cvmx_iob_outb_com_pri_cnt cvmx_iob_outb_com_pri_cnt_t;
1266
1267 /**
1268 * cvmx_iob_outb_control_match
1269 *
1270 * IOB_OUTB_CONTROL_MATCH = IOB Outbound Control Match
1271 *
1272 * Match pattern for the outbound control to set the OUTB_MATCH_BIT. PASS-2 Register
1273 */
1274 union cvmx_iob_outb_control_match {
1275 uint64_t u64;
1276 struct cvmx_iob_outb_control_match_s {
1277 #ifdef __BIG_ENDIAN_BITFIELD
1278 uint64_t reserved_26_63 : 38;
1279 uint64_t mask : 8; /**< Pattern to match on the outbound NCB. */
1280 uint64_t eot : 1; /**< Pattern to match on the outbound NCB. */
1281 uint64_t dst : 8; /**< Pattern to match on the outbound NCB. */
1282 uint64_t src : 9; /**< Pattern to match on the outbound NCB. */
1283 #else
1284 uint64_t src : 9;
1285 uint64_t dst : 8;
1286 uint64_t eot : 1;
1287 uint64_t mask : 8;
1288 uint64_t reserved_26_63 : 38;
1289 #endif
1290 } s;
1291 struct cvmx_iob_outb_control_match_s cn30xx;
1292 struct cvmx_iob_outb_control_match_s cn31xx;
1293 struct cvmx_iob_outb_control_match_s cn38xx;
1294 struct cvmx_iob_outb_control_match_s cn38xxp2;
1295 struct cvmx_iob_outb_control_match_s cn50xx;
1296 struct cvmx_iob_outb_control_match_s cn52xx;
1297 struct cvmx_iob_outb_control_match_s cn52xxp1;
1298 struct cvmx_iob_outb_control_match_s cn56xx;
1299 struct cvmx_iob_outb_control_match_s cn56xxp1;
1300 struct cvmx_iob_outb_control_match_s cn58xx;
1301 struct cvmx_iob_outb_control_match_s cn58xxp1;
1302 struct cvmx_iob_outb_control_match_s cn61xx;
1303 struct cvmx_iob_outb_control_match_s cn63xx;
1304 struct cvmx_iob_outb_control_match_s cn63xxp1;
1305 struct cvmx_iob_outb_control_match_s cn66xx;
1306 struct cvmx_iob_outb_control_match_s cn68xx;
1307 struct cvmx_iob_outb_control_match_s cn68xxp1;
1308 struct cvmx_iob_outb_control_match_s cnf71xx;
1309 };
1310 typedef union cvmx_iob_outb_control_match cvmx_iob_outb_control_match_t;
1311
1312 /**
1313 * cvmx_iob_outb_control_match_enb
1314 *
1315 * IOB_OUTB_CONTROL_MATCH_ENB = IOB Outbound Control Match Enable
1316 *
1317 * Enables the match of the corresponding bit in the IOB_OUTB_CONTROL_MATCH reister. PASS-2 Register
1318 */
1319 union cvmx_iob_outb_control_match_enb {
1320 uint64_t u64;
1321 struct cvmx_iob_outb_control_match_enb_s {
1322 #ifdef __BIG_ENDIAN_BITFIELD
1323 uint64_t reserved_26_63 : 38;
1324 uint64_t mask : 8; /**< Pattern to match on the outbound NCB. */
1325 uint64_t eot : 1; /**< Pattern to match on the outbound NCB. */
1326 uint64_t dst : 8; /**< Pattern to match on the outbound NCB. */
1327 uint64_t src : 9; /**< Pattern to match on the outbound NCB. */
1328 #else
1329 uint64_t src : 9;
1330 uint64_t dst : 8;
1331 uint64_t eot : 1;
1332 uint64_t mask : 8;
1333 uint64_t reserved_26_63 : 38;
1334 #endif
1335 } s;
1336 struct cvmx_iob_outb_control_match_enb_s cn30xx;
1337 struct cvmx_iob_outb_control_match_enb_s cn31xx;
1338 struct cvmx_iob_outb_control_match_enb_s cn38xx;
1339 struct cvmx_iob_outb_control_match_enb_s cn38xxp2;
1340 struct cvmx_iob_outb_control_match_enb_s cn50xx;
1341 struct cvmx_iob_outb_control_match_enb_s cn52xx;
1342 struct cvmx_iob_outb_control_match_enb_s cn52xxp1;
1343 struct cvmx_iob_outb_control_match_enb_s cn56xx;
1344 struct cvmx_iob_outb_control_match_enb_s cn56xxp1;
1345 struct cvmx_iob_outb_control_match_enb_s cn58xx;
1346 struct cvmx_iob_outb_control_match_enb_s cn58xxp1;
1347 struct cvmx_iob_outb_control_match_enb_s cn61xx;
1348 struct cvmx_iob_outb_control_match_enb_s cn63xx;
1349 struct cvmx_iob_outb_control_match_enb_s cn63xxp1;
1350 struct cvmx_iob_outb_control_match_enb_s cn66xx;
1351 struct cvmx_iob_outb_control_match_enb_s cn68xx;
1352 struct cvmx_iob_outb_control_match_enb_s cn68xxp1;
1353 struct cvmx_iob_outb_control_match_enb_s cnf71xx;
1354 };
1355 typedef union cvmx_iob_outb_control_match_enb cvmx_iob_outb_control_match_enb_t;
1356
1357 /**
1358 * cvmx_iob_outb_data_match
1359 *
1360 * IOB_OUTB_DATA_MATCH = IOB Outbound Data Match
1361 *
1362 * Match pattern for the outbound data to set the OUTB_MATCH_BIT. PASS-2 Register
1363 */
1364 union cvmx_iob_outb_data_match {
1365 uint64_t u64;
1366 struct cvmx_iob_outb_data_match_s {
1367 #ifdef __BIG_ENDIAN_BITFIELD
1368 uint64_t data : 64; /**< Pattern to match on the outbound NCB. */
1369 #else
1370 uint64_t data : 64;
1371 #endif
1372 } s;
1373 struct cvmx_iob_outb_data_match_s cn30xx;
1374 struct cvmx_iob_outb_data_match_s cn31xx;
1375 struct cvmx_iob_outb_data_match_s cn38xx;
1376 struct cvmx_iob_outb_data_match_s cn38xxp2;
1377 struct cvmx_iob_outb_data_match_s cn50xx;
1378 struct cvmx_iob_outb_data_match_s cn52xx;
1379 struct cvmx_iob_outb_data_match_s cn52xxp1;
1380 struct cvmx_iob_outb_data_match_s cn56xx;
1381 struct cvmx_iob_outb_data_match_s cn56xxp1;
1382 struct cvmx_iob_outb_data_match_s cn58xx;
1383 struct cvmx_iob_outb_data_match_s cn58xxp1;
1384 struct cvmx_iob_outb_data_match_s cn61xx;
1385 struct cvmx_iob_outb_data_match_s cn63xx;
1386 struct cvmx_iob_outb_data_match_s cn63xxp1;
1387 struct cvmx_iob_outb_data_match_s cn66xx;
1388 struct cvmx_iob_outb_data_match_s cn68xx;
1389 struct cvmx_iob_outb_data_match_s cn68xxp1;
1390 struct cvmx_iob_outb_data_match_s cnf71xx;
1391 };
1392 typedef union cvmx_iob_outb_data_match cvmx_iob_outb_data_match_t;
1393
1394 /**
1395 * cvmx_iob_outb_data_match_enb
1396 *
1397 * IOB_OUTB_DATA_MATCH_ENB = IOB Outbound Data Match Enable
1398 *
1399 * Enables the match of the corresponding bit in the IOB_OUTB_DATA_MATCH reister. PASS-2 Register
1400 */
1401 union cvmx_iob_outb_data_match_enb {
1402 uint64_t u64;
1403 struct cvmx_iob_outb_data_match_enb_s {
1404 #ifdef __BIG_ENDIAN_BITFIELD
1405 uint64_t data : 64; /**< Bit to enable match of. */
1406 #else
1407 uint64_t data : 64;
1408 #endif
1409 } s;
1410 struct cvmx_iob_outb_data_match_enb_s cn30xx;
1411 struct cvmx_iob_outb_data_match_enb_s cn31xx;
1412 struct cvmx_iob_outb_data_match_enb_s cn38xx;
1413 struct cvmx_iob_outb_data_match_enb_s cn38xxp2;
1414 struct cvmx_iob_outb_data_match_enb_s cn50xx;
1415 struct cvmx_iob_outb_data_match_enb_s cn52xx;
1416 struct cvmx_iob_outb_data_match_enb_s cn52xxp1;
1417 struct cvmx_iob_outb_data_match_enb_s cn56xx;
1418 struct cvmx_iob_outb_data_match_enb_s cn56xxp1;
1419 struct cvmx_iob_outb_data_match_enb_s cn58xx;
1420 struct cvmx_iob_outb_data_match_enb_s cn58xxp1;
1421 struct cvmx_iob_outb_data_match_enb_s cn61xx;
1422 struct cvmx_iob_outb_data_match_enb_s cn63xx;
1423 struct cvmx_iob_outb_data_match_enb_s cn63xxp1;
1424 struct cvmx_iob_outb_data_match_enb_s cn66xx;
1425 struct cvmx_iob_outb_data_match_enb_s cn68xx;
1426 struct cvmx_iob_outb_data_match_enb_s cn68xxp1;
1427 struct cvmx_iob_outb_data_match_enb_s cnf71xx;
1428 };
1429 typedef union cvmx_iob_outb_data_match_enb cvmx_iob_outb_data_match_enb_t;
1430
1431 /**
1432 * cvmx_iob_outb_fpa_pri_cnt
1433 *
1434 * FPA To NCB Priority Counter = FPA Returns to NCB Priority Counter Enable and Timer Value
1435 *
1436 * Enables and supplies the timeout count for raising the priority of FPA Rreturn Page request to the Outbound NCB.
1437 */
1438 union cvmx_iob_outb_fpa_pri_cnt {
1439 uint64_t u64;
1440 struct cvmx_iob_outb_fpa_pri_cnt_s {
1441 #ifdef __BIG_ENDIAN_BITFIELD
1442 uint64_t reserved_16_63 : 48;
1443 uint64_t cnt_enb : 1; /**< Enables the raising of NCB access priority
1444 when CNT_VAL is reached. */
1445 uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising
1446 the priority for access to NCB. */
1447 #else
1448 uint64_t cnt_val : 15;
1449 uint64_t cnt_enb : 1;
1450 uint64_t reserved_16_63 : 48;
1451 #endif
1452 } s;
1453 struct cvmx_iob_outb_fpa_pri_cnt_s cn38xx;
1454 struct cvmx_iob_outb_fpa_pri_cnt_s cn38xxp2;
1455 struct cvmx_iob_outb_fpa_pri_cnt_s cn52xx;
1456 struct cvmx_iob_outb_fpa_pri_cnt_s cn52xxp1;
1457 struct cvmx_iob_outb_fpa_pri_cnt_s cn56xx;
1458 struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1;
1459 struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx;
1460 struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1;
1461 struct cvmx_iob_outb_fpa_pri_cnt_s cn61xx;
1462 struct cvmx_iob_outb_fpa_pri_cnt_s cn63xx;
1463 struct cvmx_iob_outb_fpa_pri_cnt_s cn63xxp1;
1464 struct cvmx_iob_outb_fpa_pri_cnt_s cn66xx;
1465 struct cvmx_iob_outb_fpa_pri_cnt_s cn68xx;
1466 struct cvmx_iob_outb_fpa_pri_cnt_s cn68xxp1;
1467 struct cvmx_iob_outb_fpa_pri_cnt_s cnf71xx;
1468 };
1469 typedef union cvmx_iob_outb_fpa_pri_cnt cvmx_iob_outb_fpa_pri_cnt_t;
1470
1471 /**
1472 * cvmx_iob_outb_req_pri_cnt
1473 *
1474 * Request To NCB Priority Counter = Request to NCB Priority Counter Enable and Timer Value
1475 *
1476 * Enables and supplies the timeout count for raising the priority of Request transfers to the Outbound NCB.
1477 */
1478 union cvmx_iob_outb_req_pri_cnt {
1479 uint64_t u64;
1480 struct cvmx_iob_outb_req_pri_cnt_s {
1481 #ifdef __BIG_ENDIAN_BITFIELD
1482 uint64_t reserved_16_63 : 48;
1483 uint64_t cnt_enb : 1; /**< Enables the raising of NCB access priority
1484 when CNT_VAL is reached. */
1485 uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising
1486 the priority for access to NCB. */
1487 #else
1488 uint64_t cnt_val : 15;
1489 uint64_t cnt_enb : 1;
1490 uint64_t reserved_16_63 : 48;
1491 #endif
1492 } s;
1493 struct cvmx_iob_outb_req_pri_cnt_s cn38xx;
1494 struct cvmx_iob_outb_req_pri_cnt_s cn38xxp2;
1495 struct cvmx_iob_outb_req_pri_cnt_s cn52xx;
1496 struct cvmx_iob_outb_req_pri_cnt_s cn52xxp1;
1497 struct cvmx_iob_outb_req_pri_cnt_s cn56xx;
1498 struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1;
1499 struct cvmx_iob_outb_req_pri_cnt_s cn58xx;
1500 struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1;
1501 struct cvmx_iob_outb_req_pri_cnt_s cn61xx;
1502 struct cvmx_iob_outb_req_pri_cnt_s cn63xx;
1503 struct cvmx_iob_outb_req_pri_cnt_s cn63xxp1;
1504 struct cvmx_iob_outb_req_pri_cnt_s cn66xx;
1505 struct cvmx_iob_outb_req_pri_cnt_s cn68xx;
1506 struct cvmx_iob_outb_req_pri_cnt_s cn68xxp1;
1507 struct cvmx_iob_outb_req_pri_cnt_s cnf71xx;
1508 };
1509 typedef union cvmx_iob_outb_req_pri_cnt cvmx_iob_outb_req_pri_cnt_t;
1510
1511 /**
1512 * cvmx_iob_p2c_req_pri_cnt
1513 *
1514 * PKO To CMB Response Priority Counter = PKO to CMB Response Priority Counter Enable and Timer Value
1515 *
1516 * Enables and supplies the timeout count for raising the priority of PKO Load access to the CMB.
1517 */
1518 union cvmx_iob_p2c_req_pri_cnt {
1519 uint64_t u64;
1520 struct cvmx_iob_p2c_req_pri_cnt_s {
1521 #ifdef __BIG_ENDIAN_BITFIELD
1522 uint64_t reserved_16_63 : 48;
1523 uint64_t cnt_enb : 1; /**< Enables the raising of CMB access priority
1524 when CNT_VAL is reached. */
1525 uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising
1526 the priority for access to CMB. */
1527 #else
1528 uint64_t cnt_val : 15;
1529 uint64_t cnt_enb : 1;
1530 uint64_t reserved_16_63 : 48;
1531 #endif
1532 } s;
1533 struct cvmx_iob_p2c_req_pri_cnt_s cn38xx;
1534 struct cvmx_iob_p2c_req_pri_cnt_s cn38xxp2;
1535 struct cvmx_iob_p2c_req_pri_cnt_s cn52xx;
1536 struct cvmx_iob_p2c_req_pri_cnt_s cn52xxp1;
1537 struct cvmx_iob_p2c_req_pri_cnt_s cn56xx;
1538 struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1;
1539 struct cvmx_iob_p2c_req_pri_cnt_s cn58xx;
1540 struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1;
1541 struct cvmx_iob_p2c_req_pri_cnt_s cn61xx;
1542 struct cvmx_iob_p2c_req_pri_cnt_s cn63xx;
1543 struct cvmx_iob_p2c_req_pri_cnt_s cn63xxp1;
1544 struct cvmx_iob_p2c_req_pri_cnt_s cn66xx;
1545 struct cvmx_iob_p2c_req_pri_cnt_s cnf71xx;
1546 };
1547 typedef union cvmx_iob_p2c_req_pri_cnt cvmx_iob_p2c_req_pri_cnt_t;
1548
1549 /**
1550 * cvmx_iob_pkt_err
1551 *
1552 * IOB_PKT_ERR = IOB Packet Error Register
1553 *
1554 * Provides status about the failing packet recevie error. This is a PASS-2 register.
1555 */
1556 union cvmx_iob_pkt_err {
1557 uint64_t u64;
1558 struct cvmx_iob_pkt_err_s {
1559 #ifdef __BIG_ENDIAN_BITFIELD
1560 uint64_t reserved_12_63 : 52;
1561 uint64_t vport : 6; /**< When IOB_INT_SUM[3:0] bit is set, this field
1562 latches the failing vport associate with the
1563 IOB_INT_SUM[3:0] bit set. */
1564 uint64_t port : 6; /**< When IOB_INT_SUM[3:0] bit is set, this field
1565 latches the failing port associate with the
1566 IOB_INT_SUM[3:0] bit set. */
1567 #else
1568 uint64_t port : 6;
1569 uint64_t vport : 6;
1570 uint64_t reserved_12_63 : 52;
1571 #endif
1572 } s;
1573 struct cvmx_iob_pkt_err_cn30xx {
1574 #ifdef __BIG_ENDIAN_BITFIELD
1575 uint64_t reserved_6_63 : 58;
1576 uint64_t port : 6; /**< When IOB_INT_SUM[3:0] bit is set, this field
1577 latches the failing port associate with the
1578 IOB_INT_SUM[3:0] bit set. */
1579 #else
1580 uint64_t port : 6;
1581 uint64_t reserved_6_63 : 58;
1582 #endif
1583 } cn30xx;
1584 struct cvmx_iob_pkt_err_cn30xx cn31xx;
1585 struct cvmx_iob_pkt_err_cn30xx cn38xx;
1586 struct cvmx_iob_pkt_err_cn30xx cn38xxp2;
1587 struct cvmx_iob_pkt_err_cn30xx cn50xx;
1588 struct cvmx_iob_pkt_err_cn30xx cn52xx;
1589 struct cvmx_iob_pkt_err_cn30xx cn52xxp1;
1590 struct cvmx_iob_pkt_err_cn30xx cn56xx;
1591 struct cvmx_iob_pkt_err_cn30xx cn56xxp1;
1592 struct cvmx_iob_pkt_err_cn30xx cn58xx;
1593 struct cvmx_iob_pkt_err_cn30xx cn58xxp1;
1594 struct cvmx_iob_pkt_err_s cn61xx;
1595 struct cvmx_iob_pkt_err_s cn63xx;
1596 struct cvmx_iob_pkt_err_s cn63xxp1;
1597 struct cvmx_iob_pkt_err_s cn66xx;
1598 struct cvmx_iob_pkt_err_s cnf71xx;
1599 };
1600 typedef union cvmx_iob_pkt_err cvmx_iob_pkt_err_t;
1601
1602 /**
1603 * cvmx_iob_to_cmb_credits
1604 *
1605 * IOB_TO_CMB_CREDITS = IOB To CMB Credits
1606 *
1607 * Controls the number of reads and writes that may be outstanding to the L2C (via the CMB).
1608 */
1609 union cvmx_iob_to_cmb_credits {
1610 uint64_t u64;
1611 struct cvmx_iob_to_cmb_credits_s {
1612 #ifdef __BIG_ENDIAN_BITFIELD
1613 uint64_t reserved_6_63 : 58;
1614 uint64_t ncb_rd : 3; /**< Number of NCB reads that can be out to L2C where
1615 0 == 8-credits. */
1616 uint64_t ncb_wr : 3; /**< Number of NCB/PKI writes that can be out to L2C
1617 where 0 == 8-credits. */
1618 #else
1619 uint64_t ncb_wr : 3;
1620 uint64_t ncb_rd : 3;
1621 uint64_t reserved_6_63 : 58;
1622 #endif
1623 } s;
1624 struct cvmx_iob_to_cmb_credits_cn52xx {
1625 #ifdef __BIG_ENDIAN_BITFIELD
1626 uint64_t reserved_9_63 : 55;
1627 uint64_t pko_rd : 3; /**< Number of PKO reads that can be out to L2C where
1628 0 == 8-credits. */
1629 uint64_t ncb_rd : 3; /**< Number of NCB reads that can be out to L2C where
1630 0 == 8-credits. */
1631 uint64_t ncb_wr : 3; /**< Number of NCB/PKI writes that can be out to L2C
1632 where 0 == 8-credits. */
1633 #else
1634 uint64_t ncb_wr : 3;
1635 uint64_t ncb_rd : 3;
1636 uint64_t pko_rd : 3;
1637 uint64_t reserved_9_63 : 55;
1638 #endif
1639 } cn52xx;
1640 struct cvmx_iob_to_cmb_credits_cn52xx cn61xx;
1641 struct cvmx_iob_to_cmb_credits_cn52xx cn63xx;
1642 struct cvmx_iob_to_cmb_credits_cn52xx cn63xxp1;
1643 struct cvmx_iob_to_cmb_credits_cn52xx cn66xx;
1644 struct cvmx_iob_to_cmb_credits_cn68xx {
1645 #ifdef __BIG_ENDIAN_BITFIELD
1646 uint64_t reserved_9_63 : 55;
1647 uint64_t dwb : 3; /**< Number of DWBs that can be out to L2C where
1648 0 == 8-credits. */
1649 uint64_t ncb_rd : 3; /**< Number of NCB reads that can be out to L2C where
1650 0 == 8-credits. */
1651 uint64_t ncb_wr : 3; /**< Number of NCB/PKI writes that can be out to L2C
1652 where 0 == 8-credits. */
1653 #else
1654 uint64_t ncb_wr : 3;
1655 uint64_t ncb_rd : 3;
1656 uint64_t dwb : 3;
1657 uint64_t reserved_9_63 : 55;
1658 #endif
1659 } cn68xx;
1660 struct cvmx_iob_to_cmb_credits_cn68xx cn68xxp1;
1661 struct cvmx_iob_to_cmb_credits_cn52xx cnf71xx;
1662 };
1663 typedef union cvmx_iob_to_cmb_credits cvmx_iob_to_cmb_credits_t;
1664
1665 /**
1666 * cvmx_iob_to_ncb_did_00_credits
1667 *
1668 * IOB_TO_NCB_DID_00_CREDITS = IOB NCB DID 00 Credits
1669 *
1670 * Number of credits for NCB DID 00.
1671 */
1672 union cvmx_iob_to_ncb_did_00_credits {
1673 uint64_t u64;
1674 struct cvmx_iob_to_ncb_did_00_credits_s {
1675 #ifdef __BIG_ENDIAN_BITFIELD
1676 uint64_t reserved_7_63 : 57;
1677 uint64_t crd : 7; /**< Number of credits for DID. Writing this field will
1678 casuse the credits to be set to the value written.
1679 Reading this field will give the number of credits
1680 PRESENTLY available. */
1681 #else
1682 uint64_t crd : 7;
1683 uint64_t reserved_7_63 : 57;
1684 #endif
1685 } s;
1686 struct cvmx_iob_to_ncb_did_00_credits_s cn68xx;
1687 struct cvmx_iob_to_ncb_did_00_credits_s cn68xxp1;
1688 };
1689 typedef union cvmx_iob_to_ncb_did_00_credits cvmx_iob_to_ncb_did_00_credits_t;
1690
1691 /**
1692 * cvmx_iob_to_ncb_did_111_credits
1693 *
1694 * IOB_TO_NCB_DID_111_CREDITS = IOB NCB DID 111 Credits
1695 *
1696 * Number of credits for NCB DID 111.
1697 */
1698 union cvmx_iob_to_ncb_did_111_credits {
1699 uint64_t u64;
1700 struct cvmx_iob_to_ncb_did_111_credits_s {
1701 #ifdef __BIG_ENDIAN_BITFIELD
1702 uint64_t reserved_7_63 : 57;
1703 uint64_t crd : 7; /**< Number of credits for DID. Writing this field will
1704 casuse the credits to be set to the value written.
1705 Reading this field will give the number of credits
1706 PRESENTLY available. */
1707 #else
1708 uint64_t crd : 7;
1709 uint64_t reserved_7_63 : 57;
1710 #endif
1711 } s;
1712 struct cvmx_iob_to_ncb_did_111_credits_s cn68xx;
1713 struct cvmx_iob_to_ncb_did_111_credits_s cn68xxp1;
1714 };
1715 typedef union cvmx_iob_to_ncb_did_111_credits cvmx_iob_to_ncb_did_111_credits_t;
1716
1717 /**
1718 * cvmx_iob_to_ncb_did_223_credits
1719 *
1720 * IOB_TO_NCB_DID_223_CREDITS = IOB NCB DID 223 Credits
1721 *
1722 * Number of credits for NCB DID 223.
1723 */
1724 union cvmx_iob_to_ncb_did_223_credits {
1725 uint64_t u64;
1726 struct cvmx_iob_to_ncb_did_223_credits_s {
1727 #ifdef __BIG_ENDIAN_BITFIELD
1728 uint64_t reserved_7_63 : 57;
1729 uint64_t crd : 7; /**< Number of credits for DID. Writing this field will
1730 casuse the credits to be set to the value written.
1731 Reading this field will give the number of credits
1732 PRESENTLY available. */
1733 #else
1734 uint64_t crd : 7;
1735 uint64_t reserved_7_63 : 57;
1736 #endif
1737 } s;
1738 struct cvmx_iob_to_ncb_did_223_credits_s cn68xx;
1739 struct cvmx_iob_to_ncb_did_223_credits_s cn68xxp1;
1740 };
1741 typedef union cvmx_iob_to_ncb_did_223_credits cvmx_iob_to_ncb_did_223_credits_t;
1742
1743 /**
1744 * cvmx_iob_to_ncb_did_24_credits
1745 *
1746 * IOB_TO_NCB_DID_24_CREDITS = IOB NCB DID 24 Credits
1747 *
1748 * Number of credits for NCB DID 24.
1749 */
1750 union cvmx_iob_to_ncb_did_24_credits {
1751 uint64_t u64;
1752 struct cvmx_iob_to_ncb_did_24_credits_s {
1753 #ifdef __BIG_ENDIAN_BITFIELD
1754 uint64_t reserved_7_63 : 57;
1755 uint64_t crd : 7; /**< Number of credits for DID. Writing this field will
1756 casuse the credits to be set to the value written.
1757 Reading this field will give the number of credits
1758 PRESENTLY available. */
1759 #else
1760 uint64_t crd : 7;
1761 uint64_t reserved_7_63 : 57;
1762 #endif
1763 } s;
1764 struct cvmx_iob_to_ncb_did_24_credits_s cn68xx;
1765 struct cvmx_iob_to_ncb_did_24_credits_s cn68xxp1;
1766 };
1767 typedef union cvmx_iob_to_ncb_did_24_credits cvmx_iob_to_ncb_did_24_credits_t;
1768
1769 /**
1770 * cvmx_iob_to_ncb_did_32_credits
1771 *
1772 * IOB_TO_NCB_DID_32_CREDITS = IOB NCB DID 32 Credits
1773 *
1774 * Number of credits for NCB DID 32.
1775 */
1776 union cvmx_iob_to_ncb_did_32_credits {
1777 uint64_t u64;
1778 struct cvmx_iob_to_ncb_did_32_credits_s {
1779 #ifdef __BIG_ENDIAN_BITFIELD
1780 uint64_t reserved_7_63 : 57;
1781 uint64_t crd : 7; /**< Number of credits for DID. Writing this field will
1782 casuse the credits to be set to the value written.
1783 Reading this field will give the number of credits
1784 PRESENTLY available. */
1785 #else
1786 uint64_t crd : 7;
1787 uint64_t reserved_7_63 : 57;
1788 #endif
1789 } s;
1790 struct cvmx_iob_to_ncb_did_32_credits_s cn68xx;
1791 struct cvmx_iob_to_ncb_did_32_credits_s cn68xxp1;
1792 };
1793 typedef union cvmx_iob_to_ncb_did_32_credits cvmx_iob_to_ncb_did_32_credits_t;
1794
1795 /**
1796 * cvmx_iob_to_ncb_did_40_credits
1797 *
1798 * IOB_TO_NCB_DID_40_CREDITS = IOB NCB DID 40 Credits
1799 *
1800 * Number of credits for NCB DID 40.
1801 */
1802 union cvmx_iob_to_ncb_did_40_credits {
1803 uint64_t u64;
1804 struct cvmx_iob_to_ncb_did_40_credits_s {
1805 #ifdef __BIG_ENDIAN_BITFIELD
1806 uint64_t reserved_7_63 : 57;
1807 uint64_t crd : 7; /**< Number of credits for DID. Writing this field will
1808 casuse the credits to be set to the value written.
1809 Reading this field will give the number of credits
1810 PRESENTLY available. */
1811 #else
1812 uint64_t crd : 7;
1813 uint64_t reserved_7_63 : 57;
1814 #endif
1815 } s;
1816 struct cvmx_iob_to_ncb_did_40_credits_s cn68xx;
1817 struct cvmx_iob_to_ncb_did_40_credits_s cn68xxp1;
1818 };
1819 typedef union cvmx_iob_to_ncb_did_40_credits cvmx_iob_to_ncb_did_40_credits_t;
1820
1821 /**
1822 * cvmx_iob_to_ncb_did_55_credits
1823 *
1824 * IOB_TO_NCB_DID_55_CREDITS = IOB NCB DID 55 Credits
1825 *
1826 * Number of credits for NCB DID 55.
1827 */
1828 union cvmx_iob_to_ncb_did_55_credits {
1829 uint64_t u64;
1830 struct cvmx_iob_to_ncb_did_55_credits_s {
1831 #ifdef __BIG_ENDIAN_BITFIELD
1832 uint64_t reserved_7_63 : 57;
1833 uint64_t crd : 7; /**< Number of credits for DID. Writing this field will
1834 casuse the credits to be set to the value written.
1835 Reading this field will give the number of credits
1836 PRESENTLY available. */
1837 #else
1838 uint64_t crd : 7;
1839 uint64_t reserved_7_63 : 57;
1840 #endif
1841 } s;
1842 struct cvmx_iob_to_ncb_did_55_credits_s cn68xx;
1843 struct cvmx_iob_to_ncb_did_55_credits_s cn68xxp1;
1844 };
1845 typedef union cvmx_iob_to_ncb_did_55_credits cvmx_iob_to_ncb_did_55_credits_t;
1846
1847 /**
1848 * cvmx_iob_to_ncb_did_64_credits
1849 *
1850 * IOB_TO_NCB_DID_64_CREDITS = IOB NCB DID 64 Credits
1851 *
1852 * Number of credits for NCB DID 64.
1853 */
1854 union cvmx_iob_to_ncb_did_64_credits {
1855 uint64_t u64;
1856 struct cvmx_iob_to_ncb_did_64_credits_s {
1857 #ifdef __BIG_ENDIAN_BITFIELD
1858 uint64_t reserved_7_63 : 57;
1859 uint64_t crd : 7; /**< Number of credits for DID. Writing this field will
1860 casuse the credits to be set to the value written.
1861 Reading this field will give the number of credits
1862 PRESENTLY available. */
1863 #else
1864 uint64_t crd : 7;
1865 uint64_t reserved_7_63 : 57;
1866 #endif
1867 } s;
1868 struct cvmx_iob_to_ncb_did_64_credits_s cn68xx;
1869 struct cvmx_iob_to_ncb_did_64_credits_s cn68xxp1;
1870 };
1871 typedef union cvmx_iob_to_ncb_did_64_credits cvmx_iob_to_ncb_did_64_credits_t;
1872
1873 /**
1874 * cvmx_iob_to_ncb_did_79_credits
1875 *
1876 * IOB_TO_NCB_DID_79_CREDITS = IOB NCB DID 79 Credits
1877 *
1878 * Number of credits for NCB DID 79.
1879 */
1880 union cvmx_iob_to_ncb_did_79_credits {
1881 uint64_t u64;
1882 struct cvmx_iob_to_ncb_did_79_credits_s {
1883 #ifdef __BIG_ENDIAN_BITFIELD
1884 uint64_t reserved_7_63 : 57;
1885 uint64_t crd : 7; /**< Number of credits for DID. Writing this field will
1886 casuse the credits to be set to the value written.
1887 Reading this field will give the number of credits
1888 PRESENTLY available. */
1889 #else
1890 uint64_t crd : 7;
1891 uint64_t reserved_7_63 : 57;
1892 #endif
1893 } s;
1894 struct cvmx_iob_to_ncb_did_79_credits_s cn68xx;
1895 struct cvmx_iob_to_ncb_did_79_credits_s cn68xxp1;
1896 };
1897 typedef union cvmx_iob_to_ncb_did_79_credits cvmx_iob_to_ncb_did_79_credits_t;
1898
1899 /**
1900 * cvmx_iob_to_ncb_did_96_credits
1901 *
1902 * IOB_TO_NCB_DID_96_CREDITS = IOB NCB DID 96 Credits
1903 *
1904 * Number of credits for NCB DID 96.
1905 */
1906 union cvmx_iob_to_ncb_did_96_credits {
1907 uint64_t u64;
1908 struct cvmx_iob_to_ncb_did_96_credits_s {
1909 #ifdef __BIG_ENDIAN_BITFIELD
1910 uint64_t reserved_7_63 : 57;
1911 uint64_t crd : 7; /**< Number of credits for DID. Writing this field will
1912 casuse the credits to be set to the value written.
1913 Reading this field will give the number of credits
1914 PRESENTLY available. */
1915 #else
1916 uint64_t crd : 7;
1917 uint64_t reserved_7_63 : 57;
1918 #endif
1919 } s;
1920 struct cvmx_iob_to_ncb_did_96_credits_s cn68xx;
1921 struct cvmx_iob_to_ncb_did_96_credits_s cn68xxp1;
1922 };
1923 typedef union cvmx_iob_to_ncb_did_96_credits cvmx_iob_to_ncb_did_96_credits_t;
1924
1925 /**
1926 * cvmx_iob_to_ncb_did_98_credits
1927 *
1928 * IOB_TO_NCB_DID_98_CREDITS = IOB NCB DID 96 Credits
1929 *
1930 * Number of credits for NCB DID 98.
1931 */
1932 union cvmx_iob_to_ncb_did_98_credits {
1933 uint64_t u64;
1934 struct cvmx_iob_to_ncb_did_98_credits_s {
1935 #ifdef __BIG_ENDIAN_BITFIELD
1936 uint64_t reserved_7_63 : 57;
1937 uint64_t crd : 7; /**< Number of credits for DID. Writing this field will
1938 casuse the credits to be set to the value written.
1939 Reading this field will give the number of credits
1940 PRESENTLY available. */
1941 #else
1942 uint64_t crd : 7;
1943 uint64_t reserved_7_63 : 57;
1944 #endif
1945 } s;
1946 struct cvmx_iob_to_ncb_did_98_credits_s cn68xx;
1947 struct cvmx_iob_to_ncb_did_98_credits_s cn68xxp1;
1948 };
1949 typedef union cvmx_iob_to_ncb_did_98_credits cvmx_iob_to_ncb_did_98_credits_t;
1950
1951 #endif
1952