1 /***********************license start***************
2 * Copyright (c) 2003-2012 Cavium Inc. ([email protected]). All rights
3 * reserved.
4 *
5 *
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7 * modification, are permitted provided that the following conditions are
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9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17
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20 * derived from this software without specific prior written
21 * permission.
22
23 * This Software, including technical data, may be subject to U.S. export control
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25 * regulations, and may be subject to export or import regulations in other
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27
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
39
40
41 /**
42 * cvmx-gpio-defs.h
43 *
44 * Configuration and status register (CSR) type definitions for
45 * Octeon gpio.
46 *
47 * This file is auto generated. Do not edit.
48 *
49 * <hr>$Revision$<hr>
50 *
51 */
52 #ifndef __CVMX_GPIO_DEFS_H__
53 #define __CVMX_GPIO_DEFS_H__
54
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_GPIO_BIT_CFGX(unsigned long offset)56 static inline uint64_t CVMX_GPIO_BIT_CFGX(unsigned long offset)
57 {
58 if (!(
59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
62 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
63 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
64 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
65 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
66 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) ||
67 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) ||
68 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) ||
69 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 15))) ||
70 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15)))))
71 cvmx_warn("CVMX_GPIO_BIT_CFGX(%lu) is invalid on this chip\n", offset);
72 return CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8;
73 }
74 #else
75 #define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
76 #endif
77 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
78 #define CVMX_GPIO_BOOT_ENA CVMX_GPIO_BOOT_ENA_FUNC()
CVMX_GPIO_BOOT_ENA_FUNC(void)79 static inline uint64_t CVMX_GPIO_BOOT_ENA_FUNC(void)
80 {
81 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
82 cvmx_warn("CVMX_GPIO_BOOT_ENA not supported on this chip\n");
83 return CVMX_ADD_IO_SEG(0x00010700000008A8ull);
84 }
85 #else
86 #define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))
87 #endif
88 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_GPIO_CLK_GENX(unsigned long offset)89 static inline uint64_t CVMX_GPIO_CLK_GENX(unsigned long offset)
90 {
91 if (!(
92 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
93 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
94 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
95 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3))) ||
96 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
97 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
98 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
99 cvmx_warn("CVMX_GPIO_CLK_GENX(%lu) is invalid on this chip\n", offset);
100 return CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8;
101 }
102 #else
103 #define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
104 #endif
105 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_GPIO_CLK_QLMX(unsigned long offset)106 static inline uint64_t CVMX_GPIO_CLK_QLMX(unsigned long offset)
107 {
108 if (!(
109 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
110 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
111 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
112 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
113 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
114 cvmx_warn("CVMX_GPIO_CLK_QLMX(%lu) is invalid on this chip\n", offset);
115 return CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8;
116 }
117 #else
118 #define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
119 #endif
120 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
121 #define CVMX_GPIO_DBG_ENA CVMX_GPIO_DBG_ENA_FUNC()
CVMX_GPIO_DBG_ENA_FUNC(void)122 static inline uint64_t CVMX_GPIO_DBG_ENA_FUNC(void)
123 {
124 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
125 cvmx_warn("CVMX_GPIO_DBG_ENA not supported on this chip\n");
126 return CVMX_ADD_IO_SEG(0x00010700000008A0ull);
127 }
128 #else
129 #define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
130 #endif
131 #define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
132 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
133 #define CVMX_GPIO_MULTI_CAST CVMX_GPIO_MULTI_CAST_FUNC()
CVMX_GPIO_MULTI_CAST_FUNC(void)134 static inline uint64_t CVMX_GPIO_MULTI_CAST_FUNC(void)
135 {
136 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
137 cvmx_warn("CVMX_GPIO_MULTI_CAST not supported on this chip\n");
138 return CVMX_ADD_IO_SEG(0x00010700000008B0ull);
139 }
140 #else
141 #define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull))
142 #endif
143 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
144 #define CVMX_GPIO_PIN_ENA CVMX_GPIO_PIN_ENA_FUNC()
CVMX_GPIO_PIN_ENA_FUNC(void)145 static inline uint64_t CVMX_GPIO_PIN_ENA_FUNC(void)
146 {
147 if (!(OCTEON_IS_MODEL(OCTEON_CN66XX)))
148 cvmx_warn("CVMX_GPIO_PIN_ENA not supported on this chip\n");
149 return CVMX_ADD_IO_SEG(0x00010700000008B8ull);
150 }
151 #else
152 #define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull))
153 #endif
154 #define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
155 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
156 #define CVMX_GPIO_TIM_CTL CVMX_GPIO_TIM_CTL_FUNC()
CVMX_GPIO_TIM_CTL_FUNC(void)157 static inline uint64_t CVMX_GPIO_TIM_CTL_FUNC(void)
158 {
159 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
160 cvmx_warn("CVMX_GPIO_TIM_CTL not supported on this chip\n");
161 return CVMX_ADD_IO_SEG(0x00010700000008A0ull);
162 }
163 #else
164 #define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
165 #endif
166 #define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
167 #define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
168 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_GPIO_XBIT_CFGX(unsigned long offset)169 static inline uint64_t CVMX_GPIO_XBIT_CFGX(unsigned long offset)
170 {
171 if (!(
172 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 16) && (offset <= 23)))) ||
173 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 16) && (offset <= 23)))) ||
174 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 16) && (offset <= 23)))) ||
175 (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 16) && (offset <= 19)))) ||
176 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 16) && (offset <= 19)))) ||
177 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 16) && (offset <= 19))))))
178 cvmx_warn("CVMX_GPIO_XBIT_CFGX(%lu) is invalid on this chip\n", offset);
179 return CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16;
180 }
181 #else
182 #define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
183 #endif
184
185 /**
186 * cvmx_gpio_bit_cfg#
187 *
188 * Notes:
189 * Only first 16 GPIO pins can introduce interrupts, GPIO_XBIT_CFG16(17,18,19)[INT_EN] and [INT_TYPE]
190 * will not be used, read out always zero.
191 */
192 union cvmx_gpio_bit_cfgx {
193 uint64_t u64;
194 struct cvmx_gpio_bit_cfgx_s {
195 #ifdef __BIG_ENDIAN_BITFIELD
196 uint64_t reserved_17_63 : 47;
197 uint64_t synce_sel : 2; /**< Selects the QLM clock output
198 x0=Normal GPIO output
199 01=GPIO QLM clock selected by CSR GPIO_CLK_QLM0
200 11=GPIO QLM clock selected by CSR GPIO_CLK_QLM1 */
201 uint64_t clk_gen : 1; /**< When TX_OE is set, GPIO pin becomes a clock */
202 uint64_t clk_sel : 2; /**< Selects which of the 4 GPIO clock generators */
203 uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */
204 uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */
205 uint64_t int_type : 1; /**< Type of interrupt
206 0 = level (default)
207 1 = rising edge */
208 uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */
209 uint64_t rx_xor : 1; /**< Invert the GPIO pin */
210 uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */
211 #else
212 uint64_t tx_oe : 1;
213 uint64_t rx_xor : 1;
214 uint64_t int_en : 1;
215 uint64_t int_type : 1;
216 uint64_t fil_cnt : 4;
217 uint64_t fil_sel : 4;
218 uint64_t clk_sel : 2;
219 uint64_t clk_gen : 1;
220 uint64_t synce_sel : 2;
221 uint64_t reserved_17_63 : 47;
222 #endif
223 } s;
224 struct cvmx_gpio_bit_cfgx_cn30xx {
225 #ifdef __BIG_ENDIAN_BITFIELD
226 uint64_t reserved_12_63 : 52;
227 uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */
228 uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */
229 uint64_t int_type : 1; /**< Type of interrupt
230 0 = level (default)
231 1 = rising edge */
232 uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */
233 uint64_t rx_xor : 1; /**< Invert the GPIO pin */
234 uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */
235 #else
236 uint64_t tx_oe : 1;
237 uint64_t rx_xor : 1;
238 uint64_t int_en : 1;
239 uint64_t int_type : 1;
240 uint64_t fil_cnt : 4;
241 uint64_t fil_sel : 4;
242 uint64_t reserved_12_63 : 52;
243 #endif
244 } cn30xx;
245 struct cvmx_gpio_bit_cfgx_cn30xx cn31xx;
246 struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
247 struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
248 struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
249 struct cvmx_gpio_bit_cfgx_cn52xx {
250 #ifdef __BIG_ENDIAN_BITFIELD
251 uint64_t reserved_15_63 : 49;
252 uint64_t clk_gen : 1; /**< When TX_OE is set, GPIO pin becomes a clock */
253 uint64_t clk_sel : 2; /**< Selects which of the 4 GPIO clock generators */
254 uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */
255 uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */
256 uint64_t int_type : 1; /**< Type of interrupt
257 0 = level (default)
258 1 = rising edge */
259 uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */
260 uint64_t rx_xor : 1; /**< Invert the GPIO pin */
261 uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */
262 #else
263 uint64_t tx_oe : 1;
264 uint64_t rx_xor : 1;
265 uint64_t int_en : 1;
266 uint64_t int_type : 1;
267 uint64_t fil_cnt : 4;
268 uint64_t fil_sel : 4;
269 uint64_t clk_sel : 2;
270 uint64_t clk_gen : 1;
271 uint64_t reserved_15_63 : 49;
272 #endif
273 } cn52xx;
274 struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1;
275 struct cvmx_gpio_bit_cfgx_cn52xx cn56xx;
276 struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1;
277 struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
278 struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
279 struct cvmx_gpio_bit_cfgx_s cn61xx;
280 struct cvmx_gpio_bit_cfgx_s cn63xx;
281 struct cvmx_gpio_bit_cfgx_s cn63xxp1;
282 struct cvmx_gpio_bit_cfgx_s cn66xx;
283 struct cvmx_gpio_bit_cfgx_s cn68xx;
284 struct cvmx_gpio_bit_cfgx_s cn68xxp1;
285 struct cvmx_gpio_bit_cfgx_s cnf71xx;
286 };
287 typedef union cvmx_gpio_bit_cfgx cvmx_gpio_bit_cfgx_t;
288
289 /**
290 * cvmx_gpio_boot_ena
291 */
292 union cvmx_gpio_boot_ena {
293 uint64_t u64;
294 struct cvmx_gpio_boot_ena_s {
295 #ifdef __BIG_ENDIAN_BITFIELD
296 uint64_t reserved_12_63 : 52;
297 uint64_t boot_ena : 4; /**< Drive boot bus chip enables [7:4] on gpio [11:8] */
298 uint64_t reserved_0_7 : 8;
299 #else
300 uint64_t reserved_0_7 : 8;
301 uint64_t boot_ena : 4;
302 uint64_t reserved_12_63 : 52;
303 #endif
304 } s;
305 struct cvmx_gpio_boot_ena_s cn30xx;
306 struct cvmx_gpio_boot_ena_s cn31xx;
307 struct cvmx_gpio_boot_ena_s cn50xx;
308 };
309 typedef union cvmx_gpio_boot_ena cvmx_gpio_boot_ena_t;
310
311 /**
312 * cvmx_gpio_clk_gen#
313 */
314 union cvmx_gpio_clk_genx {
315 uint64_t u64;
316 struct cvmx_gpio_clk_genx_s {
317 #ifdef __BIG_ENDIAN_BITFIELD
318 uint64_t reserved_32_63 : 32;
319 uint64_t n : 32; /**< Determines the frequency of the GPIO clk generator
320 NOTE: Fgpio_clk = Feclk * N / 2^32
321 N = (Fgpio_clk / Feclk) * 2^32
322 NOTE: writing N == 0 stops the clock generator
323 N should be <= 2^31-1. */
324 #else
325 uint64_t n : 32;
326 uint64_t reserved_32_63 : 32;
327 #endif
328 } s;
329 struct cvmx_gpio_clk_genx_s cn52xx;
330 struct cvmx_gpio_clk_genx_s cn52xxp1;
331 struct cvmx_gpio_clk_genx_s cn56xx;
332 struct cvmx_gpio_clk_genx_s cn56xxp1;
333 struct cvmx_gpio_clk_genx_s cn61xx;
334 struct cvmx_gpio_clk_genx_s cn63xx;
335 struct cvmx_gpio_clk_genx_s cn63xxp1;
336 struct cvmx_gpio_clk_genx_s cn66xx;
337 struct cvmx_gpio_clk_genx_s cn68xx;
338 struct cvmx_gpio_clk_genx_s cn68xxp1;
339 struct cvmx_gpio_clk_genx_s cnf71xx;
340 };
341 typedef union cvmx_gpio_clk_genx cvmx_gpio_clk_genx_t;
342
343 /**
344 * cvmx_gpio_clk_qlm#
345 *
346 * Notes:
347 * QLM0(A) and QLM1(B) can configured to source any of QLM0 or QLM2 as clock source.
348 * Clock speed output for different modes ...
349 *
350 * Speed With Speed with
351 * SERDES speed (Gbaud) DIV=0 (MHz) DIV=1 (MHz)
352 * **********************************************************
353 * 1.25 62.5 31.25
354 * 2.5 125 62.5
355 * 3.125 156.25 78.125
356 * 5.0 250 125
357 * 6.25 312.5 156.25
358 */
359 union cvmx_gpio_clk_qlmx {
360 uint64_t u64;
361 struct cvmx_gpio_clk_qlmx_s {
362 #ifdef __BIG_ENDIAN_BITFIELD
363 uint64_t reserved_11_63 : 53;
364 uint64_t qlm_sel : 3; /**< Selects which DLM to select from
365 x0 = select DLM0 as clock source
366 x1 = Disabled */
367 uint64_t reserved_3_7 : 5;
368 uint64_t div : 1; /**< Internal clock divider
369 0=DIV2
370 1=DIV4 */
371 uint64_t lane_sel : 2; /**< Selects which RX lane clock from QLMx to use as
372 the GPIO internal QLMx clock. The GPIO block can
373 support upto two unique clocks to send out any
374 GPIO pin as configured by $GPIO_BIT_CFG[SYNCE_SEL]
375 The clock can either be a divided by 2 or divide
376 by 4 of the selected RX lane clock. */
377 #else
378 uint64_t lane_sel : 2;
379 uint64_t div : 1;
380 uint64_t reserved_3_7 : 5;
381 uint64_t qlm_sel : 3;
382 uint64_t reserved_11_63 : 53;
383 #endif
384 } s;
385 struct cvmx_gpio_clk_qlmx_cn61xx {
386 #ifdef __BIG_ENDIAN_BITFIELD
387 uint64_t reserved_10_63 : 54;
388 uint64_t qlm_sel : 2; /**< Selects which QLM to select from
389 01 = select QLM0 as clock source
390 1x = select QLM2 as clock source
391 0 = Disabled */
392 uint64_t reserved_3_7 : 5;
393 uint64_t div : 1; /**< Internal clock divider
394 0=DIV2
395 1=DIV4 */
396 uint64_t lane_sel : 2; /**< Selects which RX lane clock from QLMx to use as
397 the GPIO internal QLMx clock. The GPIO block can
398 support upto two unique clocks to send out any
399 GPIO pin as configured by $GPIO_BIT_CFG[SYNCE_SEL]
400 The clock can either be a divided by 2 or divide
401 by 4 of the selected RX lane clock. */
402 #else
403 uint64_t lane_sel : 2;
404 uint64_t div : 1;
405 uint64_t reserved_3_7 : 5;
406 uint64_t qlm_sel : 2;
407 uint64_t reserved_10_63 : 54;
408 #endif
409 } cn61xx;
410 struct cvmx_gpio_clk_qlmx_cn63xx {
411 #ifdef __BIG_ENDIAN_BITFIELD
412 uint64_t reserved_3_63 : 61;
413 uint64_t div : 1; /**< Internal clock divider
414 0=DIV2
415 1=DIV4 */
416 uint64_t lane_sel : 2; /**< Selects which RX lane clock from QLM2 to use as
417 the GPIO internal QLMx clock. The GPIO block can
418 support upto two unique clocks to send out any
419 GPIO pin as configured by $GPIO_BIT_CFG[SYNCE_SEL]
420 The clock can either be a divided by 2 or divide
421 by 4 of the selected RX lane clock. */
422 #else
423 uint64_t lane_sel : 2;
424 uint64_t div : 1;
425 uint64_t reserved_3_63 : 61;
426 #endif
427 } cn63xx;
428 struct cvmx_gpio_clk_qlmx_cn63xx cn63xxp1;
429 struct cvmx_gpio_clk_qlmx_cn61xx cn66xx;
430 struct cvmx_gpio_clk_qlmx_s cn68xx;
431 struct cvmx_gpio_clk_qlmx_s cn68xxp1;
432 struct cvmx_gpio_clk_qlmx_cn61xx cnf71xx;
433 };
434 typedef union cvmx_gpio_clk_qlmx cvmx_gpio_clk_qlmx_t;
435
436 /**
437 * cvmx_gpio_dbg_ena
438 */
439 union cvmx_gpio_dbg_ena {
440 uint64_t u64;
441 struct cvmx_gpio_dbg_ena_s {
442 #ifdef __BIG_ENDIAN_BITFIELD
443 uint64_t reserved_21_63 : 43;
444 uint64_t dbg_ena : 21; /**< Enable the debug port to be driven on the gpio */
445 #else
446 uint64_t dbg_ena : 21;
447 uint64_t reserved_21_63 : 43;
448 #endif
449 } s;
450 struct cvmx_gpio_dbg_ena_s cn30xx;
451 struct cvmx_gpio_dbg_ena_s cn31xx;
452 struct cvmx_gpio_dbg_ena_s cn50xx;
453 };
454 typedef union cvmx_gpio_dbg_ena cvmx_gpio_dbg_ena_t;
455
456 /**
457 * cvmx_gpio_int_clr
458 *
459 * Notes:
460 * Only 16 out of 20 GPIOs support interrupt.GPIO_INT_CLR only apply to GPIO0-GPIO15.
461 *
462 */
463 union cvmx_gpio_int_clr {
464 uint64_t u64;
465 struct cvmx_gpio_int_clr_s {
466 #ifdef __BIG_ENDIAN_BITFIELD
467 uint64_t reserved_16_63 : 48;
468 uint64_t type : 16; /**< Clear the interrupt rising edge detector */
469 #else
470 uint64_t type : 16;
471 uint64_t reserved_16_63 : 48;
472 #endif
473 } s;
474 struct cvmx_gpio_int_clr_s cn30xx;
475 struct cvmx_gpio_int_clr_s cn31xx;
476 struct cvmx_gpio_int_clr_s cn38xx;
477 struct cvmx_gpio_int_clr_s cn38xxp2;
478 struct cvmx_gpio_int_clr_s cn50xx;
479 struct cvmx_gpio_int_clr_s cn52xx;
480 struct cvmx_gpio_int_clr_s cn52xxp1;
481 struct cvmx_gpio_int_clr_s cn56xx;
482 struct cvmx_gpio_int_clr_s cn56xxp1;
483 struct cvmx_gpio_int_clr_s cn58xx;
484 struct cvmx_gpio_int_clr_s cn58xxp1;
485 struct cvmx_gpio_int_clr_s cn61xx;
486 struct cvmx_gpio_int_clr_s cn63xx;
487 struct cvmx_gpio_int_clr_s cn63xxp1;
488 struct cvmx_gpio_int_clr_s cn66xx;
489 struct cvmx_gpio_int_clr_s cn68xx;
490 struct cvmx_gpio_int_clr_s cn68xxp1;
491 struct cvmx_gpio_int_clr_s cnf71xx;
492 };
493 typedef union cvmx_gpio_int_clr cvmx_gpio_int_clr_t;
494
495 /**
496 * cvmx_gpio_multi_cast
497 *
498 * Notes:
499 * GPIO<7:4> have the option of operating in GPIO Interrupt Multicast mode. In
500 * this mode, the PP GPIO interrupts (CIU_INT<0-7>_SUM0/CIU_INT<0-3>_SUM4[GPIO<7:4>] values are
501 * stored per cnMIPS core.
502 * For GPIO<7:4> (x=4-7):
503 * When GPIO_MULTI_CAST[EN] = 1:
504 * When GPIO_BIT_CFGx[INT_EN]==1 & GPIO_BIT_CFGx[INT_TYPE]==1 (edge detection and interrupt enabled):
505 * * Reads to CIU_INT<0-7>_SUM0/<0-3>_SUM4[GPIO<x>] will return a unique interrupt state per
506 * cnMIPS core.
507 * * Reads to CIU_INT32/33_SUM0/4[GPIO<x>] will return the common GPIO<x>
508 * interrupt state.
509 * * Write of '1' to CIU_INT<0-7>_SUM0/<0-3>_SUM4[GPIO<x>] will clear the individual
510 * interrupt associated with the cnMIPS core.
511 * * Write of '1' to CIU_INT32/33_SUM0/4[GPIO<x>] will clear the common GPIO<x>
512 * interrupt state.
513 * * Write of '1' to GPIO_INT_CLR[TYPE<x>] will clear all
514 * CIU_INT*_SUM0/4[GPIO<x>] state across all cnMIPS cores and common GPIO<x> interrupt states.
515 * When GPIO_BIT_CFGx[INT_EN]==0 or GPIO_BIT_CFGx[INT_TYPE]==0,
516 * * either leveled interrupt or interrupt not enabled, write of '1' to CIU_INT*_SUM0/4[GPIO<x>]
517 * will have no effects.
518 * When GPIO_MULTI_CAST[EN] = 0:
519 * * Write of '1' to CIU_INT_SUM0/4[GPIO<x>] will have no effects, as this field is RO,
520 * backward compatible with o63.
521 * When GPIO_BIT_CFGx[INT_EN]==1 & GPIO_BIT_CFGx[INT_TYPE]==1 (edge detection and interrupt enabled):
522 * * Reads to CIU_INT*_SUM0/4[GPIO<x>] will return the common GPIO<X> interrupt state.
523 * * Write of '1' to GPIO_INT_CLR[TYPE<x>] will clear all
524 * CIU_INT*_SUM0/4[GPIO<x>] state across all cnMIPS cores and common GPIO<x> interrupt states.
525 * When GPIO_BIT_CFGx[INT_EN]==0 or GPIO_BIT_CFGx[INT_TYPE]==0,
526 * * either leveled interrupt or interrupt not enabled, write of '1' to CIU_INT*_SUM0/4[GPIO<x>]
527 * will have no effects.
528 *
529 * GPIO<15:8> and GPIO<3:0> will never be in multicast mode as those don't have per cnMIPS capabilities.
530 * For GPIO<y> (y=0-3,8-15):
531 * When GPIO_BIT_CFGx[INT_EN]==1 & GPIO_BIT_CFGx[INT_TYPE]==1 (edge detection and interrupt enabled):
532 * * Reads to CIU_INT*_SUM0/4[GPIO<y>] will return the common GPIO<y> interrupt state.
533 * * Write of '1' to GPIO_INT_CLR[TYPE<y>] will clear all CIU_INT*_SUM0/4[GPIO<y>] common GPIO<y>
534 * interrupt states.
535 * When GPIO_MULTI_CAST[EN] = 1:
536 * * Write of '1' to CIU_INT*_SUM0/4[GPIO<y>] will clear the common GPIO<y> interrupt state.
537 * When GPIO_MULTI_CAST[EN] = 0:
538 * * Write of '1' to CIU_INT*_SUM0/4[GPIO<y>] has no effect, as this field is RO,
539 * backward compatible to o63.
540 * When GPIO_BIT_CFGx[INT_EN]==0 or GPIO_BIT_CFGx[INT_TYPE]==0,
541 * * either leveled interrupt or interrupt not enabled, write of '1' to CIU_INT*_SUM0/4[GPIO<y>]
542 * will have no effects.
543 *
544 * Whenever there is mode change, (GPIO_BIT_CFGx[INT_EN] or GPIO_BIT_CFGx[INT_TYPE] or GPIO_MULTI_CAST[EN])
545 * software needs to write to $GPIO_INT_CLR to clear up all pending/stale interrupts.
546 */
547 union cvmx_gpio_multi_cast {
548 uint64_t u64;
549 struct cvmx_gpio_multi_cast_s {
550 #ifdef __BIG_ENDIAN_BITFIELD
551 uint64_t reserved_1_63 : 63;
552 uint64_t en : 1; /**< Enable GPIO Interrupt Multicast mode
553 When EN is set, GPIO<7:4> will function in
554 multicast mode allowing these four GPIOs to
555 interrupt multi-cores.
556 Multicast functionality allows the GPIO to exist
557 as per cnMIPS interrupts as opposed to a global
558 interrupt. */
559 #else
560 uint64_t en : 1;
561 uint64_t reserved_1_63 : 63;
562 #endif
563 } s;
564 struct cvmx_gpio_multi_cast_s cn61xx;
565 struct cvmx_gpio_multi_cast_s cnf71xx;
566 };
567 typedef union cvmx_gpio_multi_cast cvmx_gpio_multi_cast_t;
568
569 /**
570 * cvmx_gpio_pin_ena
571 *
572 * Notes:
573 * GPIO0-GPIO17 has dedicated pins.
574 * GPIO18 share pin with UART (UART0_CTS_L/GPIO_18), GPIO18 enabled when $GPIO_PIN_ENA[ENA18]=1
575 * GPIO19 share pin with UART (UART1_CTS_L/GPIO_19), GPIO18 enabled when $GPIO_PIN_ENA[ENA19]=1
576 */
577 union cvmx_gpio_pin_ena {
578 uint64_t u64;
579 struct cvmx_gpio_pin_ena_s {
580 #ifdef __BIG_ENDIAN_BITFIELD
581 uint64_t reserved_20_63 : 44;
582 uint64_t ena19 : 1; /**< If 0, UART1_CTS_L/GPIO_19 pin is UART pin
583 If 1, UART1_CTS_L/GPIO_19 pin is GPIO19 pin */
584 uint64_t ena18 : 1; /**< If 0, UART0_CTS_L/GPIO_18 pin is UART pin
585 If 1, UART0_CTS_L/GPIO_18 pin is GPIO18 pin */
586 uint64_t reserved_0_17 : 18;
587 #else
588 uint64_t reserved_0_17 : 18;
589 uint64_t ena18 : 1;
590 uint64_t ena19 : 1;
591 uint64_t reserved_20_63 : 44;
592 #endif
593 } s;
594 struct cvmx_gpio_pin_ena_s cn66xx;
595 };
596 typedef union cvmx_gpio_pin_ena cvmx_gpio_pin_ena_t;
597
598 /**
599 * cvmx_gpio_rx_dat
600 */
601 union cvmx_gpio_rx_dat {
602 uint64_t u64;
603 struct cvmx_gpio_rx_dat_s {
604 #ifdef __BIG_ENDIAN_BITFIELD
605 uint64_t reserved_24_63 : 40;
606 uint64_t dat : 24; /**< GPIO Read Data */
607 #else
608 uint64_t dat : 24;
609 uint64_t reserved_24_63 : 40;
610 #endif
611 } s;
612 struct cvmx_gpio_rx_dat_s cn30xx;
613 struct cvmx_gpio_rx_dat_s cn31xx;
614 struct cvmx_gpio_rx_dat_cn38xx {
615 #ifdef __BIG_ENDIAN_BITFIELD
616 uint64_t reserved_16_63 : 48;
617 uint64_t dat : 16; /**< GPIO Read Data */
618 #else
619 uint64_t dat : 16;
620 uint64_t reserved_16_63 : 48;
621 #endif
622 } cn38xx;
623 struct cvmx_gpio_rx_dat_cn38xx cn38xxp2;
624 struct cvmx_gpio_rx_dat_s cn50xx;
625 struct cvmx_gpio_rx_dat_cn38xx cn52xx;
626 struct cvmx_gpio_rx_dat_cn38xx cn52xxp1;
627 struct cvmx_gpio_rx_dat_cn38xx cn56xx;
628 struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
629 struct cvmx_gpio_rx_dat_cn38xx cn58xx;
630 struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
631 struct cvmx_gpio_rx_dat_cn61xx {
632 #ifdef __BIG_ENDIAN_BITFIELD
633 uint64_t reserved_20_63 : 44;
634 uint64_t dat : 20; /**< GPIO Read Data */
635 #else
636 uint64_t dat : 20;
637 uint64_t reserved_20_63 : 44;
638 #endif
639 } cn61xx;
640 struct cvmx_gpio_rx_dat_cn38xx cn63xx;
641 struct cvmx_gpio_rx_dat_cn38xx cn63xxp1;
642 struct cvmx_gpio_rx_dat_cn61xx cn66xx;
643 struct cvmx_gpio_rx_dat_cn38xx cn68xx;
644 struct cvmx_gpio_rx_dat_cn38xx cn68xxp1;
645 struct cvmx_gpio_rx_dat_cn61xx cnf71xx;
646 };
647 typedef union cvmx_gpio_rx_dat cvmx_gpio_rx_dat_t;
648
649 /**
650 * cvmx_gpio_tim_ctl
651 */
652 union cvmx_gpio_tim_ctl {
653 uint64_t u64;
654 struct cvmx_gpio_tim_ctl_s {
655 #ifdef __BIG_ENDIAN_BITFIELD
656 uint64_t reserved_4_63 : 60;
657 uint64_t sel : 4; /**< Selects the GPIO pin to route to TIM */
658 #else
659 uint64_t sel : 4;
660 uint64_t reserved_4_63 : 60;
661 #endif
662 } s;
663 struct cvmx_gpio_tim_ctl_s cn68xx;
664 struct cvmx_gpio_tim_ctl_s cn68xxp1;
665 };
666 typedef union cvmx_gpio_tim_ctl cvmx_gpio_tim_ctl_t;
667
668 /**
669 * cvmx_gpio_tx_clr
670 */
671 union cvmx_gpio_tx_clr {
672 uint64_t u64;
673 struct cvmx_gpio_tx_clr_s {
674 #ifdef __BIG_ENDIAN_BITFIELD
675 uint64_t reserved_24_63 : 40;
676 uint64_t clr : 24; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
677 to '0'. When read, CLR returns the GPIO_TX_DAT
678 storage. */
679 #else
680 uint64_t clr : 24;
681 uint64_t reserved_24_63 : 40;
682 #endif
683 } s;
684 struct cvmx_gpio_tx_clr_s cn30xx;
685 struct cvmx_gpio_tx_clr_s cn31xx;
686 struct cvmx_gpio_tx_clr_cn38xx {
687 #ifdef __BIG_ENDIAN_BITFIELD
688 uint64_t reserved_16_63 : 48;
689 uint64_t clr : 16; /**< Bit mask to indicate which bits to drive to '0'. */
690 #else
691 uint64_t clr : 16;
692 uint64_t reserved_16_63 : 48;
693 #endif
694 } cn38xx;
695 struct cvmx_gpio_tx_clr_cn38xx cn38xxp2;
696 struct cvmx_gpio_tx_clr_s cn50xx;
697 struct cvmx_gpio_tx_clr_cn38xx cn52xx;
698 struct cvmx_gpio_tx_clr_cn38xx cn52xxp1;
699 struct cvmx_gpio_tx_clr_cn38xx cn56xx;
700 struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
701 struct cvmx_gpio_tx_clr_cn38xx cn58xx;
702 struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
703 struct cvmx_gpio_tx_clr_cn61xx {
704 #ifdef __BIG_ENDIAN_BITFIELD
705 uint64_t reserved_20_63 : 44;
706 uint64_t clr : 20; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
707 to '0'. When read, CLR returns the GPIO_TX_DAT
708 storage. */
709 #else
710 uint64_t clr : 20;
711 uint64_t reserved_20_63 : 44;
712 #endif
713 } cn61xx;
714 struct cvmx_gpio_tx_clr_cn38xx cn63xx;
715 struct cvmx_gpio_tx_clr_cn38xx cn63xxp1;
716 struct cvmx_gpio_tx_clr_cn61xx cn66xx;
717 struct cvmx_gpio_tx_clr_cn38xx cn68xx;
718 struct cvmx_gpio_tx_clr_cn38xx cn68xxp1;
719 struct cvmx_gpio_tx_clr_cn61xx cnf71xx;
720 };
721 typedef union cvmx_gpio_tx_clr cvmx_gpio_tx_clr_t;
722
723 /**
724 * cvmx_gpio_tx_set
725 */
726 union cvmx_gpio_tx_set {
727 uint64_t u64;
728 struct cvmx_gpio_tx_set_s {
729 #ifdef __BIG_ENDIAN_BITFIELD
730 uint64_t reserved_24_63 : 40;
731 uint64_t set : 24; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
732 to '1'. When read, SET returns the GPIO_TX_DAT
733 storage. */
734 #else
735 uint64_t set : 24;
736 uint64_t reserved_24_63 : 40;
737 #endif
738 } s;
739 struct cvmx_gpio_tx_set_s cn30xx;
740 struct cvmx_gpio_tx_set_s cn31xx;
741 struct cvmx_gpio_tx_set_cn38xx {
742 #ifdef __BIG_ENDIAN_BITFIELD
743 uint64_t reserved_16_63 : 48;
744 uint64_t set : 16; /**< Bit mask to indicate which bits to drive to '1'. */
745 #else
746 uint64_t set : 16;
747 uint64_t reserved_16_63 : 48;
748 #endif
749 } cn38xx;
750 struct cvmx_gpio_tx_set_cn38xx cn38xxp2;
751 struct cvmx_gpio_tx_set_s cn50xx;
752 struct cvmx_gpio_tx_set_cn38xx cn52xx;
753 struct cvmx_gpio_tx_set_cn38xx cn52xxp1;
754 struct cvmx_gpio_tx_set_cn38xx cn56xx;
755 struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
756 struct cvmx_gpio_tx_set_cn38xx cn58xx;
757 struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
758 struct cvmx_gpio_tx_set_cn61xx {
759 #ifdef __BIG_ENDIAN_BITFIELD
760 uint64_t reserved_20_63 : 44;
761 uint64_t set : 20; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
762 to '1'. When read, SET returns the GPIO_TX_DAT
763 storage. */
764 #else
765 uint64_t set : 20;
766 uint64_t reserved_20_63 : 44;
767 #endif
768 } cn61xx;
769 struct cvmx_gpio_tx_set_cn38xx cn63xx;
770 struct cvmx_gpio_tx_set_cn38xx cn63xxp1;
771 struct cvmx_gpio_tx_set_cn61xx cn66xx;
772 struct cvmx_gpio_tx_set_cn38xx cn68xx;
773 struct cvmx_gpio_tx_set_cn38xx cn68xxp1;
774 struct cvmx_gpio_tx_set_cn61xx cnf71xx;
775 };
776 typedef union cvmx_gpio_tx_set cvmx_gpio_tx_set_t;
777
778 /**
779 * cvmx_gpio_xbit_cfg#
780 *
781 * Notes:
782 * Only first 16 GPIO pins can introduce interrupts, GPIO_XBIT_CFG16(17,18,19)[INT_EN] and [INT_TYPE]
783 * will not be used, read out always zero.
784 */
785 union cvmx_gpio_xbit_cfgx {
786 uint64_t u64;
787 struct cvmx_gpio_xbit_cfgx_s {
788 #ifdef __BIG_ENDIAN_BITFIELD
789 uint64_t reserved_17_63 : 47;
790 uint64_t synce_sel : 2; /**< Selects the QLM clock output
791 x0=Normal GPIO output
792 01=GPIO QLM clock selected by CSR GPIO_CLK_QLM0
793 11=GPIO QLM clock selected by CSR GPIO_CLK_QLM1 */
794 uint64_t clk_gen : 1; /**< When TX_OE is set, GPIO pin becomes a clock */
795 uint64_t clk_sel : 2; /**< Selects which of the 4 GPIO clock generators */
796 uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */
797 uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */
798 uint64_t int_type : 1; /**< Type of interrupt
799 0 = level (default)
800 1 = rising edge */
801 uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */
802 uint64_t rx_xor : 1; /**< Invert the GPIO pin */
803 uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */
804 #else
805 uint64_t tx_oe : 1;
806 uint64_t rx_xor : 1;
807 uint64_t int_en : 1;
808 uint64_t int_type : 1;
809 uint64_t fil_cnt : 4;
810 uint64_t fil_sel : 4;
811 uint64_t clk_sel : 2;
812 uint64_t clk_gen : 1;
813 uint64_t synce_sel : 2;
814 uint64_t reserved_17_63 : 47;
815 #endif
816 } s;
817 struct cvmx_gpio_xbit_cfgx_cn30xx {
818 #ifdef __BIG_ENDIAN_BITFIELD
819 uint64_t reserved_12_63 : 52;
820 uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */
821 uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */
822 uint64_t reserved_2_3 : 2;
823 uint64_t rx_xor : 1; /**< Invert the GPIO pin */
824 uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */
825 #else
826 uint64_t tx_oe : 1;
827 uint64_t rx_xor : 1;
828 uint64_t reserved_2_3 : 2;
829 uint64_t fil_cnt : 4;
830 uint64_t fil_sel : 4;
831 uint64_t reserved_12_63 : 52;
832 #endif
833 } cn30xx;
834 struct cvmx_gpio_xbit_cfgx_cn30xx cn31xx;
835 struct cvmx_gpio_xbit_cfgx_cn30xx cn50xx;
836 struct cvmx_gpio_xbit_cfgx_s cn61xx;
837 struct cvmx_gpio_xbit_cfgx_s cn66xx;
838 struct cvmx_gpio_xbit_cfgx_s cnf71xx;
839 };
840 typedef union cvmx_gpio_xbit_cfgx cvmx_gpio_xbit_cfgx_t;
841
842 #endif
843