1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that ARM uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 17 18 #include "MCTargetDesc/ARMBaseInfo.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/ADT/StringRef.h" 21 #include "llvm/CodeGen/CallingConvLower.h" 22 #include "llvm/CodeGen/ISDOpcodes.h" 23 #include "llvm/CodeGen/MachineFunction.h" 24 #include "llvm/CodeGen/SelectionDAGNodes.h" 25 #include "llvm/CodeGen/TargetLowering.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/IR/Attributes.h" 28 #include "llvm/IR/CallingConv.h" 29 #include "llvm/IR/Function.h" 30 #include "llvm/IR/IRBuilder.h" 31 #include "llvm/IR/InlineAsm.h" 32 #include "llvm/Support/CodeGen.h" 33 #include "llvm/Support/MachineValueType.h" 34 #include <utility> 35 36 namespace llvm { 37 38 class ARMSubtarget; 39 class DataLayout; 40 class FastISel; 41 class FunctionLoweringInfo; 42 class GlobalValue; 43 class InstrItineraryData; 44 class Instruction; 45 class MachineBasicBlock; 46 class MachineInstr; 47 class SelectionDAG; 48 class TargetLibraryInfo; 49 class TargetMachine; 50 class TargetRegisterInfo; 51 class VectorType; 52 53 namespace ARMISD { 54 55 // ARM Specific DAG Nodes 56 enum NodeType : unsigned { 57 // Start the numbering where the builtin ops and target ops leave off. 58 FIRST_NUMBER = ISD::BUILTIN_OP_END, 59 60 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 61 // TargetExternalSymbol, and TargetGlobalAddress. 62 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in 63 // PIC mode. 64 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 65 66 // Add pseudo op to model memcpy for struct byval. 67 COPY_STRUCT_BYVAL, 68 69 CALL, // Function call. 70 CALL_PRED, // Function call that's predicable. 71 CALL_NOLINK, // Function call with branch not branch-and-link. 72 BRCOND, // Conditional branch. 73 BR_JT, // Jumptable branch. 74 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 75 RET_FLAG, // Return with a flag operand. 76 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand. 77 78 PIC_ADD, // Add with a PC operand and a PIC label. 79 80 CMP, // ARM compare instructions. 81 CMN, // ARM CMN instructions. 82 CMPZ, // ARM compare that sets only Z flag. 83 CMPFP, // ARM VFP compare instruction, sets FPSCR. 84 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 85 FMSTAT, // ARM fmstat instruction. 86 87 CMOV, // ARM conditional move instructions. 88 SUBS, // Flag-setting subtraction. 89 90 SSAT, // Signed saturation 91 USAT, // Unsigned saturation 92 93 BCC_i64, 94 95 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 96 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 97 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 98 99 ADDC, // Add with carry 100 ADDE, // Add using carry 101 SUBC, // Sub with carry 102 SUBE, // Sub using carry 103 104 VMOVRRD, // double to two gprs. 105 VMOVDRR, // Two gprs to double. 106 VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr 107 108 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 109 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 110 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch. 111 112 TC_RETURN, // Tail call return pseudo. 113 114 THREAD_POINTER, 115 116 DYN_ALLOC, // Dynamic allocation on the stack. 117 118 MEMBARRIER_MCR, // Memory barrier (MCR) 119 120 PRELOAD, // Preload 121 122 WIN__CHKSTK, // Windows' __chkstk call to do stack probing. 123 WIN__DBZCHK, // Windows' divide by zero check 124 125 VCEQ, // Vector compare equal. 126 VCEQZ, // Vector compare equal to zero. 127 VCGE, // Vector compare greater than or equal. 128 VCGEZ, // Vector compare greater than or equal to zero. 129 VCLEZ, // Vector compare less than or equal to zero. 130 VCGEU, // Vector compare unsigned greater than or equal. 131 VCGT, // Vector compare greater than. 132 VCGTZ, // Vector compare greater than zero. 133 VCLTZ, // Vector compare less than zero. 134 VCGTU, // Vector compare unsigned greater than. 135 VTST, // Vector test bits. 136 137 // Vector shift by immediate: 138 VSHL, // ...left 139 VSHRs, // ...right (signed) 140 VSHRu, // ...right (unsigned) 141 142 // Vector rounding shift by immediate: 143 VRSHRs, // ...right (signed) 144 VRSHRu, // ...right (unsigned) 145 VRSHRN, // ...right narrow 146 147 // Vector saturating shift by immediate: 148 VQSHLs, // ...left (signed) 149 VQSHLu, // ...left (unsigned) 150 VQSHLsu, // ...left (signed to unsigned) 151 VQSHRNs, // ...right narrow (signed) 152 VQSHRNu, // ...right narrow (unsigned) 153 VQSHRNsu, // ...right narrow (signed to unsigned) 154 155 // Vector saturating rounding shift by immediate: 156 VQRSHRNs, // ...right narrow (signed) 157 VQRSHRNu, // ...right narrow (unsigned) 158 VQRSHRNsu, // ...right narrow (signed to unsigned) 159 160 // Vector shift and insert: 161 VSLI, // ...left 162 VSRI, // ...right 163 164 // Vector get lane (VMOV scalar to ARM core register) 165 // (These are used for 8- and 16-bit element types only.) 166 VGETLANEu, // zero-extend vector extract element 167 VGETLANEs, // sign-extend vector extract element 168 169 // Vector move immediate and move negated immediate: 170 VMOVIMM, 171 VMVNIMM, 172 173 // Vector move f32 immediate: 174 VMOVFPIMM, 175 176 // Move H <-> R, clearing top 16 bits 177 VMOVrh, 178 VMOVhr, 179 180 // Vector duplicate: 181 VDUP, 182 VDUPLANE, 183 184 // Vector shuffles: 185 VEXT, // extract 186 VREV64, // reverse elements within 64-bit doublewords 187 VREV32, // reverse elements within 32-bit words 188 VREV16, // reverse elements within 16-bit halfwords 189 VZIP, // zip (interleave) 190 VUZP, // unzip (deinterleave) 191 VTRN, // transpose 192 VTBL1, // 1-register shuffle with mask 193 VTBL2, // 2-register shuffle with mask 194 195 // Vector multiply long: 196 VMULLs, // ...signed 197 VMULLu, // ...unsigned 198 199 SMULWB, // Signed multiply word by half word, bottom 200 SMULWT, // Signed multiply word by half word, top 201 UMLAL, // 64bit Unsigned Accumulate Multiply 202 SMLAL, // 64bit Signed Accumulate Multiply 203 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply 204 SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16 205 SMLALBT, // 64-bit signed accumulate multiply bottom, top 16 206 SMLALTB, // 64-bit signed accumulate multiply top, bottom 16 207 SMLALTT, // 64-bit signed accumulate multiply top, top 16 208 SMLALD, // Signed multiply accumulate long dual 209 SMLALDX, // Signed multiply accumulate long dual exchange 210 SMLSLD, // Signed multiply subtract long dual 211 SMLSLDX, // Signed multiply subtract long dual exchange 212 SMMLAR, // Signed multiply long, round and add 213 SMMLSR, // Signed multiply long, subtract and round 214 215 // Operands of the standard BUILD_VECTOR node are not legalized, which 216 // is fine if BUILD_VECTORs are always lowered to shuffles or other 217 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 218 // operands need to be legalized. Define an ARM-specific version of 219 // BUILD_VECTOR for this purpose. 220 BUILD_VECTOR, 221 222 // Bit-field insert 223 BFI, 224 225 // Vector OR with immediate 226 VORRIMM, 227 // Vector AND with NOT of immediate 228 VBICIMM, 229 230 // Vector bitwise select 231 VBSL, 232 233 // Pseudo-instruction representing a memory copy using ldm/stm 234 // instructions. 235 MEMCPY, 236 237 // Vector load N-element structure to all lanes: 238 VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, 239 VLD2DUP, 240 VLD3DUP, 241 VLD4DUP, 242 243 // NEON loads with post-increment base updates: 244 VLD1_UPD, 245 VLD2_UPD, 246 VLD3_UPD, 247 VLD4_UPD, 248 VLD2LN_UPD, 249 VLD3LN_UPD, 250 VLD4LN_UPD, 251 VLD1DUP_UPD, 252 VLD2DUP_UPD, 253 VLD3DUP_UPD, 254 VLD4DUP_UPD, 255 256 // NEON stores with post-increment base updates: 257 VST1_UPD, 258 VST2_UPD, 259 VST3_UPD, 260 VST4_UPD, 261 VST2LN_UPD, 262 VST3LN_UPD, 263 VST4LN_UPD 264 }; 265 266 } // end namespace ARMISD 267 268 /// Define some predicates that are used for node matching. 269 namespace ARM { 270 271 bool isBitFieldInvertedMask(unsigned v); 272 273 } // end namespace ARM 274 275 //===--------------------------------------------------------------------===// 276 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 277 278 class ARMTargetLowering : public TargetLowering { 279 public: 280 explicit ARMTargetLowering(const TargetMachine &TM, 281 const ARMSubtarget &STI); 282 283 unsigned getJumpTableEncoding() const override; 284 bool useSoftFloat() const override; 285 286 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 287 288 /// ReplaceNodeResults - Replace the results of node with an illegal result 289 /// type with new values built out of custom code. 290 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 291 SelectionDAG &DAG) const override; 292 293 const char *getTargetNodeName(unsigned Opcode) const override; 294 isSelectSupported(SelectSupportKind Kind)295 bool isSelectSupported(SelectSupportKind Kind) const override { 296 // ARM does not support scalar condition selects on vectors. 297 return (Kind != ScalarCondVectorVal); 298 } 299 300 bool isReadOnly(const GlobalValue *GV) const; 301 302 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 303 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 304 EVT VT) const override; 305 306 MachineBasicBlock * 307 EmitInstrWithCustomInserter(MachineInstr &MI, 308 MachineBasicBlock *MBB) const override; 309 310 void AdjustInstrPostInstrSelection(MachineInstr &MI, 311 SDNode *Node) const override; 312 313 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; 314 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const; 315 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const; 316 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 317 318 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override; 319 320 /// allowsMisalignedMemoryAccesses - Returns true if the target allows 321 /// unaligned memory accesses of the specified type. Returns whether it 322 /// is "fast" by reference in the second argument. 323 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, 324 unsigned Align, 325 bool *Fast) const override; 326 327 EVT getOptimalMemOpType(uint64_t Size, 328 unsigned DstAlign, unsigned SrcAlign, 329 bool IsMemset, bool ZeroMemset, 330 bool MemcpyStrSrc, 331 MachineFunction &MF) const override; 332 333 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 334 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 335 bool isZExtFree(SDValue Val, EVT VT2) const override; 336 bool isFNegFree(EVT VT) const override; 337 338 bool isVectorLoadExtDesirable(SDValue ExtVal) const override; 339 340 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override; 341 342 343 /// isLegalAddressingMode - Return true if the addressing mode represented 344 /// by AM is legal for this target, for a load/store of the specified type. 345 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 346 Type *Ty, unsigned AS, 347 Instruction *I = nullptr) const override; 348 349 /// getScalingFactorCost - Return the cost of the scaling used in 350 /// addressing mode represented by AM. 351 /// If the AM is supported, the return value must be >= 0. 352 /// If the AM is not supported, the return value must be negative. 353 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, 354 unsigned AS) const override; 355 356 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 357 358 /// Returns true if the addresing mode representing by AM is legal 359 /// for the Thumb1 target, for a load/store of the specified type. 360 bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 361 362 /// isLegalICmpImmediate - Return true if the specified immediate is legal 363 /// icmp immediate, that is the target has icmp instructions which can 364 /// compare a register against the immediate without having to materialize 365 /// the immediate into a register. 366 bool isLegalICmpImmediate(int64_t Imm) const override; 367 368 /// isLegalAddImmediate - Return true if the specified immediate is legal 369 /// add immediate, that is the target has add instructions which can 370 /// add a register and the immediate without having to materialize 371 /// the immediate into a register. 372 bool isLegalAddImmediate(int64_t Imm) const override; 373 374 /// getPreIndexedAddressParts - returns true by value, base pointer and 375 /// offset pointer and addressing mode by reference if the node's address 376 /// can be legally represented as pre-indexed load / store address. 377 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 378 ISD::MemIndexedMode &AM, 379 SelectionDAG &DAG) const override; 380 381 /// getPostIndexedAddressParts - returns true by value, base pointer and 382 /// offset pointer and addressing mode by reference if this node can be 383 /// combined with a load / store to form a post-indexed load / store. 384 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 385 SDValue &Offset, ISD::MemIndexedMode &AM, 386 SelectionDAG &DAG) const override; 387 388 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 389 const APInt &DemandedElts, 390 const SelectionDAG &DAG, 391 unsigned Depth) const override; 392 393 bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded, 394 TargetLoweringOpt &TLO) const override; 395 396 397 bool ExpandInlineAsm(CallInst *CI) const override; 398 399 ConstraintType getConstraintType(StringRef Constraint) const override; 400 401 /// Examine constraint string and operand type and determine a weight value. 402 /// The operand object must already have been set up with the operand type. 403 ConstraintWeight getSingleConstraintMatchWeight( 404 AsmOperandInfo &info, const char *constraint) const override; 405 406 std::pair<unsigned, const TargetRegisterClass *> 407 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 408 StringRef Constraint, MVT VT) const override; 409 410 const char *LowerXConstraint(EVT ConstraintVT) const override; 411 412 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 413 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 414 /// true it means one of the asm constraint of the inline asm instruction 415 /// being processed is 'm'. 416 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 417 std::vector<SDValue> &Ops, 418 SelectionDAG &DAG) const override; 419 420 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode)421 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 422 if (ConstraintCode == "Q") 423 return InlineAsm::Constraint_Q; 424 else if (ConstraintCode == "o") 425 return InlineAsm::Constraint_o; 426 else if (ConstraintCode.size() == 2) { 427 if (ConstraintCode[0] == 'U') { 428 switch(ConstraintCode[1]) { 429 default: 430 break; 431 case 'm': 432 return InlineAsm::Constraint_Um; 433 case 'n': 434 return InlineAsm::Constraint_Un; 435 case 'q': 436 return InlineAsm::Constraint_Uq; 437 case 's': 438 return InlineAsm::Constraint_Us; 439 case 't': 440 return InlineAsm::Constraint_Ut; 441 case 'v': 442 return InlineAsm::Constraint_Uv; 443 case 'y': 444 return InlineAsm::Constraint_Uy; 445 } 446 } 447 } 448 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 449 } 450 getSubtarget()451 const ARMSubtarget* getSubtarget() const { 452 return Subtarget; 453 } 454 455 /// getRegClassFor - Return the register class that should be used for the 456 /// specified value type. 457 const TargetRegisterClass *getRegClassFor(MVT VT) const override; 458 459 /// Returns true if a cast between SrcAS and DestAS is a noop. isNoopAddrSpaceCast(unsigned SrcAS,unsigned DestAS)460 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { 461 // Addrspacecasts are always noops. 462 return true; 463 } 464 465 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, 466 unsigned &PrefAlign) const override; 467 468 /// createFastISel - This method returns a target specific FastISel object, 469 /// or null if the target does not support "fast" ISel. 470 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 471 const TargetLibraryInfo *libInfo) const override; 472 473 Sched::Preference getSchedulingPreference(SDNode *N) const override; 474 475 bool 476 isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 477 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 478 479 /// isFPImmLegal - Returns true if the target can instruction select the 480 /// specified FP immediate natively. If false, the legalizer will 481 /// materialize the FP immediate as a load from a constant pool. 482 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 483 484 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 485 const CallInst &I, 486 MachineFunction &MF, 487 unsigned Intrinsic) const override; 488 489 /// Returns true if it is beneficial to convert a load of a constant 490 /// to just the constant itself. 491 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 492 Type *Ty) const override; 493 494 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type 495 /// with this index. 496 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 497 unsigned Index) const override; 498 499 /// Returns true if an argument of type Ty needs to be passed in a 500 /// contiguous block of registers in calling convention CallConv. 501 bool functionArgumentNeedsConsecutiveRegisters( 502 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override; 503 504 /// If a physical register, this returns the register that receives the 505 /// exception address on entry to an EH pad. 506 unsigned 507 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 508 509 /// If a physical register, this returns the register that receives the 510 /// exception typeid on entry to a landing pad. 511 unsigned 512 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 513 514 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const; 515 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr, 516 AtomicOrdering Ord) const override; 517 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val, 518 Value *Addr, AtomicOrdering Ord) const override; 519 520 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override; 521 522 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, 523 AtomicOrdering Ord) const override; 524 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, 525 AtomicOrdering Ord) const override; 526 getMaxSupportedInterleaveFactor()527 unsigned getMaxSupportedInterleaveFactor() const override { return 4; } 528 529 bool lowerInterleavedLoad(LoadInst *LI, 530 ArrayRef<ShuffleVectorInst *> Shuffles, 531 ArrayRef<unsigned> Indices, 532 unsigned Factor) const override; 533 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, 534 unsigned Factor) const override; 535 536 bool shouldInsertFencesForAtomic(const Instruction *I) const override; 537 TargetLoweringBase::AtomicExpansionKind 538 shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 539 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 540 TargetLoweringBase::AtomicExpansionKind 541 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 542 TargetLoweringBase::AtomicExpansionKind 543 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 544 545 bool useLoadStackGuardNode() const override; 546 547 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, 548 unsigned &Cost) const override; 549 canMergeStoresTo(unsigned AddressSpace,EVT MemVT,const SelectionDAG & DAG)550 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, 551 const SelectionDAG &DAG) const override { 552 // Do not merge to larger than i32. 553 return (MemVT.getSizeInBits() <= 32); 554 } 555 556 bool isCheapToSpeculateCttz() const override; 557 bool isCheapToSpeculateCtlz() const override; 558 convertSetCCLogicToBitwiseLogic(EVT VT)559 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 560 return VT.isScalarInteger(); 561 } 562 supportSwiftError()563 bool supportSwiftError() const override { 564 return true; 565 } 566 hasStandaloneRem(EVT VT)567 bool hasStandaloneRem(EVT VT) const override { 568 return HasStandaloneRem; 569 } 570 571 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const; 572 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const; 573 574 /// Returns true if \p VecTy is a legal interleaved access type. This 575 /// function checks the vector element type and the overall width of the 576 /// vector. 577 bool isLegalInterleavedAccessType(VectorType *VecTy, 578 const DataLayout &DL) const; 579 580 bool alignLoopsWithOptSize() const override; 581 582 /// Returns the number of interleaved accesses that will be generated when 583 /// lowering accesses of the given type. 584 unsigned getNumInterleavedAccesses(VectorType *VecTy, 585 const DataLayout &DL) const; 586 587 void finalizeLowering(MachineFunction &MF) const override; 588 589 /// Return the correct alignment for the current calling convention. 590 unsigned getABIAlignmentForCallingConv(Type *ArgTy, 591 DataLayout DL) const override; 592 593 bool isDesirableToCommuteWithShift(const SDNode *N, 594 CombineLevel Level) const override; 595 596 bool shouldFoldShiftPairToMask(const SDNode *N, 597 CombineLevel Level) const override; 598 protected: 599 std::pair<const TargetRegisterClass *, uint8_t> 600 findRepresentativeClass(const TargetRegisterInfo *TRI, 601 MVT VT) const override; 602 603 private: 604 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 605 /// make the right decision when generating code for different targets. 606 const ARMSubtarget *Subtarget; 607 608 const TargetRegisterInfo *RegInfo; 609 610 const InstrItineraryData *Itins; 611 612 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 613 unsigned ARMPCLabelIndex; 614 615 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper 616 // check. 617 bool InsertFencesForAtomic; 618 619 bool HasStandaloneRem = true; 620 621 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT); 622 void addDRTypeForNEON(MVT VT); 623 void addQRTypeForNEON(MVT VT); 624 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const; 625 626 using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>; 627 628 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, 629 SDValue &Arg, RegsToPassVector &RegsToPass, 630 CCValAssign &VA, CCValAssign &NextVA, 631 SDValue &StackPtr, 632 SmallVectorImpl<SDValue> &MemOpChains, 633 ISD::ArgFlagsTy Flags) const; 634 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 635 SDValue &Root, SelectionDAG &DAG, 636 const SDLoc &dl) const; 637 638 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC, 639 bool isVarArg) const; 640 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 641 bool isVarArg) const; 642 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 643 const SDLoc &dl, SelectionDAG &DAG, 644 const CCValAssign &VA, 645 ISD::ArgFlagsTy Flags) const; 646 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 647 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 648 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const; 649 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 650 const ARMSubtarget *Subtarget) const; 651 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 652 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 653 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 654 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 655 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 656 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const; 657 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 658 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 659 SelectionDAG &DAG) const; 660 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 661 SelectionDAG &DAG, 662 TLSModel::Model model) const; 663 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 664 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const; 665 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 666 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 667 SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const; 668 SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const; 669 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 670 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 671 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 672 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 673 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 674 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 675 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 676 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 677 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 678 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 679 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, 680 const ARMSubtarget *ST) const; 681 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 682 const ARMSubtarget *ST) const; 683 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; 684 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; 685 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const; 686 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed, 687 SmallVectorImpl<SDValue> &Results) const; 688 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed, 689 SDValue &Chain) const; 690 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const; 691 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 692 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 693 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 694 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 695 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 696 697 unsigned getRegisterByName(const char* RegName, EVT VT, 698 SelectionDAG &DAG) const override; 699 700 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 701 SmallVectorImpl<SDNode *> &Created) const override; 702 703 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 704 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 705 /// expanded to FMAs when this method returns true, otherwise fmuladd is 706 /// expanded to fmul + fadd. 707 /// 708 /// ARM supports both fused and unfused multiply-add operations; we already 709 /// lower a pair of fmul and fadd to the latter so it's not clear that there 710 /// would be a gain or that the gain would be worthwhile enough to risk 711 /// correctness bugs. isFMAFasterThanFMulAndFAdd(EVT VT)712 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; } 713 714 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 715 716 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 717 CallingConv::ID CallConv, bool isVarArg, 718 const SmallVectorImpl<ISD::InputArg> &Ins, 719 const SDLoc &dl, SelectionDAG &DAG, 720 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 721 SDValue ThisVal) const; 722 supportSplitCSR(MachineFunction * MF)723 bool supportSplitCSR(MachineFunction *MF) const override { 724 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 725 MF->getFunction().hasFnAttribute(Attribute::NoUnwind); 726 } 727 728 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 729 void insertCopiesSplitCSR( 730 MachineBasicBlock *Entry, 731 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 732 733 SDValue 734 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 735 const SmallVectorImpl<ISD::InputArg> &Ins, 736 const SDLoc &dl, SelectionDAG &DAG, 737 SmallVectorImpl<SDValue> &InVals) const override; 738 739 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl, 740 SDValue &Chain, const Value *OrigArg, 741 unsigned InRegsParamRecordIdx, int ArgOffset, 742 unsigned ArgSize) const; 743 744 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 745 const SDLoc &dl, SDValue &Chain, 746 unsigned ArgOffset, unsigned TotalArgRegsSaveSize, 747 bool ForceMutable = false) const; 748 749 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 750 SmallVectorImpl<SDValue> &InVals) const override; 751 752 /// HandleByVal - Target-specific cleanup for ByVal support. 753 void HandleByVal(CCState *, unsigned &, unsigned) const override; 754 755 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 756 /// for tail call optimization. Targets which want to do tail call 757 /// optimization should implement this function. 758 bool IsEligibleForTailCallOptimization(SDValue Callee, 759 CallingConv::ID CalleeCC, 760 bool isVarArg, 761 bool isCalleeStructRet, 762 bool isCallerStructRet, 763 const SmallVectorImpl<ISD::OutputArg> &Outs, 764 const SmallVectorImpl<SDValue> &OutVals, 765 const SmallVectorImpl<ISD::InputArg> &Ins, 766 SelectionDAG& DAG) const; 767 768 bool CanLowerReturn(CallingConv::ID CallConv, 769 MachineFunction &MF, bool isVarArg, 770 const SmallVectorImpl<ISD::OutputArg> &Outs, 771 LLVMContext &Context) const override; 772 773 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 774 const SmallVectorImpl<ISD::OutputArg> &Outs, 775 const SmallVectorImpl<SDValue> &OutVals, 776 const SDLoc &dl, SelectionDAG &DAG) const override; 777 778 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 779 780 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 781 shouldConsiderGEPOffsetSplit()782 bool shouldConsiderGEPOffsetSplit() const override { return true; } 783 784 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal, 785 SDValue ARMcc, SDValue CCR, SDValue Cmp, 786 SelectionDAG &DAG) const; 787 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 788 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const; 789 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 790 const SDLoc &dl, bool InvalidOnQNaN) const; 791 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const; 792 793 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 794 795 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, 796 MachineBasicBlock *DispatchBB, int FI) const; 797 798 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const; 799 800 bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const; 801 802 MachineBasicBlock *EmitStructByval(MachineInstr &MI, 803 MachineBasicBlock *MBB) const; 804 805 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI, 806 MachineBasicBlock *MBB) const; 807 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI, 808 MachineBasicBlock *MBB) const; 809 }; 810 811 enum NEONModImmType { 812 VMOVModImm, 813 VMVNModImm, 814 OtherModImm 815 }; 816 817 namespace ARM { 818 819 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 820 const TargetLibraryInfo *libInfo); 821 822 } // end namespace ARM 823 824 } // end namespace llvm 825 826 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 827