| /llvm-project-15.0.7/llvm/examples/OrcV2Examples/LLJITDumpObjects/ |
| H A D | LLJITDumpObjects.cpp | 65 int (*Add1)(int) = Add1Addr.toPtr<int(int)>(); in main() local
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| /llvm-project-15.0.7/llvm/examples/OrcV2Examples/LLJITWithCustomObjectLinkingLayer/ |
| H A D | LLJITWithCustomObjectLinkingLayer.cpp | 60 int (*Add1)(int) = Add1Addr.toPtr<int(int)>(); in main() local
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| /llvm-project-15.0.7/llvm/examples/HowToUseLLJIT/ |
| H A D | HowToUseLLJIT.cpp | 95 int (*Add1)(int) = Add1Addr.toPtr<int(int)>(); in main() local
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| /llvm-project-15.0.7/llvm/examples/OrcV2Examples/LLJITWithObjectCache/ |
| H A D | LLJITWithObjectCache.cpp | 73 int (*Add1)(int) = Add1Addr.toPtr<int(int)>(); in runJITWithCache() local
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| /llvm-project-15.0.7/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| H A D | BasicValueFactory.h | 212 const llvm::APSInt &Add1(const llvm::APSInt &V) { in Add1() function
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| /llvm-project-15.0.7/llvm/unittests/Analysis/ |
| H A D | AliasAnalysisTest.cpp | 181 auto *Add1 = BinaryOperator::CreateAdd(Value, Value, "add", BB); in TEST_F() local
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| H A D | ScalarEvolutionTest.cpp | 406 Instruction *Add1 = BinaryOperator::CreateAdd(Mul1, Trunc, "", EntryBB); in TEST_F() local
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| /llvm-project-15.0.7/llvm/unittests/IR/ |
| H A D | PatternMatch.cpp | 1303 Value *Add1 = IRB.CreateExtractValue(Add, 1); in TEST_F() local
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2914 SDValue Add1 = ShiftAmt->getOperand(1); in tryShiftAmountMod() local
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 1088 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), in performADDCombine() local
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 3991 SDValue Add1 = ShiftAmt->getOperand(1); in tryShiftAmountMod() local
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1769 SDValue Add1 = DAG.getBitcast(VT, in LowerUDIVREM64() local
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| H A D | AMDGPULegalizerInfo.cpp | 3554 auto Add1 = B.buildMerge(S64, {Add1_Lo, Add1_Hi}); in legalizeUnsignedDIV_REM64Impl() local
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| H A D | SIISelLowering.cpp | 10835 SDValue Add1 = DAG.getNode(Opc, SL, VT, Op0, Op1); in reassociateScalarOps() local
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13385 SDValue Add1 = in TryDistrubutionADDVecReduce() local
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