1 //===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements a target parser to recognise ARM hardware features 11 // such as FPU/CPU/ARCH/extensions and specific support such as HWDIV. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_SUPPORT_ARMTARGETPARSER_H 16 #define LLVM_SUPPORT_ARMTARGETPARSER_H 17 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Support/ARMBuildAttributes.h" 21 #include <vector> 22 23 namespace llvm { 24 namespace ARM { 25 26 // Arch extension modifiers for CPUs. 27 // Note that this is not the same as the AArch64 list 28 enum ArchExtKind : unsigned { 29 AEK_INVALID = 0, 30 AEK_NONE = 1, 31 AEK_CRC = 1 << 1, 32 AEK_CRYPTO = 1 << 2, 33 AEK_FP = 1 << 3, 34 AEK_HWDIVTHUMB = 1 << 4, 35 AEK_HWDIVARM = 1 << 5, 36 AEK_MP = 1 << 6, 37 AEK_SIMD = 1 << 7, 38 AEK_SEC = 1 << 8, 39 AEK_VIRT = 1 << 9, 40 AEK_DSP = 1 << 10, 41 AEK_FP16 = 1 << 11, 42 AEK_RAS = 1 << 12, 43 AEK_SVE = 1 << 13, 44 AEK_DOTPROD = 1 << 14, 45 AEK_SHA2 = 1 << 15, 46 AEK_AES = 1 << 16, 47 AEK_FP16FML = 1 << 17, 48 AEK_SB = 1 << 18, 49 // Unsupported extensions. 50 AEK_OS = 0x8000000, 51 AEK_IWMMXT = 0x10000000, 52 AEK_IWMMXT2 = 0x20000000, 53 AEK_MAVERICK = 0x40000000, 54 AEK_XSCALE = 0x80000000, 55 }; 56 57 // List of Arch Extension names. 58 // FIXME: TableGen this. 59 struct ExtName { 60 const char *NameCStr; 61 size_t NameLength; 62 unsigned ID; 63 const char *Feature; 64 const char *NegFeature; 65 getNameExtName66 StringRef getName() const { return StringRef(NameCStr, NameLength); } 67 }; 68 69 const ExtName ARCHExtNames[] = { 70 #define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) \ 71 {NAME, sizeof(NAME) - 1, ID, FEATURE, NEGFEATURE}, 72 #include "ARMTargetParser.def" 73 }; 74 75 // List of HWDiv names (use getHWDivSynonym) and which architectural 76 // features they correspond to (use getHWDivFeatures). 77 // FIXME: TableGen this. 78 const struct { 79 const char *NameCStr; 80 size_t NameLength; 81 unsigned ID; 82 getName__anonf8bcb9d1010883 StringRef getName() const { return StringRef(NameCStr, NameLength); } 84 } HWDivNames[] = { 85 #define ARM_HW_DIV_NAME(NAME, ID) {NAME, sizeof(NAME) - 1, ID}, 86 #include "ARMTargetParser.def" 87 }; 88 89 // Arch names. 90 enum class ArchKind { 91 #define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID, 92 #include "ARMTargetParser.def" 93 }; 94 95 // List of CPU names and their arches. 96 // The same CPU can have multiple arches and can be default on multiple arches. 97 // When finding the Arch for a CPU, first-found prevails. Sort them accordingly. 98 // When this becomes table-generated, we'd probably need two tables. 99 // FIXME: TableGen this. 100 template <typename T> struct CpuNames { 101 const char *NameCStr; 102 size_t NameLength; 103 T ArchID; 104 bool Default; // is $Name the default CPU for $ArchID ? 105 unsigned DefaultExtensions; 106 getNameCpuNames107 StringRef getName() const { return StringRef(NameCStr, NameLength); } 108 }; 109 110 const CpuNames<ArchKind> CPUNames[] = { 111 #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \ 112 {NAME, sizeof(NAME) - 1, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT}, 113 #include "ARMTargetParser.def" 114 }; 115 116 // FPU names. 117 enum FPUKind { 118 #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) KIND, 119 #include "ARMTargetParser.def" 120 FK_LAST 121 }; 122 123 // FPU Version 124 enum class FPUVersion { 125 NONE, 126 VFPV2, 127 VFPV3, 128 VFPV3_FP16, 129 VFPV4, 130 VFPV5 131 }; 132 133 // An FPU name restricts the FPU in one of three ways: 134 enum class FPURestriction { 135 None = 0, ///< No restriction 136 D16, ///< Only 16 D registers 137 SP_D16 ///< Only single-precision instructions, with 16 D registers 138 }; 139 140 // An FPU name implies one of three levels of Neon support: 141 enum class NeonSupportLevel { 142 None = 0, ///< No Neon 143 Neon, ///< Neon 144 Crypto ///< Neon with Crypto 145 }; 146 147 // ISA kinds. 148 enum class ISAKind { INVALID = 0, ARM, THUMB, AARCH64 }; 149 150 // Endianness 151 // FIXME: BE8 vs. BE32? 152 enum class EndianKind { INVALID = 0, LITTLE, BIG }; 153 154 // v6/v7/v8 Profile 155 enum class ProfileKind { INVALID = 0, A, R, M }; 156 157 // List of canonical FPU names (use getFPUSynonym) and which architectural 158 // features they correspond to (use getFPUFeatures). 159 // FIXME: TableGen this. 160 // The entries must appear in the order listed in ARM::FPUKind for correct 161 // indexing 162 struct FPUName { 163 const char *NameCStr; 164 size_t NameLength; 165 FPUKind ID; 166 FPUVersion FPUVer; 167 NeonSupportLevel NeonSupport; 168 FPURestriction Restriction; 169 getNameFPUName170 StringRef getName() const { return StringRef(NameCStr, NameLength); } 171 }; 172 173 static const FPUName FPUNames[] = { 174 #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) \ 175 {NAME, sizeof(NAME) - 1, KIND, VERSION, NEON_SUPPORT, RESTRICTION}, 176 #include "llvm/Support/ARMTargetParser.def" 177 }; 178 179 // List of canonical arch names (use getArchSynonym). 180 // This table also provides the build attribute fields for CPU arch 181 // and Arch ID, according to the Addenda to the ARM ABI, chapters 182 // 2.4 and 2.3.5.2 respectively. 183 // FIXME: SubArch values were simplified to fit into the expectations 184 // of the triples and are not conforming with their official names. 185 // Check to see if the expectation should be changed. 186 // FIXME: TableGen this. 187 template <typename T> struct ArchNames { 188 const char *NameCStr; 189 size_t NameLength; 190 const char *CPUAttrCStr; 191 size_t CPUAttrLength; 192 const char *SubArchCStr; 193 size_t SubArchLength; 194 unsigned DefaultFPU; 195 unsigned ArchBaseExtensions; 196 T ID; 197 ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes. 198 getNameArchNames199 StringRef getName() const { return StringRef(NameCStr, NameLength); } 200 201 // CPU class in build attributes. getCPUAttrArchNames202 StringRef getCPUAttr() const { return StringRef(CPUAttrCStr, CPUAttrLength); } 203 204 // Sub-Arch name. getSubArchArchNames205 StringRef getSubArch() const { return StringRef(SubArchCStr, SubArchLength); } 206 }; 207 208 static const ArchNames<ArchKind> ARCHNames[] = { 209 #define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, \ 210 ARCH_BASE_EXT) \ 211 {NAME, sizeof(NAME) - 1, \ 212 CPU_ATTR, sizeof(CPU_ATTR) - 1, \ 213 SUB_ARCH, sizeof(SUB_ARCH) - 1, \ 214 ARCH_FPU, ARCH_BASE_EXT, \ 215 ArchKind::ID, ARCH_ATTR}, 216 #include "llvm/Support/ARMTargetParser.def" 217 }; 218 219 // Information by ID 220 StringRef getFPUName(unsigned FPUKind); 221 FPUVersion getFPUVersion(unsigned FPUKind); 222 NeonSupportLevel getFPUNeonSupportLevel(unsigned FPUKind); 223 FPURestriction getFPURestriction(unsigned FPUKind); 224 225 // FIXME: These should be moved to TargetTuple once it exists 226 bool getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features); 227 bool getHWDivFeatures(unsigned HWDivKind, std::vector<StringRef> &Features); 228 bool getExtensionFeatures(unsigned Extensions, 229 std::vector<StringRef> &Features); 230 231 StringRef getArchName(ArchKind AK); 232 unsigned getArchAttr(ArchKind AK); 233 StringRef getCPUAttr(ArchKind AK); 234 StringRef getSubArch(ArchKind AK); 235 StringRef getArchExtName(unsigned ArchExtKind); 236 StringRef getArchExtFeature(StringRef ArchExt); 237 StringRef getHWDivName(unsigned HWDivKind); 238 239 // Information by Name 240 unsigned getDefaultFPU(StringRef CPU, ArchKind AK); 241 unsigned getDefaultExtensions(StringRef CPU, ArchKind AK); 242 StringRef getDefaultCPU(StringRef Arch); 243 StringRef getCanonicalArchName(StringRef Arch); 244 StringRef getFPUSynonym(StringRef FPU); 245 StringRef getArchSynonym(StringRef Arch); 246 247 // Parser 248 unsigned parseHWDiv(StringRef HWDiv); 249 unsigned parseFPU(StringRef FPU); 250 ArchKind parseArch(StringRef Arch); 251 unsigned parseArchExt(StringRef ArchExt); 252 ArchKind parseCPUArch(StringRef CPU); 253 ISAKind parseArchISA(StringRef Arch); 254 EndianKind parseArchEndian(StringRef Arch); 255 ProfileKind parseArchProfile(StringRef Arch); 256 unsigned parseArchVersion(StringRef Arch); 257 258 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values); 259 StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU); 260 261 } // namespace ARM 262 } // namespace llvm 263 264 #endif 265