Changes in prelude_lower.isle

2f7dbd61 - PCC: remove proof-carrying code (for now?). (#12800)

Tue, 31 Mar 2026 04:36:33 +0000

PCC: remove proof-carrying code (for now?). (#12800)In late 2023, we built out an experimental feature calledProof-Carrying Code (PCC), where we attached "facts" to values in theCLIF IR and built verification of these facts after lowering tomachine instructions. We also added "memory types" describing layoutof memory and a "checked" flag on memory operations such that we couldverify that any checked memory operation accessed valid memory (asdefined by memory types attached to pointer values viafacts). Wasmtime's Cranelift backend then put appropriate memory typesand facts in its IR such that all accesses to memory (aspirationally)could be checked, taking the whole mid-end and lowering backend ofCranelift out of the trusted core that enforces SFI.This basically worked, at the time, for static memories; but never fordynamic memories, and then work on the feature lostprioritization (aka I had to work on other things) and I wasn't ableto complete it and put it in fuzzing/enable it as a production option.Unfortunately since then it has bit-rotted significantly -- as we addnew backend optimizations and instruction lowerings we haven't keptthe PCC framework up to date.Inspired by the discussion in #12497 I think it's time to deleteit (hopefully just "for now"?) unless/until we can build it again. Andwhen we do that, we should probably get it to the point of validatingrobust operation on all combinations of memory configurations beforemerging. (That implies a big experiment branch rather than a bunch ofeager PRs in-tree, but so it goes.) I still believe it is possible tobuild this (and I have ideas on how to do it!) but not right now. List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

bc0ed827 - Cranelift: ISLE: add type parameters to most clif terms in lower (#12717)

Wed, 11 Mar 2026 22:13:05 +0000

Cranelift: ISLE: add type parameters to most clif terms in lower (#12717)* Cranelift: ISLE: add type parameters to most clif terms in lowerRight now in ISLE, most clif instructions have a type parameter in opt for the midend, but not in lowering. From our previous discussions, this is mostly due to the order of implementation rather than a design deciscion. For our verification work, it's useful to also have the type parameters in the lowering terms, as well, if they produce values (e.g., excluding things like `store`). This is based on an earlier commit from @mmcloughlin, with changes to merge into upstream after #10524.* Remove commented out build log* pulley changes, cargo fmt* fmt all* Update cranelift/codegen/meta/src/gen_isle.rsCo-authored-by: Nick Fitzgerald ---------Co-authored-by: Nick Fitzgerald List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

87ed3b60 - Cranelift: make all non-tail, non-indirect calls patchable, and rename patchable ABI to `preserve_all`. (#12160)

Mon, 15 Dec 2025 23:29:06 +0000

Cranelift: make all non-tail, non-indirect calls patchable, and rename patchable ABI to `preserve_all`. (#12160)* Cranelift: make all non-tail, non-indirect calls patchable, and rename patchable ABI to `preserve_all`.As discussed in this week's Cranelift meeting, we've discovered a needto generalize the `patchable_call` mechanism and corresponding`patchable` ABI slightly. In particular, we will need patchable`try_call` callsites as well in order to allow breakpoint handlers tothrow exceptions (desirable functionality eventually) and have this workin the presence of inlining. Also, it's just a nice generalization tosay that patchability is an orthogonal dimension to the call ABI and theother restrictions we initially imposed, and works as long as the basicrequirement (no return values) is met.This also renames the `patchable` ABI to `preserve_all`, to make itclear that its purpose is actually orthogonal, and it can be usedindependently of patchable callsites. It also deletes the `cold` ABI,which never actually did anything and is misleading in the presence ofan actual cold-ish (subzero temperature, actually) ABI like`preserve_all`.* Review feedback. List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

c00e9ea2 - Cranelift: add patchable call instructions. (#12101)

Tue, 02 Dec 2025 00:59:15 +0000

Cranelift: add patchable call instructions. (#12101)* Cranelift: add patchable call instructions.The new `patchable_call` CLIF instruction pairs with the `patchable`ABI, and emits a callsite with one new key property: the MachBuffercarries metadata that describes exactly which byte range to "NOP out"(overwrite with NOP instructions) to disable that callsite. Doing so issemantically valid and explicitly supported.This enables patching of code at runtime to dynamically turn on and offfeatures such as instrumentation or debugging hooks. We plan to use thisto implement breakpoints in Wasmtime's guest debugging support.As part of this change, I added a notion of "unit of NOP bytes" to theMachBuffer so that the consumer (e.g., Wasmtime's Cranelift-based codecompilation pipeline and metadata-producing logic) can handle patchablecallsites without any other special knowledge of the ISA.For the "real metal" ISAs there are perfectly well-defined NOPs to use,but for Pulley, where all opcodes are assigned at compile time by macromagic, I explicitly defined NOP as opcode byte 0 by moving `Nop`'sdefinition to the top of the list and adding a unit test asserting itsencoding.A design note: in principle it would be possible, as an alternative, totreat "patchability" as an orthogonal dimension of all callsites, andemit the metadata describing the instruction-offset range for anycallsite with the flag set. The only truly necessary semanticrestriction is that there are no return values (because if we turn thecallsite off, nothing writes to them); we could support patchability forother ABIs and for the other kinds of call instructions. The `patchable`ABI would then be better described as something like the "no clobbersABI". I opted not to generalize in this way because it creates someless-tested corners and the generalized form, at least at the MachInstlevel, is not really much simpler in the end.A testing note: I opted not to implement actual code patching in the`cranelift-tools` filetest runner and test patching callsites in/out viasome actuation (e.g. a magic hostcall, like we do for throws) because(i) that's a lot of new plumbing and (ii) we are going to test this veryshortly in Wasmtime anyway and (iii) the correctness (or not) of thelocation-and-length metadata is easy enough to verify in thedisassemblies in the compile-tests.* Review feedback: remove dependence on (and test for) NOP being the literal byte 0. List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

62dfbd60 - Cranelift: use SP-offset amodes for `stack_addr`+load/store. (#11727)

Thu, 25 Sep 2025 21:10:54 +0000

Cranelift: use SP-offset amodes for `stack_addr`+load/store. (#11727)We provide `stack_load`/ `stack_store` / `stack_addr` instructions inCranelift to operate on stack slots, and the first two are legalizedto a `stack_addr` plus an ordinary load or store instruction.We currently have lowerings for `stack_addr` that materialize anSP-relative address into a register: for example, `leaq 8(%rsp), %rax`on x86-64 or `add x0, sp, #8` on aarch64.Taken together, we see sequences like (aarch64 / x86-64)``` add x0, sp, #8 / leaq 8(%rsp), %rax str x1, [x0] / movq %rdx, (%rax)```when using `stack_store`s. In particular, we do *not* use the directSP-relative form, which would look like``` str x1, [sp, #8] / movq %rdx, 8(%rsp)```and which we can already generate in other cases, e.g. spillslotmoves (spills/reloads) and clobber saves/restores.This inefficiency is undesirable whenever the embedder is usingstackslots, but in particular when we expect to have high memorytraffic to stack slots (e.g., I am seeing this now when implementingdebug instrumentation in Wasmtime, and user stack map instrumentationfor GC will also benefit).This PR adds new lowerings that use the existing synthetic addressmode we already use for spillslots to emit loads/stores to stackslotsdirectly when possible. The PR does this for x86-64 and aarch64;others could be updated later. List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

4c01ee2f - Cranelift: add get_exception_handler_address. (#11629)

Fri, 05 Sep 2025 22:41:46 +0000

Cranelift: add get_exception_handler_address. (#11629)* Cranelift: add get_exception_handler_address.This is designed to enable applications such as #11592 that usealternative unwinding mechanisms that may not necessarily want to walk astack and look up exception tables. The idea is that whenever it wouldbe valid to resume to an exception handler that is active on the stack,we can provide the same PC as a first-class runtime value that would befound in the exception table for the given handler edge. A "custom"resume step can then use this PC as a resume-point as long as it followsthe relevant exception ABI (i.e.: restore SP, FP, any other savedregisters that the exception ABI specifies, and provide appropriatepayload value(s)).Handlers are associated with edges out of `try_call`s (or`try_call_indirect`s); and edges specifically, not blocks, because therecould be multiple out-edges to one block. The instruction thus takes theblock that contains the try-call and an immediate that indexes itsexceptional edges.This CLIF instruction required a bit of infrastructure to (i) allownaming raw blocks, not just block calls, as instruction arguments, and(ii) allow getting the MachLabel for any other lowered block duringlowering. But given that, the lowerings themselves are straightforwarduses of MachBuffer labels to fix-up PC-relative address-loadinginstructions (e.g., `LEA` or `ADR` or `AUIPC`+`ADDI`).* Review feedback.* Review feedback: more tests. List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

10d2cbc5 - aarch64: Add support for "near" in `LoadExtName` (#11570)

Sat, 30 Aug 2025 00:13:02 +0000

aarch64: Add support for "near" in `LoadExtName` (#11570)* aarch64: Add support for "near" in `LoadExtName`The current aarch64 backend does not support `symbol_value` to get thevalue of a function, for example, with a "near" relocation using arelative relocation. Currently it uses an `Abs8` relocation which meansthat it's not suitable in Wasmtime, for example.This commit refactors relocation/external name support in the aarch64backend to support this mode of relocation. The previous `LoadExtName`was split into `LoadExtName{Got,Near,Far}` where the "near" bit iswhat's new to the backend. The preexisting `symbol-value.clif`-styletests were updated to match the x64 backend which has a morecomprehensive suite of examples of what it looks like to refer tovarious symbols.The goal of this commit is to enable Wasmtime to generate code whichrefers to a relative point elsewhere in the code (e.g. an exceptionhandler) and load the value into a register. This part isn't filled outyet, but it seemed good to at least in the meantime fill out thesemissing relocations in the backend.* Fix clippy warning* Add support for new relocations to cranelift-jitNeeded for filetests List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

79cf7e8e - x64: Migrate `cmov*` to the new assembler (#11095)

Sat, 21 Jun 2025 19:11:45 +0000

x64: Migrate `cmov*` to the new assembler (#11095)This commit adds all `cmov*` variants from the Intel manual to the newassembler. This then additionally removes the `Cmove` pseudo-inst infavor of these new instructions. One difference from before is that thenaming in the `CC` enum does not exactly match what mnemonics Capstoneuses to disassemble. For example `CC.NB` in ISLE corresponds to theIntel instruction `CMOVNB`. This instruction, however, has the sameencoding as `CMOVAE` and Capstone disassembles as `CMOVAE`. This meansthat the instruction selection in ISLE isn't a 1:1 match with mnemonics.This additionally adds support in the assembler ISLE generation tounderstand that instructions which read EFLAGS generate a`ConsumesFlags` variant in their instruction helpers. List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

cfe17cb1 - Cranelift: Generate integer numeric ops and conversions for ISLE in the meta crate (#11065)

Thu, 19 Jun 2025 00:24:34 +0000

Cranelift: Generate integer numeric ops and conversions for ISLE in the meta crate (#11065)* Cranelift: Generate integer numeric ops and conversions for ISLE in the meta crateThis automatically generates operations and conversions for integer types foruse in ISLE.Supported types are: `{i,u}{8,16,32,64,128}`We generate* Comparisons (eq, ne, lt, lt_eq, gt, gt_eq)* Arithmetic operations (add, sub, mul, div, neg) * These each have checked, wrapping, and unwrapping variants* Bitwise operations (and, or, xor, shifts, counting leading/trailing zeros/ones)* A variety of predicates (is_zero, is_power_of_two, is_odd, etc...) * These generate both partial constructors and a handful of extractors* Conversions * These come in a variety of flavors: fallible, infallible, truncating, unwrapping, sign-reinterpretation * Fallible conversions are also available as an extractor* Fix copy paste* Rename `x_reinterpret_as_y` to `x_cast_[un]signed`* Collapse some fallible conversions in pulley lowering* Clean up pulley iconst lowering, make sure narrowest `xconst*` instruction is always used* Avoid an unnecessary truncation in riscv64 lowering* Use extractor instead of partial constructor in x64 `imm` rule* Clean up `op mem, imm` x64 lowering rules* Use `(i64_eq a b)` instead of `(u64_eq (i64_cast_unsigned a) (i64_cast_unsigned b))`* Rename `_unwrapping_` to `_` List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

a4f8f8f4 - Add lowering rules for `{add,sub,or,and} mem, imm` on x64 (#11043)

Mon, 16 Jun 2025 19:50:33 +0000

Add lowering rules for `{add,sub,or,and} mem, imm` on x64 (#11043)* Add lowering rules for `{add,sub,or,and} mem, imm` on x64* Fold ` reg, imm` lowering rules into existing `x64_op_mem` helpers* Remove duplicate decl that got added elsewhere in a different commit on main List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

55e56c18 - [s390x] Use VCodeConstant literal pool (#10756)

Tue, 13 May 2025 17:55:15 +0000

[s390x] Use VCodeConstant literal pool (#10756)This switches s390x to use the common-code VCodeConstantliteral pool instead of constants inlined into the instructionstream. List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

5ded0f4e - Refactor call ABI implementation (#10722)

Tue, 06 May 2025 15:53:24 +0000

Refactor call ABI implementation (#10722)This refactors implementation of call ABI handling across architectureswith the goal of bringing s390x in line with other platforms.The main idea is to- handle main call instruction selection and generation in ISLE (like s390x but unlike other platforms today)- handle argument setup mostly outside of ISLE (like other platforms but unlike s390x today)- handle return value processing as part of the call instructio (like all platforms today)All platforms now emit the main call instruction directly from ISLE,which e.g. handles selection of the correct ISA instruction dependingon the call destination. This ISLE code calls out to helper routinesto handle argument and return value processing. These helpers aremostly common code and provided by the Callee and/or Lower layers,with some platform-specific additions via ISLE Context routines.The old CallSite abstraction is no longer needed; most of thedifferences between call and return_call handling disappear.(There is still a common-code CallInfo vs. a platform-specifcReturnCallInfo. At this point, it should be relatively straight-forward to make CallInfo platform-specific as well if desired,but this is not done here.)Some ISLE infrastructure for iterators / loops, which was onlyever used by the s390x argument processing code, has been removed.s390x now closely matches all other platforms, with only a fewspecial cases (slightly different tail-call ABI requires somedifferences in stack offset computations; we still need tohandle vector lane swaps for cross-ABI calls), which shouldsimplify future maintenance. List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

7bf31723 - Cranelift: simplify some side-effectful instructions in ISLE (#10524)

Tue, 08 Apr 2025 17:57:03 +0000

Cranelift: simplify some side-effectful instructions in ISLE (#10524)* Cranelift: simplify some side-effectful instructions in ISLEThis commit adds a new top-level ISLE entrypoint specifically for instructionsin the side-effectful skeleton: `simplify_skeleton`. While these rewrites areprocessed during the egraph pass, values from skeleton instructions still do notget inserted into the egraph. Indeed, `simplify_skeleton` operateson *instructions* rather than *values* because we do not represent side effectsas values; values do not have side effects in CLIF, instructions do. Therefore,rather than doing a whole dynamic-programming style extraction of the bestcandidate simplification like we do with the egraph, we take an eager and greedyapproach.Furthermore, `simplify_skeleton` is limited only to skeleton instructions thatdo not involve control-flow or terminators right now. This is because changingthe control-flow graph can change whether a use is dominated by a def or not,and we do not currently have the machinery to track and fix up invalidateduses. Addressing this is left for future commits.* fix `MIN / -1` cprop and add negative tests for things simplify_skeleton cannot handle yet List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

94ec88ea - Cranelift: initial try_call / try_call_indirect (exception) support. (#10510)

Tue, 08 Apr 2025 00:02:16 +0000

Cranelift: initial try_call / try_call_indirect (exception) support. (#10510)* Cranelift: initial try_call / try_call_indirect (exception) support.This PR adds `try_call` and `try_call_indirect` instructions, andlowerings on four of five ISAs (x86-64, aarch64, riscv64, pulley; s390xhas its own non-shared ABI code that will need separate work).It extends CLIF to support these instructions as new kinds of branches,and extends block-calls to accept `retN` and `exnN` block-call args thatcarry the normal return values or exception payloads (respectively) intothe appropriate successor blocks.It wires up the "normal return path" so that it continues to work.It updates the ABI so that unwinding is possible without an initialregister state at throw: specifically, as per our RFC, all registers areclobbered. It also includes metadata in the `MachBuffer` that describesexception-catch destinations. However, no unwinder exists to interpretthese catch-destinations yet, so they are untested.* Add try_call_indirect lowering as well. List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

a968b7d3 - asm: add `LOCK`-prefixed instructions (#10477)

Fri, 28 Mar 2025 23:48:40 +0000

asm: add `LOCK`-prefixed instructions (#10477)* asm: add initial `LOCK`-prefixed instructionsThis change is the first in a series to add new instructions that emitthe `LOCK` prefix during encoding.* asm: add all `lock and*` instructionsThis defines all `LOCK`-prefixed variants for `and*`.* asm: add all `lock add|adc*` instructions* asm: add all `lock or*` instructions* asm: add all `lock sub|sbb*` instructions* asm: add all `lock xor*` instructions* asm: reformat using slightly longer linesThis allows the `LOCK`-prefixed definitions to still fit on a singleline.* asm: integrate mem-only operands in `cranelift-codegen``LOCK`-prefixed instructions can only write to memory operands (seeprior commits). This change wires up the necessary codegen to handle thenew `m*` operands.* asm: lower RMW instructions with new `LOCK`-prefixed instructions* Bump allowed size of the `Inst` enumIt is unclear why this would happen now, though perhaps the addition ofall the `LOCK`-prefixed instructions could do it (?). List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

9260ce47 - pulley: Reimplement wasm loads/stores & memory opcodes (#10154)

Mon, 10 Feb 2025 18:05:03 +0000

pulley: Reimplement wasm loads/stores & memory opcodes (#10154)* pulley: Reimplement wasm loads/stores & memory opcodesThis commit is a large refactoring to reimplement how WebAssemblyloads/stores are translated to Pulley opcodes when using theinterpreter. Additionally the functionality related to memory supporthas changed quite a bit with the interpreter as well. This is all basedoff comments on #10102 with the end goal of folding the two Pulleyopcodes today of "do the bounds check" and "do the load" into oneopcode. This is intended to reduce the number of opcodes and overallimprove interpreter throughput by minimizing turns of the interpreterloop.The basic idea behind this PR is that a new basic suite of loads/storesare added to Pulley which trap if the address is zero. This provides aroute to translate trapping loads/stores in CLIF to Pulley bytecodewithout actually causing segfaults at runtime. WebAssembly translationto CLIF is then updated to use the `select` trick for wasm loads/storeswhere either 0 is loaded from or the actual address is loaded from.Basic support for translation and such is added for this everywhere, andthis ensures that all loads/stores for wasm will be translatedsuccessfully with Pulley.The next step was to extend the "g32" addressing mode preexisting inPulley to support a bounds check as well. New pattern-matches were addedto ISLE to search for a bounds check in the address of a trappingload/store. If found then the entire chain of operations necessary tocompute the address are folded into a single "g32" opcode which ends upbeing a fallible load/store at runtime.To fit all this into Pulley this commit contains a number ofrefactorings to shuffle around existing opcodes related to memory andextend various pieces of functionality here and there:* Pulley now uses a `AddrFoo` types to represent addressing modes as a single immediate rather than splitting it up into pieces for each method. For example `AddrO32` represents "base + offset32". `AddrZ` represents the same thing but traps if the address is zero. The `AddrG32` mode represents a bounds-checked 32-bit linear memory access on behalf of wasm.* Pulley loads/stores were reduced to always using an `AddrFoo` immediate. This means that the old `offset8` addressing mode was removed without replacement here (to be added in the future if necessary). Additionally the suite of sign-extension modes supported were trimmed down to remove 8-to-64, 16-to-64, and 32-to-64 extensions folded as part of the opcode. These can of course always be re-added later but probably want to be added just for the `G32` addressing mode as opposed to all addressing modes.* The interpreter itself was refactored to have an `AddressingMode` trait to ensure that all memory accesses, regardless of addressing modes, are largely just copy/pastes of each other. In the future it might make sense to implement these methods with a macro, but for now it's copy/paste.* In ISLE the `XLoad` generic instruction removed its `ext` field to have extensions handled exclusively in ISLE instead of partly in `emit.rs`.* Float/vector loads/stores now have "g32" addressing (in addition to the "z" that's required for wasm) since it was easy to add them.* Translation of 1-byte accesses on Pulley from WebAssembly to CLIF no longer has a special case for using `a >= b` instead of `a > b - 1` to ensure that the same bounds-check instruction can be used for all sizes of loads/stores.* The bounds-check which folded a load-of-the-bound into the opcode is now present as a "g32bne" addressing mode. with its of suite of instructions to boo.Overall this PR is not a 1:1 replacement of all previous opcodes withexactly one opcode. For example loading 8 bits sign-extended to 64-bitsis now two opcodes instead of one. Additionally some previous opcodeshave expanded in size where for example the 8-bit offset mode was removein favor of only having 32-bit offsets. The goal of this PR is to reboothow memory is handled in Pulley. All loads/stores now use a specificaddressing mode and currently all operations supported across addressingmodes are consistently supported. In the future it's expected that somefeatures will be added to some addressing modes and not others asnecessary, for example extending the "g32" addressing mode only insteadof all addressing modes.For an evaluation of this PR:* Code size: `spidermonkey.cwasm` file is reduced from 19M to 16M.* Sightglass: `pulldown-cmark` is improved by 15%* Sightglass: `bz2` is improved by 20%* Sightglass: `spidermonkey` is improved by 22%* Coremark: score improved by 40%Overall this PR and new design looks to be a large win. This is alldriven by the reduction in opcodes both for compiled code size andexecution speed by minimizing turns of the interpreter loop. In the endI'm also pretty happy with how this turned out and I think therefactorings are well worth it.* Use new `is_pulley` helper more* Improve `addrz` helper, tighten up `memory-inbounds.wat` a bit* Improve codegen in a few `memory-inbounds.wat` cases* Fix test expectation List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

1e4c470a - pulley: Add immediate payloads to more opcodes (#9861)

Thu, 19 Dec 2024 02:23:49 +0000

pulley: Add immediate payloads to more opcodes (#9861)* pulley: Add immediate payloads to more opcodesThis commit adds immediate payloads to the following instructions:* `xmul32` - `xmul32_s8` / `xmul32_s32`* `xmul64` - `xmul64_s8` / `xmul64_s32`* `xband32` - `xband32_s8` / `xband32_s32`* `xband64` - `xband64_s8` / `xband64_s32`* `xbor32` - `xbor32_s8` / `xbor32_s32`* `xbor64` - `xbor64_s8` / `xbor64_s32`* `xbxor32` - `xbxor32_s8` / `xbxor32_s32`* `xbxor64` - `xbxor64_s8` / `xbxor64_s32`* `xshl32` - `xshl32_u6`* `xshl64` - `xshl64_u6`* `xshr32_u` - `xshl32_u_u6`* `xshr64_u` - `xshl64_u_u6`* `xshr32_s` - `xshl32_s_u6`* `xshr64_s` - `xshl64_s_u6`For shifts there's no need to have 32-bit immediates (or even 8-bit)since 6 bits is enough to encode all the immediates. This means that the6-bit immediate is packed within `BinaryOperands` as a new `U6` type.This commit unfortunately does not shrink `spidermonkey.cwasm`significantly beyond the prior 29M. This is nevertheless expected to berelatively important for performance.* Fix test expectations List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

b3ac63ae - pulley: Add add/sub-with immediate opcodes (#9859)

Wed, 18 Dec 2024 22:24:13 +0000

pulley: Add add/sub-with immediate opcodes (#9859)This commit extends the pulley opcode space with integeraddition/subtraction where `src2` is an immediate. The goal here is tobe a "sort of macro instruction" despite it not being too too macrohere. This cuts down on `xconstN` instructions which both saves space inthe final binary and should be slightly more optimal perf-wise due toonly one dispatch being needed.In this commit the `xadd32` instruction is previously 3 bytes: one foran opcode and 2 bytes for the dst/src1/src2 binary operands. Adding asmall constant to a register previously took 5 bytes where 2 bytes wereneeded for `xconst8 N` then 3 for the addition. Here the encoding sizeof the new instruction is 4 bytes: 1 for the opcode, 2 for dst/src1, andone for the immediate. This is currently chosen to mostly optimizedispatch in the interpreter loop as opposed to code size (as only asingle byte is saved). In the future thought it would be possible toextend `BinaryOperands` to one operand being a 6-bit immediate topreserve the same code size.This also notably adds, for addition/subtraction, only unsignedimmediates. With addition/subtraction being inverses of one anothersupporting signed immediates isn't necessary and helps free up anotherbit for packing numbers into these opcodes.This change reduces the size of `spidermonkey.cwasm` from 31M to 29Mlocally. List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

bb886ffc - ISLE: Add proper bool type (#9593)

Thu, 14 Nov 2024 22:55:38 +0000

ISLE: Add proper bool type (#9593)* ISLE: add proper booleans (expressions)Copyright (c) 2024, Arm Limited.Signed-off-by: Karl Meakin * ISLE: add proper booleans (patterns)Copyright (c) 2024, Arm Limited.Signed-off-by: Karl Meakin * ISLE: add proper booleans (spec expressions)Copyright (c) 2024, Arm Limited.Signed-off-by: Karl Meakin * ISLE: replace opaque boolean constantsCopyright (c) 2024, Arm Limited.Replace all occurences of `$true` and `$false` with `true` and `false`.Signed-off-by: Karl Meakin * ISLE: remove `on_lhs` argumentInstead of threading `on_lhs` through all the calls to `translate_expr`,we can just set `is_partial` and `is_pure` on `root_flags` to true.Copyright (c) 2024, Arm Limited.Signed-off-by: Karl Meakin * ISLE: add proper booleans (language reference)Copyright (c) 2024, Arm Limited.Signed-off-by: Karl Meakin ---------Signed-off-by: Karl Meakin List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle

af968461 - Gate support for implicit return area pointers behind an option (#9511)

Sun, 27 Oct 2024 18:05:54 +0000

Gate support for implicit return area pointers behind an option (#9511)* Remove couple of unused isle helpers* Gate support for implicit return area pointers behind an optionIt implements an incorrect ABI and may be removed in the future due tocomplexity reasons. By requiring to enable an option to use it, itbecomes harder to accidentally hit the ABI issue and allows a moredeprecation and eventual removal.* Fix review comments* Enable enable_multi_ret_implicit_sret for s390x tests that use i128* Enable enable_multi_ret_implicit_sret for riscv tests that use vector types* Enable enable_multi_ret_implicit_sret for more riscv tests* Enable enable_multi_ret_implicit_sret for windows tests that use i128 List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude_lower.isle