Changes in prelude.isle

198e34a2 - [Cranelift] add type-aware rotate operations (#12764)

Mon, 16 Mar 2026 21:19:24 +0000

[Cranelift] add type-aware rotate operations (#12764)* [Cranelift] add type-aware rotate operations* [Cranelift] add cprop rules for rotations* [Cranlift] assert datatype assumptions* add filetests for cprops List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

7129b4b9 - Constant propagation opts (#11790)

Tue, 07 Oct 2025 14:32:13 +0000

Constant propagation opts (#11790)* Add optimizations for leading / trailing zeros* Add optimizations for srem* Add optimizations for urem* clean up* fixes* fixes* nicer rust* urem* srem* Remove srem special casingiN::min % -1 = 0* Remove unneeded variable shift List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

a21aba2d - Revert "Constant propagation opts (#11748)" (#11785)

Fri, 03 Oct 2025 16:21:12 +0000

Revert "Constant propagation opts (#11748)" (#11785)* Revert "Constant propagation opts (#11748)"This reverts commit 7cebfa206fe4a40ab54e9862f30b05c5fefb9043.* Add regression test for revert List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

7cebfa20 - Constant propagation opts (#11748)

Wed, 01 Oct 2025 20:11:07 +0000

Constant propagation opts (#11748)* Add optimizations for leading / trailing zeros* Add optimizations for srem* Add optimizations for urem* clean up* fixes List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

cfe17cb1 - Cranelift: Generate integer numeric ops and conversions for ISLE in the meta crate (#11065)

Thu, 19 Jun 2025 00:24:34 +0000

Cranelift: Generate integer numeric ops and conversions for ISLE in the meta crate (#11065)* Cranelift: Generate integer numeric ops and conversions for ISLE in the meta crateThis automatically generates operations and conversions for integer types foruse in ISLE.Supported types are: `{i,u}{8,16,32,64,128}`We generate* Comparisons (eq, ne, lt, lt_eq, gt, gt_eq)* Arithmetic operations (add, sub, mul, div, neg) * These each have checked, wrapping, and unwrapping variants* Bitwise operations (and, or, xor, shifts, counting leading/trailing zeros/ones)* A variety of predicates (is_zero, is_power_of_two, is_odd, etc...) * These generate both partial constructors and a handful of extractors* Conversions * These come in a variety of flavors: fallible, infallible, truncating, unwrapping, sign-reinterpretation * Fallible conversions are also available as an extractor* Fix copy paste* Rename `x_reinterpret_as_y` to `x_cast_[un]signed`* Collapse some fallible conversions in pulley lowering* Clean up pulley iconst lowering, make sure narrowest `xconst*` instruction is always used* Avoid an unnecessary truncation in riscv64 lowering* Use extractor instead of partial constructor in x64 `imm` rule* Clean up `op mem, imm` x64 lowering rules* Use `(i64_eq a b)` instead of `(u64_eq (i64_cast_unsigned a) (i64_cast_unsigned b))`* Rename `_unwrapping_` to `_` List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

a4f8f8f4 - Add lowering rules for `{add,sub,or,and} mem, imm` on x64 (#11043)

Mon, 16 Jun 2025 19:50:33 +0000

Add lowering rules for `{add,sub,or,and} mem, imm` on x64 (#11043)* Add lowering rules for `{add,sub,or,and} mem, imm` on x64* Fold ` reg, imm` lowering rules into existing `x64_op_mem` helpers* Remove duplicate decl that got added elsewhere in a different commit on main List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

d6f72b56 - x64: Delete the `Imm` instruction variant (#11038)

Mon, 16 Jun 2025 17:18:08 +0000

x64: Delete the `Imm` instruction variant (#11038)* x64: Delete the `Imm` instruction variantThis commit deletes the `Imm` instruction variant in ISLE in favor ofpreexisting instructions already added to the new assembler. Thisrequired rejiggering and refactoring the `imm` constructor in ISLE andrefactoring the `Inst::imm` method as well.One minor change in this PR is that the immediate `u64::from(u32::MAX)`was mistakenly classified previously as requiring `movabsq` but afterthis PR it's now classified as being able to use `movl` because theupper bits are zero'd with `movl`. This was an off-by-one mistake in the`nonzero_u64_fits_in_u32` extractor that was deleted in this PR.This change also documents the preexisting behavior of the `imm`constructor and the `Inst::imm` helper which is to zero the upper bitsof the 64-bit immediate passed in to those functions if the desired sizeis less than 64-bits. This is something I would prefer to avoid becauseit means the logical value of the immediate is not being preserved whichcould be a way to possibly subtly introduce bugs in the future. For nowthough more widespread changes would be needed to fix this so they'reomitted.* Remove emit tests* Update winch test expectations List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

41bbc458 - x64: Remove `MovImmM` and `MovRM` (#11021)

Thu, 12 Jun 2025 00:30:30 +0000

x64: Remove `MovImmM` and `MovRM` (#11021)This commit removes these two instruction variants although nothing newwas added to the new assembler as all the necessary instructions werealready supported. List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

94477009 - Cranelift: `or(x, C) + (-C) --> and(x, ~C)` (#10979)

Tue, 10 Jun 2025 17:33:19 +0000

Cranelift: `or(x, C) + (-C) --> and(x, ~C)` (#10979)* add helper* add rule and test* update rule* add rule summary* update expectation test List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

84477fc5 - Cranelift: properly reject unimplemented big-endian loads/stores. (#10863)

Fri, 30 May 2025 19:00:05 +0000

Cranelift: properly reject unimplemented big-endian loads/stores. (#10863)At some point during the development of the Cranelift backendinfrastructure, to properly support big-endian architectures such ass390x, we added explicit endianness flags to `MemFlags`, which aregiven to all memory operations (e.g., loads, stores, and atomicops). In s390x in particular, the backend carefully observes theseflags, because a prominent use of Cranelift (as a Wasm backend)requires explicit little-endian behavior and the system isbig-endian. However, all of our other supported ISAs are little-endianand so we did not implement explicit checks at the time, insteadaccepting all loads and stores as an artifact of ourlittle-endian-only origins.This PR adds explicit conditions to all ISLE rules that lower loads,stores, and atomic ops on x86-64, aarch64, and riscv64 to acceptlittle or "native" (also little) endian operations only. Compilationof a big-endian operation will now result in a compilation errorbecause no ISLE rule will match (no lowering exists). At some laterpoint we could add these lowerings, but for now we at least do notmiscompile.Fixes #10861. List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

6abe3c44 - x64: Fix panic compiling 16-bit multiply-with-immediate (#10817)

Tue, 20 May 2025 21:31:11 +0000

x64: Fix panic compiling 16-bit multiply-with-immediate (#10817)* x64: Fix panic compiling 16-bit multiply-with-immediateThis commit fixes a minor regression from #10782 found via fuzzing. Theregression is 16-bit immediates were forced to fit from an `i32` valueinto a `u16` for 16-bit multiplication. This meant though that negativenumbers failed this conversion which meant that ISLE would panic due tothe value not being matched. This fixes the logic to first fit the i32into an i16 and then cast that to a u16 where the first phase should hitall the constants that are possible in Cranelift.* Add some more tests List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

7ea7ebcc - x64: convert all multiplication-related instructions (#10782)

Mon, 19 May 2025 20:01:44 +0000

x64: convert all multiplication-related instructions (#10782)* asm: add SSE4.1 feature* asm: refactor format constructors with expanding structs* asm: add implicit operandsImplicit operands are used by an instruction but not present in itsdisassembled output. Instructions like `mul`, e.g., will write to the`%rax` and `%rdx` registers, but this is all invisible in disassembly.Implicit operands are always fixed (i.e., the register is known), butnot all fixed operands are implicit (i.e., some fixed registers _are_disassembled).* asm: add `mul*` instructions, vector and scalar* asm: generate ISLE for multi-return constructors--`AssemblerOutputs::RetValueRegs`Certain `mul*` instructions write to multiple registers. For registerallocation, Cranelift needs to know about all of these registers. Thischange uses the pre-existing pattern of returning a `ValueRegs` type toindicate this. This change is limited to what is needed now: the onlymulti-return needed now uses two fixed registers.* x64: convert SSE multiplications* x64: convert scalar multiplications* x64: remove old `Inst::Mul*` variants* winch: convert multiplicationsThis does not include any special "small immediate resizing" rules forWinch, so the Winch disassembly tests gain a few bytes (e.g., someimmediates that _could_ fit in 8 bits are emitted as the full 32 bits).* refactor: move `i32`-related extractors to `prelude.isle`* review: print the implicit registers as well* fix: the instruction size has changed (again) List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

5ded0f4e - Refactor call ABI implementation (#10722)

Tue, 06 May 2025 15:53:24 +0000

Refactor call ABI implementation (#10722)This refactors implementation of call ABI handling across architectureswith the goal of bringing s390x in line with other platforms.The main idea is to- handle main call instruction selection and generation in ISLE (like s390x but unlike other platforms today)- handle argument setup mostly outside of ISLE (like other platforms but unlike s390x today)- handle return value processing as part of the call instructio (like all platforms today)All platforms now emit the main call instruction directly from ISLE,which e.g. handles selection of the correct ISA instruction dependingon the call destination. This ISLE code calls out to helper routinesto handle argument and return value processing. These helpers aremostly common code and provided by the Callee and/or Lower layers,with some platform-specific additions via ISLE Context routines.The old CallSite abstraction is no longer needed; most of thedifferences between call and return_call handling disappear.(There is still a common-code CallInfo vs. a platform-specifcReturnCallInfo. At this point, it should be relatively straight-forward to make CallInfo platform-specific as well if desired,but this is not done here.)Some ISLE infrastructure for iterators / loops, which was onlyever used by the s390x argument processing code, has been removed.s390x now closely matches all other platforms, with only a fewspecial cases (slightly different tail-call ABI requires somedifferences in stack offset computations; we still need tohandle vector lane swaps for cross-ABI calls), which shouldsimplify future maintenance. List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

d48b3856 - Add support for loading, storing and bitcasting small vectors on x64 and aarch64 (#10693)

Tue, 29 Apr 2025 22:46:04 +0000

Add support for loading, storing and bitcasting small vectors on x64 and aarch64 (#10693) List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

e52ddbd3 - Add initial `f16` and `f128` support to the s390x backend (#10691)

Tue, 29 Apr 2025 17:46:37 +0000

Add initial `f16` and `f128` support to the s390x backend (#10691) List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

494f5af2 - Add inital support for `f16` without `Zfh` and `f128` to the riscv64 backend (#10652)

Thu, 24 Apr 2025 16:40:13 +0000

Add inital support for `f16` without `Zfh` and `f128` to the riscv64 backend (#10652) List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

7bf31723 - Cranelift: simplify some side-effectful instructions in ISLE (#10524)

Tue, 08 Apr 2025 17:57:03 +0000

Cranelift: simplify some side-effectful instructions in ISLE (#10524)* Cranelift: simplify some side-effectful instructions in ISLEThis commit adds a new top-level ISLE entrypoint specifically for instructionsin the side-effectful skeleton: `simplify_skeleton`. While these rewrites areprocessed during the egraph pass, values from skeleton instructions still do notget inserted into the egraph. Indeed, `simplify_skeleton` operateson *instructions* rather than *values* because we do not represent side effectsas values; values do not have side effects in CLIF, instructions do. Therefore,rather than doing a whole dynamic-programming style extraction of the bestcandidate simplification like we do with the egraph, we take an eager and greedyapproach.Furthermore, `simplify_skeleton` is limited only to skeleton instructions thatdo not involve control-flow or terminators right now. This is because changingthe control-flow graph can change whether a use is dominated by a def or not,and we do not currently have the machinery to track and fix up invalidateduses. Addressing this is left for future commits.* fix `MIN / -1` cprop and add negative tests for things simplify_skeleton cannot handle yet List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

9260ce47 - pulley: Reimplement wasm loads/stores & memory opcodes (#10154)

Mon, 10 Feb 2025 18:05:03 +0000

pulley: Reimplement wasm loads/stores & memory opcodes (#10154)* pulley: Reimplement wasm loads/stores & memory opcodesThis commit is a large refactoring to reimplement how WebAssemblyloads/stores are translated to Pulley opcodes when using theinterpreter. Additionally the functionality related to memory supporthas changed quite a bit with the interpreter as well. This is all basedoff comments on #10102 with the end goal of folding the two Pulleyopcodes today of "do the bounds check" and "do the load" into oneopcode. This is intended to reduce the number of opcodes and overallimprove interpreter throughput by minimizing turns of the interpreterloop.The basic idea behind this PR is that a new basic suite of loads/storesare added to Pulley which trap if the address is zero. This provides aroute to translate trapping loads/stores in CLIF to Pulley bytecodewithout actually causing segfaults at runtime. WebAssembly translationto CLIF is then updated to use the `select` trick for wasm loads/storeswhere either 0 is loaded from or the actual address is loaded from.Basic support for translation and such is added for this everywhere, andthis ensures that all loads/stores for wasm will be translatedsuccessfully with Pulley.The next step was to extend the "g32" addressing mode preexisting inPulley to support a bounds check as well. New pattern-matches were addedto ISLE to search for a bounds check in the address of a trappingload/store. If found then the entire chain of operations necessary tocompute the address are folded into a single "g32" opcode which ends upbeing a fallible load/store at runtime.To fit all this into Pulley this commit contains a number ofrefactorings to shuffle around existing opcodes related to memory andextend various pieces of functionality here and there:* Pulley now uses a `AddrFoo` types to represent addressing modes as a single immediate rather than splitting it up into pieces for each method. For example `AddrO32` represents "base + offset32". `AddrZ` represents the same thing but traps if the address is zero. The `AddrG32` mode represents a bounds-checked 32-bit linear memory access on behalf of wasm.* Pulley loads/stores were reduced to always using an `AddrFoo` immediate. This means that the old `offset8` addressing mode was removed without replacement here (to be added in the future if necessary). Additionally the suite of sign-extension modes supported were trimmed down to remove 8-to-64, 16-to-64, and 32-to-64 extensions folded as part of the opcode. These can of course always be re-added later but probably want to be added just for the `G32` addressing mode as opposed to all addressing modes.* The interpreter itself was refactored to have an `AddressingMode` trait to ensure that all memory accesses, regardless of addressing modes, are largely just copy/pastes of each other. In the future it might make sense to implement these methods with a macro, but for now it's copy/paste.* In ISLE the `XLoad` generic instruction removed its `ext` field to have extensions handled exclusively in ISLE instead of partly in `emit.rs`.* Float/vector loads/stores now have "g32" addressing (in addition to the "z" that's required for wasm) since it was easy to add them.* Translation of 1-byte accesses on Pulley from WebAssembly to CLIF no longer has a special case for using `a >= b` instead of `a > b - 1` to ensure that the same bounds-check instruction can be used for all sizes of loads/stores.* The bounds-check which folded a load-of-the-bound into the opcode is now present as a "g32bne" addressing mode. with its of suite of instructions to boo.Overall this PR is not a 1:1 replacement of all previous opcodes withexactly one opcode. For example loading 8 bits sign-extended to 64-bitsis now two opcodes instead of one. Additionally some previous opcodeshave expanded in size where for example the 8-bit offset mode was removein favor of only having 32-bit offsets. The goal of this PR is to reboothow memory is handled in Pulley. All loads/stores now use a specificaddressing mode and currently all operations supported across addressingmodes are consistently supported. In the future it's expected that somefeatures will be added to some addressing modes and not others asnecessary, for example extending the "g32" addressing mode only insteadof all addressing modes.For an evaluation of this PR:* Code size: `spidermonkey.cwasm` file is reduced from 19M to 16M.* Sightglass: `pulldown-cmark` is improved by 15%* Sightglass: `bz2` is improved by 20%* Sightglass: `spidermonkey` is improved by 22%* Coremark: score improved by 40%Overall this PR and new design looks to be a large win. This is alldriven by the reduction in opcodes both for compiled code size andexecution speed by minimizing turns of the interpreter loop. In the endI'm also pretty happy with how this turned out and I think therefactorings are well worth it.* Use new `is_pulley` helper more* Improve `addrz` helper, tighten up `memory-inbounds.wat` a bit* Improve codegen in a few `memory-inbounds.wat` cases* Fix test expectation List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

a6a08570 - pulley: Add more addressing modes for loads/stores (#9994)

Mon, 13 Jan 2025 21:05:07 +0000

pulley: Add more addressing modes for loads/stores (#9994)* pulley: Add more addressing modes for loads/storesThis commit adds a new "g32" addressing mode to Pulley that matches thepattern emitted by Cranelift for 32-bit wasm guests running on hosts.The general idea here is that this addressing mode encompasses anaddition of a host-width value to a zero-extended (optionally) 32-bitvalue. On 32-bit hosts there's no zero-extension but on 64-bit hoststhere's a zero-extension. The wasm address is always 32-bits thoughwhich enables using a single instruction for both 32 and 64-bit hosts.New "g32" loads and stores are added to Pulley with varying sizes andoptions according to what seems to be common in wasm. The `disas` testsuite was updated to showcase using these instructions for wasmloads/stores on 32 and 64-bit hosts.An additional change in this commit is to deduplicate the 32/64-bitbounds-check macro-ops. The trick in this commit works for those as wellmeaning that only a single instruction is needed instead ofone-per-host-pointer-width. Additionally the load of the bound from the`VMContext` is folded into the bounds check itself as it was found thatthis was always present anyway before the bounds check.Overall this shrinks the size of `spidermonkey.cwasm` from 21M to 20Mand the runtime of `pulldown-cmark`, `bz2`, and `spidermonkey` onSightglass have all been reduced by 10%. Not as big wins as I was hopingfor but alas.* Fix debug assertions on 32-bit List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle

1e4c470a - pulley: Add immediate payloads to more opcodes (#9861)

Thu, 19 Dec 2024 02:23:49 +0000

pulley: Add immediate payloads to more opcodes (#9861)* pulley: Add immediate payloads to more opcodesThis commit adds immediate payloads to the following instructions:* `xmul32` - `xmul32_s8` / `xmul32_s32`* `xmul64` - `xmul64_s8` / `xmul64_s32`* `xband32` - `xband32_s8` / `xband32_s32`* `xband64` - `xband64_s8` / `xband64_s32`* `xbor32` - `xbor32_s8` / `xbor32_s32`* `xbor64` - `xbor64_s8` / `xbor64_s32`* `xbxor32` - `xbxor32_s8` / `xbxor32_s32`* `xbxor64` - `xbxor64_s8` / `xbxor64_s32`* `xshl32` - `xshl32_u6`* `xshl64` - `xshl64_u6`* `xshr32_u` - `xshl32_u_u6`* `xshr64_u` - `xshl64_u_u6`* `xshr32_s` - `xshl32_s_u6`* `xshr64_s` - `xshl64_s_u6`For shifts there's no need to have 32-bit immediates (or even 8-bit)since 6 bits is enough to encode all the immediates. This means that the6-bit immediate is packed within `BinaryOperands` as a new `U6` type.This commit unfortunately does not shrink `spidermonkey.cwasm`significantly beyond the prior 29M. This is nevertheless expected to berelatively important for performance.* Fix test expectations List of files: /wasmtime-44.0.1/cranelift/codegen/src/prelude.isle