Changes in vcode.rs

2f7dbd61 - PCC: remove proof-carrying code (for now?). (#12800)

Tue, 31 Mar 2026 04:36:33 +0000

PCC: remove proof-carrying code (for now?). (#12800)In late 2023, we built out an experimental feature calledProof-Carrying Code (PCC), where we attached "facts" to values in theCLIF IR and built verification of these facts after lowering tomachine instructions. We also added "memory types" describing layoutof memory and a "checked" flag on memory operations such that we couldverify that any checked memory operation accessed valid memory (asdefined by memory types attached to pointer values viafacts). Wasmtime's Cranelift backend then put appropriate memory typesand facts in its IR such that all accesses to memory (aspirationally)could be checked, taking the whole mid-end and lowering backend ofCranelift out of the trusted core that enforces SFI.This basically worked, at the time, for static memories; but never fordynamic memories, and then work on the feature lostprioritization (aka I had to work on other things) and I wasn't ableto complete it and put it in fuzzing/enable it as a production option.Unfortunately since then it has bit-rotted significantly -- as we addnew backend optimizations and instruction lowerings we haven't keptthe PCC framework up to date.Inspired by the discussion in #12497 I think it's time to deleteit (hopefully just "for now"?) unless/until we can build it again. Andwhen we do that, we should probably get it to the point of validatingrobust operation on all combinations of memory configurations beforemerging. (That implies a big experiment branch rather than a bunch ofeager PRs in-tree, but so it goes.) I still believe it is possible tobuild this (and I have ideas on how to do it!) but not right now. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

b5d2ff5d - Cranelift: update regalloc2 to 0.15.0 to permit more VRegs. (#12611)

Wed, 18 Feb 2026 00:23:43 +0000

Cranelift: update regalloc2 to 0.15.0 to permit more VRegs. (#12611)* Cranelift: update regalloc2 to 0.15.0 to permit more VRegs.This pulls in bytecodealliance/regalloc2#257 to permit more VRegs tobe used in a single function body, addressing #12229 and our followupdiscussions about supporting function body sizes up to the Wasmimplementation limit standard.In addition to the RA2 upgrade, this also includes a bit more explicitlimit-checking on the Cranelift side: note that we don't directly use`regalloc2::VReg` but instead we further bitpack it into `Reg`, whichis logically a sum type of `VReg`, `PReg` and `SpillSlot` (the lastone needed to represent stack allocation locations on defs, e.g. oncallsites with many returns). `PReg`s are packed into the beginning ofthe `VReg` index space but `SpillSlot`s are distinguished by stealingthe upper bit of a `u32`. This was previously not a problem given thesmaller `VReg` index space but now we need to check explicitly; hence`Reg::from_virtual_reg_checked` and its use in the lowering vregallocator. Because the `VReg` index packs the class into the bottomtwo bits, and index into the upper 30, but we steal one bit at thetop, the true limit for VReg count is thus actually 2^29, or512M.Fixes #12229.* Drop `code_too_large` test. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

9fe4cc18 - cranelift: improve debug value locations around cold blocks (#12484)

Wed, 04 Feb 2026 19:42:04 +0000

cranelift: improve debug value locations around cold blocks (#12484)If a debug range started or ended on an instruction from a cold block,we omitted the entire range. Fix by skipping the instructions in thecold block to find the next valid offset. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

76911c29 - Partial support for no_std in cranelift_codegen (#12222)

Wed, 07 Jan 2026 16:41:32 +0000

Partial support for no_std in cranelift_codegen (#12222)* Move most things from std to core and alloc* Port assembler_x64 to no_std* before adding prelude to each file* Most of the files now work with no_std* update isle to use alloc and core* some instances shouldn't have been renamed, fixes cargo test* add cranelift-assembler-x64 (no_std) to CI* fix codegen_meta, missed one spot with std::slice* automatically remove prelude with cargo fix* update isle changes* update assembler changes* update assembler changes* use latest codegen changes + fix FxHash problem* add imports* fix floating issues with libm* remove unused import* temporarily remove OnceLock* add no_std arm support and add it into CI* Move most things from std to core and alloc* Port assembler_x64 to no_std* before adding prelude to each file* Most of the files now work with no_std* update isle to use alloc and core* some instances shouldn't have been renamed, fixes cargo test* add cranelift-assembler-x64 (no_std) to CI* automatically remove prelude with cargo fix* update isle changes* update assembler changes* update assembler changes* use latest codegen changes + fix FxHash problem* add imports* fix floating issues with libm* remove unused import* temporarily remove OnceLock* add no_std arm support and add it into CI* Move most things from std to core and alloc* Port assembler_x64 to no_std* before adding prelude to each file* Most of the files now work with no_std* update isle to use alloc and core* add cranelift-assembler-x64 (no_std) to CI* automatically remove prelude with cargo fix* update isle changes* update assembler changes* use latest codegen changes + fix FxHash problem* add imports* fix floating issues with libm* temporarily remove OnceLock* add no_std arm support and add it into CI* revert Cargo.toml formating* remove prelude and fix cargo.toml* cargo fmt* remove empty lines* bad renames* macro_use only on no_std* revert OnceLock change* only use stable libm features* update regalloc2* update comment* use continue instead* Update vets---------Co-authored-by: Alex Crichton List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

0889323a - cranelift-codegen: rename most uses of std to core and alloc (#12237)

Sat, 03 Jan 2026 00:54:48 +0000

cranelift-codegen: rename most uses of std to core and alloc (#12237)* rename most std uses to core and alloc* cargo fmt List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

a3d6e407 - Cranelift: add debug tag infrastructure. (#11768)

Mon, 06 Oct 2025 19:38:03 +0000

Cranelift: add debug tag infrastructure. (#11768)* Cranelift: add debug tag infrastructure.This PR adds *debug tags*, a kind of metadata that can attach to CLIFinstructions and be lowered to VCode instructions and as metadata onthe produced compiled code. It also adds opaque descriptor blobscarried with stackslots. Together, these two features allow decoratingIR with first-class debug instrumentation that is properly preservedby the compiler, including across optimizations andinlining. (Wasmtime's use of these features will come in followupPRs.)The key idea of a "debug tag" is to allow the Cranelift embedder toexpress whatever information it needs to, in a format that is opaqueto Cranelift itself, except for the parts that need translation duringlowering. In particular, the `DebugTag::StackSlot` variant getstranslated to a physical offset into the stackframe in the compiledmetadata output. So, for example, the embedder can emit a tagreferring to a stackslot, and another describing an offset in thatstackslot.The debug tags exist as a *sequence* on any given instruction; themeaning of the sequence is known only to the embedder, *except* thatduring inlining, the tags for the inlining call instruction areprepended to the tags of inlined instructions. In this way, acanonical use-case of tags as describing original source-languageframes can preserve the source-language view even when multiplefunctions are inlined into one.The descriptor on a stackslot may look a little odd at first, but itspurpose is to allow serializing some description ofstackslot-contained runtime user-program data, in a way that is firmlyattached to the stackslot. In particular, in the face of inlining,this descriptor is copied into the inlining (parent) function from theinlined function when the stackslot entity is copied; no othermetadata outside Cranelift needs to track the identity of stackslotsand know about that motion. This fits nicely with the ability of tagsto refer to stackslots; together, the embedder can annotateinstructions as having certain state in stackslots, and describe theformat of that state per stackslot.This infrastructure is tested with some compile-tests now;testing of the interpretation of the metadata output will come withend-to-end debug instrumentation tests in a followup PR.* Review feedback: add back sequence points and enforce tags only on sequence points or calls.* Use Vecs for debug metadata in MachBuffer to avoid SmallVec size penalty in not-used case.* Review feedback: switch from inlined stackslot descriptor blobs to u64 keys. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

3b85d838 - feat: add granular tail call detection infrastructure to MachInst (#11599)

Wed, 03 Sep 2025 22:47:50 +0000

feat: add granular tail call detection infrastructure to MachInst (#11599)* feat: add granular tail call detection infrastructure to machinstAdds core infrastructure for distinguishing between regular calls andtail calls at the instruction level.* feat: implement call_type() method for all ISA backends* refactor: pass around function_calls enum instead of boolean* feat: add function_calls.update() logic List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

3fe9c3c7 - fix: accurate leaf detection (#11581)

Wed, 03 Sep 2025 15:57:55 +0000

fix: accurate leaf detection (#11581)* feat: add is_call() method to MachInst trait and VCode analysisAdd is_call() method to MachInst trait to enable accurate leaf functiondetection during register allocation. Update VCode compute_clobbers() toreturn (clobbers, is_leaf) tuple by analyzing actual call instructionsin machine code.* feat: implement is_call() method across all architecturesImplement is_call() method for all architecture-specific MachInstimplementations:- x64: Detects CallKnown, CallUnknown, ReturnCall variants, and TLScalls (ElfTlsGetAddr, MachOTlsGetAddr)- aarch64: Detects Call, CallInd, ReturnCall variants, and TLS calls(ElfTlsGetAddr, MachOTlsGetAddr)- riscv64: Detects Call, CallInd, ReturnCall variants, and ElfTlsGetAddr- s390x: Detects CallKnown, CallUnknown, ReturnCall variants- pulley: Detects Call, CallIndirect, ReturnCall variantsCo-authored-by: bjorn3 <17426603+bjorn3@users.noreply.github.com>* feat: improve leaf function detection and pass is_leaf to FrameLayout* test: add filetests for leaf detection* test: update expected outputs for accurate leaf function detection* test(riscv64): update filetests output---------Co-authored-by: bjorn3 <17426603+bjorn3@users.noreply.github.com> List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

0854775b - Couple of optimizations to the Cranelift incremental cache (#11186)

Tue, 08 Jul 2025 16:11:24 +0000

Couple of optimizations to the Cranelift incremental cache (#11186)* Fix a couple of comments* Remove flags.predicate_view()It is a remenant of the old backend framework.* Avoid string conversions for hashing the TargetIsa* Remove func_body_lenIt is identical to buffer.data.len()* Introduce IsaFlagsHashKey List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

90ac295e - Update Wasmtime to the 2024 Rust Edition (#10806)

Mon, 19 May 2025 16:40:55 +0000

Update Wasmtime to the 2024 Rust Edition (#10806)* Update Wasmtime to the 2024 Rust EditionNow that our MSRV supports the 2024 edition it's possible to make thisswitch. This commit moves Wasmtime to the 2024 Edition to keepup-to-date with Rust idioms and access many of the edition featuresexclusive to the 2024 edition.prtest:full* Reformat with the 2024 edition List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

5ded0f4e - Refactor call ABI implementation (#10722)

Tue, 06 May 2025 15:53:24 +0000

Refactor call ABI implementation (#10722)This refactors implementation of call ABI handling across architectureswith the goal of bringing s390x in line with other platforms.The main idea is to- handle main call instruction selection and generation in ISLE (like s390x but unlike other platforms today)- handle argument setup mostly outside of ISLE (like other platforms but unlike s390x today)- handle return value processing as part of the call instructio (like all platforms today)All platforms now emit the main call instruction directly from ISLE,which e.g. handles selection of the correct ISA instruction dependingon the call destination. This ISLE code calls out to helper routinesto handle argument and return value processing. These helpers aremostly common code and provided by the Callee and/or Lower layers,with some platform-specific additions via ISLE Context routines.The old CallSite abstraction is no longer needed; most of thedifferences between call and return_call handling disappear.(There is still a common-code CallInfo vs. a platform-specifcReturnCallInfo. At this point, it should be relatively straight-forward to make CallInfo platform-specific as well if desired,but this is not done here.)Some ISLE infrastructure for iterators / loops, which was onlyever used by the s390x argument processing code, has been removed.s390x now closely matches all other platforms, with only a fewspecial cases (slightly different tail-call ABI requires somedifferences in stack offset computations; we still need tohandle vector lane swaps for cross-ABI calls), which shouldsimplify future maintenance. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

5b63c874 - [DI] Fix live range tracking off-by-one confusions (#10570)

Tue, 15 Apr 2025 20:15:48 +0000

[DI] Fix live range tracking off-by-one confusions (#10570)* Dump blocks in the VL table* Add a test* Work around #10572 in tests* [DI] Fix live range tracking off-by-one confusionsHow things used to work w.r.t. instruction indices (IIs):1) In lowering: - Reversed order: IIs represented "before IP"s. - Block args were defined one instruction too late, but this issue was masked due to how RA allocates, at least in simple examples. - Execution order: IIs represented "after IP"s.2) In RA: - IIs represented "before IP"s. - Notice the mismatch.3) In emit: - RA directions w.r.t. the explicit ProgPoint positions were not respected and always treated as "after".How things work after this change:1) In lowering: - Reversed order: IIs represent "after IP"s. - Execution order: IIs represent "before IP"s.2) In RA: - No change; mismatch fixed.3) In emit: - ProgPoint positions now respected.This fixes various "silent bad debug info" issues. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

3da7fc8e - [DI] Dump value label assignments in a table (#10549)

Tue, 08 Apr 2025 19:42:14 +0000

[DI] Dump value label assignments in a table (#10549)* Dump compilation start/end* [DI] Log value label ranges in a tableSample table:|Inst |IP |VL0 |VL1 |VL3 |VL4 |VL5 |VL7 |VL10 |VL11 |VL4294967294||--------|----|--------|---------|---------|--------|--------|--------|---------|--------|------------||Inst 0 |53 | | | | | | | | | | | | | | | | | | ||Inst 1 |53 | | | | | | | | | | | | | | | | | | ||Inst 2 |60 |v194|p2i|v232|p12i| | | | | | | | | | | | |v192|p7i ||Inst 3 |64 |* |p2i|* |p12i|v231|p13i| | | | | | | | | | |* |p7i ||Inst 4 |68 |* |p2i|* |p12i|* |p13i| | | | | | | | | | |* |p7i ||Inst 5 |72 |* |p2i|* |p12i|* |p13i| | | | | | | | | | |* |p7i ||Inst 6 |76 |* |p2i|* |p12i|* |p13i| | | | | | | | | | |* |p7i ||Inst 7 |87 |* | |* |p12i|* |p13i| | | | | | | | | | |* |p7i ||Inst 8 |92 |* | |* |p12i|* |p13i|v227|p0i| | | | | | | | |* |p15i ||Inst 9 |94 |* | |v204| |v204| |v204| |v204| |v204| |v204| |v204| |* |p15i ||Inst 10 |100 |* | |* | |* | |* | |* | |* | |* | |* | |* |p15i ||Inst 11 |105 |* | |* | |* | |* | |v226|p9i|* | |* | |* | |* |p15i ||Inst 12 |109 |* | |* | |* | |* | |* | |v225|p9i|* | |* | |* |p15i ||Inst 13 |114 |* | |* | |* | |* | |* | |* | |* | |* | |* |p15i ||Inst 14 |119 |* | |* | |* | |* | |* | |* | |* | |* | |* |p15i ||Inst 15 |125 |* | |* | |* | |* | |* | |* | |* | |* | |* |p15i ||Inst 16 |129 |* | |* | |* | |* | |* | |* | |v223|p11i|* | |* |p15i ||Inst 17 |134 |* | |* | |* | |* | |* | |* | |* | |* | |* |p15i ||Inst 18 |134 |* | |* | |* | |* | |* | |* | |* | |* | |* |p15i ||Inst 19 |139 |* | |* | |* | |* | |* | |* | |* | |v222|p0i|* |p15i ||Inst 20 |143 |* | |* | |* | |* | |* | |* | |* | |* |p0i|* |p15i ||Inst 21 |143 |* | |* | |* | |* | |* | |* | |* | |* |p0i|* | |This will make it much easier to diagnose problems with incomplete/missing live ranges. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

94ec88ea - Cranelift: initial try_call / try_call_indirect (exception) support. (#10510)

Tue, 08 Apr 2025 00:02:16 +0000

Cranelift: initial try_call / try_call_indirect (exception) support. (#10510)* Cranelift: initial try_call / try_call_indirect (exception) support.This PR adds `try_call` and `try_call_indirect` instructions, andlowerings on four of five ISAs (x86-64, aarch64, riscv64, pulley; s390xhas its own non-shared ABI code that will need separate work).It extends CLIF to support these instructions as new kinds of branches,and extends block-calls to accept `retN` and `exnN` block-call args thatcarry the normal return values or exception payloads (respectively) intothe appropriate successor blocks.It wires up the "normal return path" so that it continues to work.It updates the ABI so that unwinding is possible without an initialregister state at throw: specifically, as per our RFC, all registers areclobbered. It also includes metadata in the `MachBuffer` that describesexception-catch destinations. However, no unwinder exists to interpretthese catch-destinations yet, so they are untested.* Add try_call_indirect lowering as well. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

a62b396f - Cranelift: remove return-value instructions after calls at callsites. (#10502)

Sat, 05 Apr 2025 05:01:13 +0000

Cranelift: remove return-value instructions after calls at callsites. (#10502)* Cranelift: remove return-value instructions after calls at callsites.This PR addresses the issues described in #10488 in a more head-onway: it removes the use of separate "return-value instructions" thatload return values from the stack, instead folding these loads intothe semantics of the call VCode instruction.This is a prerequisite for exception-handling: we need calls to beworkable as terminators, meaning that we cannot require anyother (VCode) instructions after the call to define the return values.In principle, this PR starts simply enough: the return-locations liston the `CallInfo` that each backend uses to provide regalloc metadatais updated to support a notion of "register or stack address" as thesource of each return value, and this list is now used for both kindsof returns, not just returns in registers. Shared code is defined in`machinst::abi` used by all backends to perform the requisite loads.In order to make this work with more defined values than fit inregisters, however, this PR also had to add support for"any"-constrained registers to Cranelift, and handling allocationsthat may be spillslots. This has always been supported by RA2, butthis is the first time that Cranelift uses them directly (previouslythey were used only internally in RA2 as lowerings from other kinds ofconstraints like safepoints). This requires encoding a spillslot indexin our `Reg` type.There is a little bit of complexity around handling the loads/defs aswell: if we have a return value on-stack, and we need to put it in aspillslot, we cannot do a memory-to-memory move directly, so we need atemporary register. Earlier versions of this PR allocated another tempas a vreg on the call, but this doesn't work with all callingconventions (too many clobbers). For simplicity I picked a particularregister that is (i) clobbered by calls and (ii) not used for returnvalues for each architecture (x86-64's tailcall needed to lose onereturn-in-register slot to make this work).This removes retval insts from the shared ABI infra completely. s390xis different, still, because it handles callsite lowering from ISLE;we will need to address that separately for exception support there.* Fix is_included_in_clobbers on aarch64: new defs must skip optimization.* Review feedback: add assert.* Review feedback: handle retval temp reg via ABI trait method.* Update is_clobbered_in_inst to affect only clobbers, not all defs. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

2af0a1f7 - Introduce log2_min_function_alignment flag (#10391)

Thu, 13 Mar 2025 22:55:43 +0000

Introduce log2_min_function_alignment flag (#10391)* Remove function_alignment handling from cranelift-object and cranelift-jitIt is already handled by MachBuffer. The symbol_alignment could also beremoved as no current backend has a symbol alignment bigger than thefunction alignment, but keeping it around is a bit safer when newbackends are introduced.* Introduce log2_min_function_alignment flagThis is required for cg_clif to implement -Zmin-function-alignment. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

392c7a96 - Cranelift/x64 backend: do not use one-way branches. (#10086)

Thu, 23 Jan 2025 02:30:01 +0000

Cranelift/x64 backend: do not use one-way branches. (#10086)* Cranelift/x64 backend: do not use one-way branches.In #9980, we saw that code copmiled with the single-pass registerallocator has incorrect behavior. We eventually narrowed this down tothe fact that the single-pass allocator is inserting code meant to beat the end of a block, just before its terminator, *between* twobranches that form the terminator sequence. The allocator is correct;the bug is with Cranelift's x64 backend.When we produce instructions into a VCode container, we maintain basicblocks, and we have the invariant (usual for basic block-based IR)that only the last -- terminator -- instruction is a branch that canleave the block. Even the conditional branches maintain thisinvariant: though VCode is meant to be "almost machine code", weemit *two-target conditionals* that are semantically like "jcond;jmp". We then are able to optimize this inline during binary emissionin the `MachBuffer`: the buffer knows about unconditional andconditional branches and will "chomp" branches off the tail of thebuffer whenever they target the fallthrough block. (We designed thesystem this way because it is simpler to think about BBs that areorder-invariant, i.e., not bake the "fallthrough" concept into theIR.) Thus we have a simpler abstraction but produce optimal terminatorsequences.Unfortunately, when adding a branch-on-floating-point-comparelowering, we had the need to branch to a target if either of *two*conditions were true, and rather than add a new kind of terminatorinstruction, we added a "one-armed branch": conditionally branch tolabel or fall through. We emitted this in sequence right before theactual terminator, so semantically it was almost equivalent.I write "almost" because the register allocator *is* allowed to insertspills/reloads/moves between any two instructions. Here the distinctpieces of the terminator sequence matter: the allocator might insertsomething just before the last instruction, assuming the basic-block"single in, single out" invariant means this will always run with theblock. With one-armed branches this is no longer true.The backtracking allocator (our original RA2 algorithm, and still thedefault today) will never insert code at the end of a block when ithas multiple terminators, because it associates such block-start/endinsertions with *edges*; so in such conditions it inserts instructionsinto the tops of successor blocks instead. But the single-passallocator needs to perform work at the end of every block, so it willtrigger this bug.This PR removes `JmpIf` and converts the br-of-fcmp lowering to use`JmpCondOr` instead, which is a pseudoinstruction that does `jcc1;jcc2; jmp`. This maintains the BB invariant and fixes the bug.Note that Winch still uses `JmpIf`, so we cannot remove it entirely:this PR renames it to `WinchJmpIf` instead, and adds a mechanism toassert failure if it is ever added to `VCode` (rather than emitteddirectly, as Winch's macro-assembler does). We could instead writeWinch's `jmp_if` assembler function in terms of `JmpCond` with afallthrough label that is immediately bound, and let the MachBufferalways chomp the jmp; I opted not to regress Winch compilerperformance by doing this. If one day we abstract out the assemblerfurther, we can remove `WinchJmpIf`.This is one of two instances of a "one-armed branch"; the other iss390x's `OneWayCondBr`, used in `br_table` lowerings, which we willaddress separately. Once we do, that will address #9980 entirely.* Add test for cascading branch-chomping behavior.* keep the paperclip happy List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

48f4621f - Run the full test suite on 32-bit platforms (#9837)

Wed, 15 Jan 2025 18:43:18 +0000

Run the full test suite on 32-bit platforms (#9837)* Run the full test suite on 32-bit platformsThis commit switches to running the full test suite in its entirety(`./ci/run-tests.sh`) on 32-bit platforms in CI in addition to 64-bitplatforms. This notably adds i686 and armv7 as architectures that aretested in CI.Lots of little fixes here and there were applied to a number of tests.Many tests just don't run on 32-bit platforms or a platform withoutCranelift support, and they've been annotated as such where necessary.Other tests were adjusted to run on all platforms a few minor bug fixesare here as well.prtest:full* Fix clippy warning* Get wasm code working by default on 32-bitDon't require the `pulley` feature opt-in on 32-bit platforms to getwasm code running.* Fix dead code warning* Fix build on armv7* Fix test assertion on armv7* Review comments* Update how tests are skipped* Change how Pulley is defaultedDefault to pulley in `build.rs` rather than in `Cargo.toml` to make iteasier to write down the condition and comment what's happening. Thismeans that the `pulley-interpreter` crate and pulley support inCranelift is always compiled in now and cannot be removed. This shouldhopefully be ok though as the `pulley-interpreter` crate is stillconditionally used (meaning it can get GC'd) and the code-size ofCranelift is not as important as the runtime itself.* pulley: Save/restore callee-save state on traps* Fewer clippy warnings about casts* Use wrapping_add in `g32_addr`, fixing arm test List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

1854929d - Update to regalloc2-0.10.0 (#9197)

Tue, 03 Sep 2024 17:02:22 +0000

Update to regalloc2-0.10.0 (#9197)* Reapply "Upgrade regalloc2 to 0.9.4 (#9191)" (#9193)This reverts commit 7081b8fc10f9909fd31fcc26da54badc2f00ad7a.* Upgrade to regalloc-0.10.0 List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs

7081b8fc - Revert "Upgrade regalloc2 to 0.9.4 (#9191)" (#9193)

Sat, 31 Aug 2024 15:54:13 +0000

Revert "Upgrade regalloc2 to 0.9.4 (#9191)" (#9193)This reverts commit 098430f3c8fd7bb92968402beef0670d08023fba. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/vcode.rs