Changes in valueregs.rs

0889323a - cranelift-codegen: rename most uses of std to core and alloc (#12237)

Sat, 03 Jan 2026 00:54:48 +0000

cranelift-codegen: rename most uses of std to core and alloc (#12237)* rename most std uses to core and alloc* cargo fmt List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/valueregs.rs

099102d9 - Remove `expect(clippy::allow_attributes_without_reason)` from cranelift-codegen (#11182)

Mon, 07 Jul 2025 17:25:40 +0000

Remove `expect(clippy::allow_attributes_without_reason)` from cranelift-codegen (#11182)* Remove `expect(clippy::allow_attributes_without_reason)` from cranelift-codegenThis commit gets around to migrating the `cranelift-codegen` crate torequire a reason on lint directives and additionally switch to`#[expect]` where possible.prtest:full* Move x64-only item to x64 backend List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/valueregs.rs

279334e7 - Couple of improvements to the abi handling code (part 3) (#9267)

Wed, 18 Sep 2024 15:11:32 +0000

Couple of improvements to the abi handling code (part 3) (#9267)* Add a couple assertions about misuse of StructReturn* Move STACK_ARG_RET_SIZE_LIMIT enforcement to SigSet::from_func_sig* Slightly simplify SigSet::abi_sig_for_sig_ref* Pass the return area pointer as first argument on sysv and fastcallThe SystemV and WindowsFastcall calling conventions expect the returnarea pointer as first argument on most archs, while the Tail and Winchcalling conventions expect it as last argument on all archs. On arm64 x8is used as return area pointer register. S390x already handledeverything correctly.* Explicitly annotate call conv to use in s390x user_stack_maps test* Fix windows_fastcall abi* Improve Debug impls for Reg and ValueRegs List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/valueregs.rs

0e9121da - Fix some typos (#8641)

Thu, 16 May 2024 23:21:22 +0000

Fix some typos (#8641)* occurred* winch typos* tests typos* cli typos* fuzz typos* examples typos* docs typos* crates/wasmtime typos* crates/environ typos* crates/cranelift typos* crates/test-programs typos* crates/c-api typos* crates/cache typos* crates other typos* cranelift/codegen/src/isa typos* cranelift/codegen/src other typos* cranelift/codegen other typos* cranelift other typos* ci js typo* .github workflows typo* RELEASES typo* Fix clang-format documentation line---------Co-authored-by: Andrew Brown List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/valueregs.rs

d180b907 - cranelift: Update operand aliases in-place (#8486)

Fri, 26 Apr 2024 16:33:18 +0000

cranelift: Update operand aliases in-place (#8486)Now all registers passed to the operand collector are mutably borroweddirectly out of their original locations in the Inst, so it is possibleto update them in place.As an initial demonstration of the utility of this change, the resultsof the VReg renamer are applied directly to the instructions duringoperand collection, and then all VReg aliases are cleared after operandcollection.Most of this commit consists of deleting noise from the many`get_operands` implementations in all the backends: most ampersands andasterisks, and all uses of the `ref` keyword. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/valueregs.rs

a0318f36 - Switch Cranelift over to regalloc2. (#3989)

Thu, 14 Apr 2022 17:28:21 +0000

Switch Cranelift over to regalloc2. (#3989)This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ``` List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/valueregs.rs

ca0e8d0a - Remove incomplete/unmaintained ARM32 backend (for now). (#3799)

Mon, 14 Feb 2022 23:03:52 +0000

Remove incomplete/unmaintained ARM32 backend (for now). (#3799)In #3721, we have been discussing what to do about the ARM32 backend in Cranelift. Currently, this backend supports only 32-bit types, which is insufficient for full Wasm-MVP; it's missing other critical bits, like floating-point support; and it has only ever been exercised, AFAIK, via the filetests for the individual CLIF instructions that are implemented. We were very very thankful for the original contribution of this backend, even in its partial state, and we had hoped at the time that we could eventually mature it in-tree until it supported e.g. Wasm and other use-cases. But that hasn't yet happened -- to the blame of no-one, to be clear, we just haven't had a contributor with sufficient time. Unfortunately, the existence of the backend and lack of active maintainer now potentially pose a bit of a burden as we hope to make continuing changes to the backend framework. For example, the ISLE migration, and the use of regalloc2 that it will allow, would need all of the existing lowering patterns in the hand-written ARM32 backend to be rewritten as ISLE rules. Given that we don't currently have the resources to do this, we think it's probably best if we, sadly, for now remove this partial backend. This is not in any way a statement of what we might accept in the future, though. If, in the future, an ARM32 backend updated to our latest codebase with an active maintainer were to appear, we'd be happy to merge it (and likewise for any other architecture!). But for now, this is probably the best path. Thanks again to the original contributor @jmkrauz and we hope that this work can eventually be brought back and reused if someone has the time to do so! List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/valueregs.rs

6c94eb82 - x86-64 Windows fastcall ABI support.

Tue, 23 Feb 2021 04:28:49 +0000

x86-64 Windows fastcall ABI support.This adds support for the "fastcall" ABI, which is the native C/C++ ABIon Windows platforms on x86-64. It is similar to but not exactly likeSystem V; primarily, its argument register assignments are different,and it requires stack shadow space.Note that this also adjusts the handling of multi-register values in theshared ABI implementation, and with this change, adjusts handling of`i128`s on *both* Fastcall/x64 *and* SysV/x64 platforms. This was doneto align with actual behavior by the "rustc ABI" on both platforms, asmapped out experimentally (Compiler Explorer link in comments). Thisbehavior is gated under the `enable_llvm_abi_extensions` flag.Note also that this does *not* add x64 unwind info on Windows. That willcome in a future PR (but is planned!). List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/valueregs.rs

6eea015d - Multi-register value support: framework for Values wider than machine regs.

Sun, 13 Dec 2020 04:48:56 +0000

Multi-register value support: framework for Values wider than machine regs.This will allow for support for `I128` values everywhere, and `I64`values on 32-bit targets (e.g., ARM32 and x86-32). It does not alter themachine backends to build such support; it just adds the framework forthe MachInst backends to *reason* about a `Value` residing in more thanone register. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/valueregs.rs