en Copyright 2015 Java http://172.16.0.5:8080/history/wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs#099102d9 Remove `expect(clippy::allow_attributes_without_reason)` from cranelift-codegen (#11182)* Remove `expect(clippy::allow_attributes_without_reason)` from cranelift-codegenThis commit gets around to migrating the `cranelift-codegen` crate torequire a reason on lint directives and additionally switch to`#[expect]` where possible.prtest:full* Move x64-only item to x64 backend List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs Mon, 07 Jul 2025 17:25:40 +0000 Alex Crichton <alex@alexcrichton.com> http://172.16.0.5:8080/history/wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs#f6a96125 Improve `atomic_rmw` lowering on `x86` (#9495) List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs Wed, 23 Oct 2024 21:51:21 +0000 beetrees <b@beetr.ee> http://172.16.0.5:8080/history/wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs#ba1a7120 Update Nightly Rust used in CI (#8211)* Update Nightly Rust used in CIAdditionally update `build-build-matrix.js` which I forgot in previousPRs.* Fix dead code warning List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs Thu, 21 Mar 2024 22:17:24 +0000 Alex Crichton <alex@alexcrichton.com> http://172.16.0.5:8080/history/wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs#df923f18 Remove MachInst::gen_constant (#5427)* aarch64: constant generation cleanup Add support for MOVZ and MOVN generation via ISLE. Handle f32const, f64const, and nop instructions via ISLE. No longer call Inst::gen_constant from lower.rs. * riscv64: constant generation cleanup Handle f32const, f64const, and nop instructions via ISLE. * s390x: constant generation cleanup Fix rule priorities for "imm" term. Only handle 32-bit stack offsets; no longer use load_constant64. * x64: constant generation cleanup No longer call Inst::gen_constant from lower.rs or abi.rs. * Refactor LowerBackend::lower to return InstOutput No longer write to the per-insn output registers; instead, return an InstOutput vector of temp registers holding the outputs. This will allow calling LowerBackend::lower multiple times for the same instruction, e.g. to rematerialize constants. When emitting the primary copy of the instruction during lowering, writing to the per-insn registers is now done in lower_clif_block. As a result, the ISLE lower_common routine is no longer needed. In addition, the InsnOutput type and all code related to it can be removed as well. * Refactor IsleContext to hold a LowerBackend reference Remove the "triple", "flags", and "isa_flags" fields that are copied from LowerBackend to each IsleContext, and instead just hold a reference to LowerBackend in IsleContext. This will allow calling LowerBackend::lower from within callbacks in src/machinst/isle.rs, e.g. to rematerialize constants. To avoid having to pass LowerBackend references through multiple functions, eliminate the lower_insn_to_regs subroutines in those targets that still have them, and just inline into the main lower routine. This also eliminates lower_inst.rs on aarch64 and riscv64. Replace all accesses to the removed IsleContext fields by going through the LowerBackend reference. * Remove MachInst::gen_constant This addresses the problem described in issue https://github.com/bytecodealliance/wasmtime/issues/4426 that targets currently have to duplicate code to emit constants between the ISLE logic and the gen_constant callback. After the various cleanups in earlier patches in this series, the only remaining user of get_constant is put_value_in_regs in Lower. This can now be removed, and instead constant rematerialization can be performed in the put_in_regs ISLE callback by simply directly calling LowerBackend::lower on the instruction defining the constant (using a different output register). Since the check for egraph mode is now no longer performed in put_value_in_regs, the Lower::flags member becomes obsolete. Care needs to be taken that other calls directly to the Lower::put_value_in_regs routine now handle the fact that no more rematerialization is performed. All such calls in target code already historically handle constants themselves. The remaining call site in the ISLE gen_call_common helper can be redirected to the ISLE put_in_regs callback. The existing target implementations of gen_constant are then unused and can be removed. (In some target there may still be further opportunities to remove duplication between ISLE and some local Rust code - this can be left to future patches.) List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs Tue, 13 Dec 2022 21:00:04 +0000 Ulrich Weigand <ulrich.weigand@de.ibm.com> http://172.16.0.5:8080/history/wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs#3a2b32bf Port branches to ISLE (AArch64) (#4943)* Port branches to ISLE (AArch64) Ported the existing implementations of the following opcodes for AArch64 to ISLE: - `Brz` - `Brnz` - `Brif` - `Brff` - `BrIcmp` - `Jump` - `BrTable` Copyright (c) 2022 Arm Limited * Remove dead code Copyright (c) 2022 Arm Limited List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs Mon, 26 Sep 2022 08:45:32 +0000 Damian Heaton <87125748+dheaton-arm@users.noreply.github.com> http://172.16.0.5:8080/history/wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs#532fb22a Cranelift: Remove the `LowerCtx` trait (#4697)The trait had only one implementation: the `Lower` struct. It is easier to just use that directly, and not introduce unnecessary layers of generics and abstractions. Once upon a time, there was hope that we would have other implementations of the `LowerCtx` trait, that did things like lower CLIF to SMTLIB for verification. However, this is not practical these days given the way that the trait has evolved over time, and our verification efforts are focused on ISLE now anyways, and we're actually making some progress on that front (much more than anyone ever did on a second `LowerCtx` trait implementation!) List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs Thu, 11 Aug 2022 23:54:17 +0000 Nick Fitzgerald <fitzgen@gmail.com> http://172.16.0.5:8080/history/wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs#8629cbc6 x64: port `atomic_rmw` to ISLE (#4389)* x64: port `atomic_rmw` to ISLE This change ports `atomic_rmw` to ISLE for the x64 backend. It does not change the lowering in any way, though it seems possible that the fixed regs need not be as fixed and that there are opportunities for single instruction lowerings. It does rename `inst_common::AtomicRmwOp` to `MachAtomicRmwOp` to disambiguate with the IR enum with the same name. * x64: remove remaining hardcoded register constraints for `atomic_rmw` * x64: use `SyntheticAmode` in `AtomicRmwSeq` * review: add missing reg collector for amode * review: collect memory registers in the 'late' phase List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs Wed, 06 Jul 2022 23:58:59 +0000 Andrew Brown <andrew.brown@intel.com> http://172.16.0.5:8080/history/wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs#ff22842d More atomic ops List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs Sun, 14 Feb 2021 10:42:28 +0000 bjorn3 <bjorn3@users.noreply.github.com> http://172.16.0.5:8080/history/wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs#712ff224 AArch64 SIMD: pattern-match load+splat into `LD1R` instruction. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs Sat, 07 Nov 2020 00:12:49 +0000 Chris Fallin <chris@cfallin.org> http://172.16.0.5:8080/history/wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs#a835c247 machinst: make get_output_reg target independent; List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs Tue, 08 Sep 2020 13:44:01 +0000 Benjamin Bouvier <public@benj.me> http://172.16.0.5:8080/history/wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs#620e4b4e This patch fills in the missing pieces needed to support wasm atomics on newBE/x64.It does this by providing an implementation of the CLIF instructions `AtomicRmw`, `AtomicCas`,`AtomicLoad`, `AtomicStore` and `Fence`.The translation is straightforward. `AtomicCas` is translated into x64 `cmpxchg`, `AtomicLoad`becomes a normal load because x64-TSO provides adequate sequencing, `AtomicStore` becomes anormal store followed by `mfence`, and `Fence` becomes `mfence`. `AtomicRmw` is the onlycomplex case: it becomes a normal load, followed by a loop which computes an updated value,tries to `cmpxchg` it back to memory, and repeats if necessary.This is a minimum-effort initial implementation. `AtomicRmw` could be implemented moreefficiently using LOCK-prefixed integer read-modify-write instructions in the case where the oldvalue in memory is not required. Subsequent work could add that, if required.The x64 emitter has been updated to emit the new instructions, obviously. The `LegacyPrefix`mechanism has been revised to handle multiple prefix bytes, not just one, since it is nowsometimes necessary to emit both 0x66 (Operand Size Override) and F0 (Lock).In the aarch64 implementation of atomics, there has been some minor renaming for the sake ofclarity, and for consistency with this x64 implementation. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/inst_common.rs Thu, 20 Aug 2020 05:36:19 +0000 Julian Seward <jseward@acm.org>