Changes in compile.rs

2f7dbd61 - PCC: remove proof-carrying code (for now?). (#12800)

Tue, 31 Mar 2026 04:36:33 +0000

PCC: remove proof-carrying code (for now?). (#12800)In late 2023, we built out an experimental feature calledProof-Carrying Code (PCC), where we attached "facts" to values in theCLIF IR and built verification of these facts after lowering tomachine instructions. We also added "memory types" describing layoutof memory and a "checked" flag on memory operations such that we couldverify that any checked memory operation accessed valid memory (asdefined by memory types attached to pointer values viafacts). Wasmtime's Cranelift backend then put appropriate memory typesand facts in its IR such that all accesses to memory (aspirationally)could be checked, taking the whole mid-end and lowering backend ofCranelift out of the trusted core that enforces SFI.This basically worked, at the time, for static memories; but never fordynamic memories, and then work on the feature lostprioritization (aka I had to work on other things) and I wasn't ableto complete it and put it in fuzzing/enable it as a production option.Unfortunately since then it has bit-rotted significantly -- as we addnew backend optimizations and instruction lowerings we haven't keptthe PCC framework up to date.Inspired by the discussion in #12497 I think it's time to deleteit (hopefully just "for now"?) unless/until we can build it again. Andwhen we do that, we should probably get it to the point of validatingrobust operation on all combinations of memory configurations beforemerging. (That implies a big experiment branch rather than a bunch ofeager PRs in-tree, but so it goes.) I still believe it is possible tobuild this (and I have ideas on how to do it!) but not right now. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

76911c29 - Partial support for no_std in cranelift_codegen (#12222)

Wed, 07 Jan 2026 16:41:32 +0000

Partial support for no_std in cranelift_codegen (#12222)* Move most things from std to core and alloc* Port assembler_x64 to no_std* before adding prelude to each file* Most of the files now work with no_std* update isle to use alloc and core* some instances shouldn't have been renamed, fixes cargo test* add cranelift-assembler-x64 (no_std) to CI* fix codegen_meta, missed one spot with std::slice* automatically remove prelude with cargo fix* update isle changes* update assembler changes* update assembler changes* use latest codegen changes + fix FxHash problem* add imports* fix floating issues with libm* remove unused import* temporarily remove OnceLock* add no_std arm support and add it into CI* Move most things from std to core and alloc* Port assembler_x64 to no_std* before adding prelude to each file* Most of the files now work with no_std* update isle to use alloc and core* some instances shouldn't have been renamed, fixes cargo test* add cranelift-assembler-x64 (no_std) to CI* automatically remove prelude with cargo fix* update isle changes* update assembler changes* update assembler changes* use latest codegen changes + fix FxHash problem* add imports* fix floating issues with libm* remove unused import* temporarily remove OnceLock* add no_std arm support and add it into CI* Move most things from std to core and alloc* Port assembler_x64 to no_std* before adding prelude to each file* Most of the files now work with no_std* update isle to use alloc and core* add cranelift-assembler-x64 (no_std) to CI* automatically remove prelude with cargo fix* update isle changes* update assembler changes* use latest codegen changes + fix FxHash problem* add imports* fix floating issues with libm* temporarily remove OnceLock* add no_std arm support and add it into CI* revert Cargo.toml formating* remove prelude and fix cargo.toml* cargo fmt* remove empty lines* bad renames* macro_use only on no_std* revert OnceLock change* only use stable libm features* update regalloc2* update comment* use continue instead* Update vets---------Co-authored-by: Alex Crichton List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

73de2ee9 - Pull in new regalloc2 with fastalloc fixes for exceptions, and re-enable and add to testing. (#11533)

Mon, 25 Aug 2025 19:22:21 +0000

Pull in new regalloc2 with fastalloc fixes for exceptions, and re-enable and add to testing. (#11533)* Revert "Cranelift/Wasmtime: disable fastalloc (single-pass) allocator for now. (#10554)"This reverts commit d52e23b09191185996792b8ef18e5fca2865ca43.* Upgrade to regalloc2 0.13.1.Pulls in bytecodealliance/regalloc2#233 to update fastalloc to supportthe looser constraints needed by exception-related changes.* cargo-vet update. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

2bac6574 - Update the `log` dependency (#11197)

Mon, 07 Jul 2025 23:25:45 +0000

Update the `log` dependency (#11197)* Update the `log` dependencyThis enables getting warnings about formatting strings in the `log`crate directives which are then additionally fixed here as well.* Update dependency directive in `Cargo.toml` List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

90ac295e - Update Wasmtime to the 2024 Rust Edition (#10806)

Mon, 19 May 2025 16:40:55 +0000

Update Wasmtime to the 2024 Rust Edition (#10806)* Update Wasmtime to the 2024 Rust EditionNow that our MSRV supports the 2024 edition it's possible to make thisswitch. This commit moves Wasmtime to the 2024 Edition to keepup-to-date with Rust idioms and access many of the edition featuresexclusive to the 2024 edition.prtest:full* Reformat with the 2024 edition List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

5ded0f4e - Refactor call ABI implementation (#10722)

Tue, 06 May 2025 15:53:24 +0000

Refactor call ABI implementation (#10722)This refactors implementation of call ABI handling across architectureswith the goal of bringing s390x in line with other platforms.The main idea is to- handle main call instruction selection and generation in ISLE (like s390x but unlike other platforms today)- handle argument setup mostly outside of ISLE (like other platforms but unlike s390x today)- handle return value processing as part of the call instructio (like all platforms today)All platforms now emit the main call instruction directly from ISLE,which e.g. handles selection of the correct ISA instruction dependingon the call destination. This ISLE code calls out to helper routinesto handle argument and return value processing. These helpers aremostly common code and provided by the Callee and/or Lower layers,with some platform-specific additions via ISLE Context routines.The old CallSite abstraction is no longer needed; most of thedifferences between call and return_call handling disappear.(There is still a common-code CallInfo vs. a platform-specifcReturnCallInfo. At this point, it should be relatively straight-forward to make CallInfo platform-specific as well if desired,but this is not done here.)Some ISLE infrastructure for iterators / loops, which was onlyever used by the s390x argument processing code, has been removed.s390x now closely matches all other platforms, with only a fewspecial cases (slightly different tail-call ABI requires somedifferences in stack offset computations; we still need tohandle vector lane swaps for cross-ABI calls), which shouldsimplify future maintenance. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

d52e23b0 - Cranelift/Wasmtime: disable fastalloc (single-pass) allocator for now. (#10554)

Wed, 09 Apr 2025 00:14:27 +0000

Cranelift/Wasmtime: disable fastalloc (single-pass) allocator for now. (#10554)Unfortunately, as discovered by a recent fuzzbug [1], the single-passregister allocator is not compatible with the approach to callsitedefs that exception-handling support has forced us to take. Inparticular, we needed to move all call return-value defs onto the callinstruction itself, so calls could be terminators; this unboundednumber of defs is made to be a solvable allocation problem by using`any` constraints, which allow allocation directly into spillslots;but fastalloc appears to error out if it runs out of registers,regardless of this constraint.Long-term, we should fix this, but unfortunately I don't have cyclesto dive into fastalloc's internals at the moment, and it's (I think) atier-3 feature. As such, this PR disables its use for now. I'vefiled a tracking issue in RA2 [2], and referenced this in theCranelift configuration option docs at least.To keep from shifting all fuzzbugs / fuzzing corpii by altering the`arbitrary` interpretation, I opted to keep the enum the same in thefuzzing crate, and remap `SinglePass` to `Backtracking` there. I'mhappy to take the other approach and remove the option (thusinvalidating all fuzzbugs) if we'd prefer that instead.[1]: https://oss-fuzz.com/testcase-detail/5433312476987392[2]: https://github.com/bytecodealliance/regalloc2/issues/217 List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

1e3e5fc1 - Cranelift: add option to use new single-pass register allocator. (#9611)

Fri, 15 Nov 2024 17:58:31 +0000

Cranelift: add option to use new single-pass register allocator. (#9611)* Cranelift: add option to use new single-pass register allocator.In bytecodealliance/regalloc2#181, @d-sonuga added a fast single-passalgorithm option to regalloc2, in addition to its existing backtrackingallocator. This produces code much more quickly, at the expense of codequality. Sometimes this tradeoff is desirable (e.g. when performing adebug build in a fast-iteration development situation, or in an initialJIT tier).This PR adds a Cranelift option to select the RA2 algorithm, plumbs itthrough to a Wasmtime option, and adds the option to Wasmtime fuzzing aswell.An initial compile-time measurement in Wasmtime: `spidermonkey.wasm`builds in 1.383s with backtracking (existing algorithm), and 1.065s withsingle-pass. The resulting binary runs a simple Fibonacci benchmark in2.060s with backtracking vs. 3.455s with single-pass.Hence, the single-pass algorithm yields a 23% compile-time reduction, atthe cost of a 67% runtime increase.* cargo-vet audit for allocator-api2 0.2.18 -> 0.2.20. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

f262c311 - PCC: support x86-64. (#7352)

Thu, 26 Oct 2023 19:27:30 +0000

PCC: support x86-64. (#7352)* PCC: support x86-64.This PR extends the proof-carrying-code infrastructure to support x86-64as well as aarch64. In the process, many of the mechanisms had to bemade a little more general.One important change is that the PCC leaves more "breadcrumbs" on thefrontend now, avoiding the need for magic handling of facts on constantvalues, etc., in the backend. For the first time a lowering rule alsogains the ability to add a fact to a vreg to preserve the chain as well.With these changes, we can validate compilation of SpiderMonkey.wasmwith Wasm static memories on x86-64 and aarch64:```cfallin@fastly2:~/work/wasmtime% target/release/wasmtime compile -C pcc=yes --target x86_64 ../wasm-tests/spidermonkey.wasmcfallin@fastly2:~/work/wasmtime% target/release/wasmtime compile -C pcc=yes --target aarch64 ../wasm-tests/spidermonkey.wasmcfallin@fastly2:~/work/wasmtime%```* Don't run regalloc checker if not requested in addition to PCC; it's fairly expensive.* Refactor x64 PCC code to avoid deep pattern matches on Gpr/Xmm types; explicitly match every instruction kind. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

8d19280a - PCC: draw the rest of the owl: fully-working PCC on hello-world Wasm on aarch64 (#7281)

Thu, 19 Oct 2023 19:54:44 +0000

PCC: draw the rest of the owl: fully-working PCC on hello-world Wasm on aarch64 (#7281)* PCC: draw the rest of the owl: fully-working PCC on hello-world Wasm on aarch64This needed a bit more inference / magic than I was hoping for at first,specifically around constants and adds. Some instructions can nowgenerate facts on their output registers, even if not stated. Thisbreaks away from the "breadcrumbs" idea, but seems to be the mostpractical solution to a general problem that we have mini-lowering stepsin various places without careful preservation of PCC facts. Twoparticular aspects:- Constants: amodes on aarch64 can decompose into new constant-generation instructions, and we need precise ranges on those to properly check them. To avoid making the ISLE rules nightmarish, it's best to reuse the existing semantics definitions of the Add* ALU insts, and add a few rules for MovK/MovZ/MovN.- Adds: similarly, amodes decompose into de-novo add instructions with no facts. To handle this, there's now a notion of "propagating" facts that cause an instruction with a propagating fact on the input to generate a fact on the output.Together, these heuristics mean that we'll eagerly generate a fact for`mem(mt0, 0, 0) + 8 -> mem(mt0, 8, 8)`, but we won't, for example,generate ranges on every single integer operation.With these changes and a few other misc fixes, this PR can now check anontrivial "hello world" Wasm on aarch64 down to the machine-code level:```$ target/release/wasmtime compile -C enable-pcc=y ../wasm-tests/helloworld-rs.wasm```* Review feedback. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

fef8a90f - PCC: add semantics for core add/shift/extend/amode ops on AArch64. (#7180)

Sat, 07 Oct 2023 01:42:53 +0000

PCC: add semantics for core add/shift/extend/amode ops on AArch64. (#7180)* PCC: add semantics for core add/shift/extend/amode ops on AArch64.This PR adds verification of facts on values produced by adds, shifts,and extends on AArch64, handling the various combination instructions(adds with builtin extends or shifts, for example), and also addsverification of all addressing modes, including those with builtinextends and shifts.It also splits the test suite into"succeed" and "fail" sets, andprovides cases that PCC should catch.* Review feedback. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

f466aa26 - Skeleton and initial support for proof-carrying code. (#7165)

Fri, 06 Oct 2023 22:31:23 +0000

Skeleton and initial support for proof-carrying code. (#7165)* WIP veriwasm 2.0Co-Authored-By: Chris Fallin * PCC: successfully parse some simple facts.Co-authored-by: Nick Fitzgerald * PCC: plumb facts through VCode and add framework on LowerBackend to check them.Co-authored-by: Nick Fitzgerald * PCC: code is carrying some proofs! Very simple test-case.Co-authored-by: Nick Fitzgerald * PCC: add a `safe` flag for checked memory accesses.* PCC: add pretty-printing of facts to CLIF output.* PCC: misc. cleanups.* PCC: lots of cleanup.* Post-rebase fixups and some misc. fixes.* Add serde traits to facts.* PCC: add succeed and fail tests.* Review feedback: rename `safe` memflag to `checked`.* Review feedback.---------Co-authored-by: Nick Fitzgerald List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

5c8a603a - Make MachineEnv a per-ABI property (#6957)

Tue, 12 Sep 2023 19:17:53 +0000

Make MachineEnv a per-ABI property (#6957)The MachineEnv structure contains the allocatable and preferredregister sets. This is currently fixed per TargetIsa - however,conceptually these register sets can differ between ABIs on thesame ISA.To allow for this, replace the TargetIsa machine_env routine withan ABIMachineSpec get_machine_env routine. To ensure the structureis still only allocated once, cache it via static OnceLock variables.No functional change intended. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

9fcdc7a6 - fuzz: Insert random instructions (#6407)

Thu, 01 Jun 2023 16:04:34 +0000

fuzz: Insert random instructions (#6407)* Fix fuel consumption of ControlPlane::shuffleCo-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser * Insert random instructions during loweringCo-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser * add documentation for get_arbitraryCo-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser * Fix zero-sized version of get_arbitraryCo-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser * Insert ints and floatsCo-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser * fix inserting of floatsCo-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser * improve abstraction of MachInst::gen_imm_f64Co-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser ---------Co-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

fde6c6f5 - fuzz: randomize block lowering order (#6254)

Tue, 02 May 2023 16:20:39 +0000

fuzz: randomize block lowering order (#6254)* fuzz: randomize block lowering orderCo-authored-by: Moritz Waser Co-authored-by: Remo Senekowitsch * fix block lowering order randomizationCo-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser * simplify control plane internalsCo-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser * avoid unnecessary allocationsCo-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser * remove unused change_order functionCo-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser * add arbitrary 1.3.0 to cargo vet imports lockCo-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser * optimize ControlPlane::shuffleCo-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser * clarify shuffle being a noop without chaos modeCo-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser * reorder only direct successors of a blockCo-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser * rename get_permutation -> shuffledCo-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser ---------Co-authored-by: Falk Zwimpfer <24669719+FalkZ@users.noreply.github.com>Co-authored-by: Moritz Waser List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

8abfe928 - Reuse the DominatorTree postorder travesal in BlockLoweringOrder (#5843)

Thu, 23 Feb 2023 22:05:20 +0000

Reuse the DominatorTree postorder travesal in BlockLoweringOrder (#5843)* Rework the blockorder module to reuse the dom tree's cfg postorder* Update domtree tests* Treat br_table with an empty jump table as multiple block exits* Bless tests* Change branch_idx to succ_idx and fix the comment List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

df923f18 - Remove MachInst::gen_constant (#5427)

Tue, 13 Dec 2022 21:00:04 +0000

Remove MachInst::gen_constant (#5427)* aarch64: constant generation cleanup Add support for MOVZ and MOVN generation via ISLE. Handle f32const, f64const, and nop instructions via ISLE. No longer call Inst::gen_constant from lower.rs. * riscv64: constant generation cleanup Handle f32const, f64const, and nop instructions via ISLE. * s390x: constant generation cleanup Fix rule priorities for "imm" term. Only handle 32-bit stack offsets; no longer use load_constant64. * x64: constant generation cleanup No longer call Inst::gen_constant from lower.rs or abi.rs. * Refactor LowerBackend::lower to return InstOutput No longer write to the per-insn output registers; instead, return an InstOutput vector of temp registers holding the outputs. This will allow calling LowerBackend::lower multiple times for the same instruction, e.g. to rematerialize constants. When emitting the primary copy of the instruction during lowering, writing to the per-insn registers is now done in lower_clif_block. As a result, the ISLE lower_common routine is no longer needed. In addition, the InsnOutput type and all code related to it can be removed as well. * Refactor IsleContext to hold a LowerBackend reference Remove the "triple", "flags", and "isa_flags" fields that are copied from LowerBackend to each IsleContext, and instead just hold a reference to LowerBackend in IsleContext. This will allow calling LowerBackend::lower from within callbacks in src/machinst/isle.rs, e.g. to rematerialize constants. To avoid having to pass LowerBackend references through multiple functions, eliminate the lower_insn_to_regs subroutines in those targets that still have them, and just inline into the main lower routine. This also eliminates lower_inst.rs on aarch64 and riscv64. Replace all accesses to the removed IsleContext fields by going through the LowerBackend reference. * Remove MachInst::gen_constant This addresses the problem described in issue https://github.com/bytecodealliance/wasmtime/issues/4426 that targets currently have to duplicate code to emit constants between the ISLE logic and the gen_constant callback. After the various cleanups in earlier patches in this series, the only remaining user of get_constant is put_value_in_regs in Lower. This can now be removed, and instead constant rematerialization can be performed in the put_in_regs ISLE callback by simply directly calling LowerBackend::lower on the instruction defining the constant (using a different output register). Since the check for egraph mode is now no longer performed in put_value_in_regs, the Lower::flags member becomes obsolete. Care needs to be taken that other calls directly to the Lower::put_value_in_regs routine now handle the fact that no more rematerialization is performed. All such calls in target code already historically handle constants themselves. The remaining call site in the ISLE gen_call_common helper can be redirected to the ISLE put_in_regs callback. The existing target implementations of gen_constant are then unused and can be removed. (In some target there may still be further opportunities to remove duplication between ISLE and some local Rust code - this can be left to future patches.) List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

c5379051 - Enable the ssa verifier in debug builds (#5354)

Wed, 07 Dec 2022 20:22:51 +0000

Enable the ssa verifier in debug builds (#5354)Enable regalloc2's SSA verifier in debug builds to check for any outstanding reuse of virtual registers in def constraints. As fuzzing enables debug_assertions, this will enable the SSA verifier when fuzzing as well. List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

58a5089e - Cranelift: log number of CLIF insts/blocks to optimize/lower (#5333)

Mon, 28 Nov 2022 19:35:29 +0000

Cranelift: log number of CLIF insts/blocks to optimize/lower (#5333) List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs

6fe69d00 - Cranelift: add debug logs counting how many vcode instructions and blocks we lower to (#5332)

Mon, 28 Nov 2022 18:57:02 +0000

Cranelift: add debug logs counting how many vcode instructions and blocks we lower to (#5332) List of files: /wasmtime-44.0.1/cranelift/codegen/src/machinst/compile.rs