Changes in mod.rs

bac0e78f - aarch64: Disable csdb emission by default (#12932)

Wed, 01 Apr 2026 22:16:55 +0000

aarch64: Disable csdb emission by default (#12932)* aarch64: Disable csdb emission by defaultThis has a massive performance penalty on macOS, for example, and peercompilers are not emitting this as part of on-by-default mitigations.This commit preserves the option to emit it with an aarch64-specific`use_csdb` flag, but the default is now `false` meaning that this is notemitted by default.Closes #12789* Fix tests* Fix tests & review comments* Use ISLE rule introduced List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

2f7dbd61 - PCC: remove proof-carrying code (for now?). (#12800)

Tue, 31 Mar 2026 04:36:33 +0000

PCC: remove proof-carrying code (for now?). (#12800)In late 2023, we built out an experimental feature calledProof-Carrying Code (PCC), where we attached "facts" to values in theCLIF IR and built verification of these facts after lowering tomachine instructions. We also added "memory types" describing layoutof memory and a "checked" flag on memory operations such that we couldverify that any checked memory operation accessed valid memory (asdefined by memory types attached to pointer values viafacts). Wasmtime's Cranelift backend then put appropriate memory typesand facts in its IR such that all accesses to memory (aspirationally)could be checked, taking the whole mid-end and lowering backend ofCranelift out of the trusted core that enforces SFI.This basically worked, at the time, for static memories; but never fordynamic memories, and then work on the feature lostprioritization (aka I had to work on other things) and I wasn't ableto complete it and put it in fuzzing/enable it as a production option.Unfortunately since then it has bit-rotted significantly -- as we addnew backend optimizations and instruction lowerings we haven't keptthe PCC framework up to date.Inspired by the discussion in #12497 I think it's time to deleteit (hopefully just "for now"?) unless/until we can build it again. Andwhen we do that, we should probably get it to the point of validatingrobust operation on all combinations of memory configurations beforemerging. (That implies a big experiment branch rather than a bunch ofeager PRs in-tree, but so it goes.) I still believe it is possible tobuild this (and I have ideas on how to do it!) but not right now. List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

0e51666b - CI: Add a check for cranelift-codegen (only x86 and aarch64) on no_std tagets (#12812)

Tue, 24 Mar 2026 20:57:57 +0000

CI: Add a check for cranelift-codegen (only x86 and aarch64) on no_std tagets (#12812)* CI: Add a check for cranelift-codegen (only x86 and aarch64) on no_std tagets* Change -F to --features* Fix CI: remove unused imports when building without unwind* Cargo fmt List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

7ac4b818 - S390x: emit new instructions added in z17 (#12319)

Tue, 03 Feb 2026 18:51:07 +0000

S390x: emit new instructions added in z17 (#12319)* s390x: Emit instructions from MIE4 & VXRS_EXT3 on z17This emits & tests a bunch of instructions: * from Miscellaneous-Instruction-Extensions Facility 4: * CLZ, 64bit * CTZ, 64bit * from Vector-Enhancements Facility 3: * 32x4, 64x2 & 128x1 variants of the following: * Divide * Remainder * 64x2 & 128x1 multiply variants * 128x1 vaiants of: * Compare * CLZ * CTZ * Max * Min * Average * Negation * EvaluateCo-authored-by: Jimmy Brisson * s390x: Emit vector blend on z17* Rename x86_blendv to blendvNow that s390x implements blendv as well, we should refer tothe instruction without the x86 prefix.---------Co-authored-by: Ulrich Weigand List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

0889323a - cranelift-codegen: rename most uses of std to core and alloc (#12237)

Sat, 03 Jan 2026 00:54:48 +0000

cranelift-codegen: rename most uses of std to core and alloc (#12237)* rename most std uses to core and alloc* cargo fmt List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

a3d6e407 - Cranelift: add debug tag infrastructure. (#11768)

Mon, 06 Oct 2025 19:38:03 +0000

Cranelift: add debug tag infrastructure. (#11768)* Cranelift: add debug tag infrastructure.This PR adds *debug tags*, a kind of metadata that can attach to CLIFinstructions and be lowered to VCode instructions and as metadata onthe produced compiled code. It also adds opaque descriptor blobscarried with stackslots. Together, these two features allow decoratingIR with first-class debug instrumentation that is properly preservedby the compiler, including across optimizations andinlining. (Wasmtime's use of these features will come in followupPRs.)The key idea of a "debug tag" is to allow the Cranelift embedder toexpress whatever information it needs to, in a format that is opaqueto Cranelift itself, except for the parts that need translation duringlowering. In particular, the `DebugTag::StackSlot` variant getstranslated to a physical offset into the stackframe in the compiledmetadata output. So, for example, the embedder can emit a tagreferring to a stackslot, and another describing an offset in thatstackslot.The debug tags exist as a *sequence* on any given instruction; themeaning of the sequence is known only to the embedder, *except* thatduring inlining, the tags for the inlining call instruction areprepended to the tags of inlined instructions. In this way, acanonical use-case of tags as describing original source-languageframes can preserve the source-language view even when multiplefunctions are inlined into one.The descriptor on a stackslot may look a little odd at first, but itspurpose is to allow serializing some description ofstackslot-contained runtime user-program data, in a way that is firmlyattached to the stackslot. In particular, in the face of inlining,this descriptor is copied into the inlining (parent) function from theinlined function when the stackslot entity is copied; no othermetadata outside Cranelift needs to track the identity of stackslotsand know about that motion. This fits nicely with the ability of tagsto refer to stackslots; together, the embedder can annotateinstructions as having certain state in stackslots, and describe theformat of that state per stackslot.This infrastructure is tested with some compile-tests now;testing of the interpretation of the metadata output will come withend-to-end debug instrumentation tests in a followup PR.* Review feedback: add back sequence points and enforce tags only on sequence points or calls.* Use Vecs for debug metadata in MachBuffer to avoid SmallVec size penalty in not-used case.* Review feedback: switch from inlined stackslot descriptor blobs to u64 keys. List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

0854775b - Couple of optimizations to the Cranelift incremental cache (#11186)

Tue, 08 Jul 2025 16:11:24 +0000

Couple of optimizations to the Cranelift incremental cache (#11186)* Fix a couple of comments* Remove flags.predicate_view()It is a remenant of the old backend framework.* Avoid string conversions for hashing the TargetIsa* Remove func_body_lenIt is identical to buffer.data.len()* Introduce IsaFlagsHashKey List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

2bac6574 - Update the `log` dependency (#11197)

Mon, 07 Jul 2025 23:25:45 +0000

Update the `log` dependency (#11197)* Update the `log` dependencyThis enables getting warnings about formatting strings in the `log`crate directives which are then additionally fixed here as well.* Update dependency directive in `Cargo.toml` List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

90ac295e - Update Wasmtime to the 2024 Rust Edition (#10806)

Mon, 19 May 2025 16:40:55 +0000

Update Wasmtime to the 2024 Rust Edition (#10806)* Update Wasmtime to the 2024 Rust EditionNow that our MSRV supports the 2024 edition it's possible to make thisswitch. This commit moves Wasmtime to the 2024 Edition to keepup-to-date with Rust idioms and access many of the edition featuresexclusive to the 2024 edition.prtest:full* Reformat with the 2024 edition List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

ee275a89 - Switch to using Wasmtime-style builtins for ceil, floor, etc. (#10657)

Thu, 24 Apr 2025 05:06:05 +0000

Switch to using Wasmtime-style builtins for ceil, floor, etc. (#10657)* Switch to using Wasmtime-style builtins for ceil, floor, etc.With this patch, all emitted calls are Wasmtime-style builtins, ratherthan Cranelift-style libcalls. This ensures that all calls fromCranelift-generated code into Wasmtime host code use the same mechanism,and eliminates the relocation handling code for the libcall mechanism.* Update tests.* Avoid using x86_pshufb on non-x86 platforms.* Revert unneeded f32/f64 changes in Pulley.* Define i8x16 as an unconstructible type if sse isn't available.* Delete the setters too.* Fix f32/f64 setters.* Test with prtest:full.prtest:full* Support fma.* Return true for `has_native_fma` on pulley.This works because pulley already has code implementing fma. This avoidsneeding to marshal f32x4 values into builtin function calls on pulley.* Update tests. List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

1e6d533e - Fix argument extension on riscv64 for Wasmtime builtins (#10069)

Thu, 23 Jan 2025 15:21:48 +0000

Fix argument extension on riscv64 for Wasmtime builtins (#10069)* Fix argument extension on riscv64 for Wasmtime builtinsThis commit fixes a crash found in the CI of #10040. That PR itselfisn't the fault per-se but rather uncovered a preexisting issue onriscv64. According to riscv64's ABI docs it looks like arguments are allexpected to be sign-extended, whereas currently in Wasmtime all hostsignatures are zero-extended on all platforms. This commit applies twochanges to fix this:* A new `TargetIsa::default_argument_extension` method was added which is now used instead of unconditionally using `uext` to apply to all arguments/results.* While I was here I went ahead and split apart things where the wasm signature of a builtin doesn't use `uext` or `sext`. The host signature still does, however, which means that any extension necessary happens in the trampoline we generate per-libcall as opposed to at all callsites.I'm not certain that all platforms require `uext` but I've left the`TargetIsa` implementation as `uext` for now with a comment explainingwhy. Currently the only non-`uext` platforms are riscv64, which is`sext` to fix the issue from #10040, and Pulley which is "none" asthings work differently there.* Update test expectations List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

1c521e17 - [DWARF] Add logging to range building (#9969)

Tue, 14 Jan 2025 21:01:45 +0000

[DWARF] Add logging to range building (#9969) List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

f247a75b - Update to target-lexicon 0.13.0 (#9752)

Fri, 06 Dec 2024 17:45:40 +0000

Update to target-lexicon 0.13.0 (#9752)* Update to target-lexicon 0.13.0Pulling in bytecodealliance/target-lexicon#115 to lay the foundation forsome big-endian work in Pulley* Fix more compile errors List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

4e50ecc6 - Implement unwind support for ARM64 Windows (#9266)

Thu, 19 Sep 2024 16:39:14 +0000

Implement unwind support for ARM64 Windows (#9266) List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

bdd78422 - Wasmtime: Implement the custom-page-sizes proposal (#8763)

Wed, 12 Jun 2024 21:46:42 +0000

Wasmtime: Implement the custom-page-sizes proposal (#8763)* Wasmtime: Implement the custom-page-sizes proposalThis commit adds support for the custom-page-sizes proposal to Wasmtime:https://github.com/WebAssembly/custom-page-sizesI've migrated, fixed some bugs within, and extended the `*.wast` tests for thisproposal from the `wasm-tools` repository. I intend to upstream them into theproposal shortly.There is a new `wasmtime::Config::wasm_custom_page_sizes_proposal` method toenable or disable the proposal. It is disabled by default.Our fuzzing config has been updated to turn this feature on/off as dictated bythe arbitrary input given to us from the fuzzer.Additionally, there were getting to be so many constructors for`wasmtime::MemoryType` that I added a builder rather than add yet anotherconstructor.In general, we store the `log2(page_size)` rather than the page sizedirectly. This helps cut down on invalid states and properties we need toassert.I've also intentionally written this code such that supporting any power of twopage size (rather than just the exact values `1` and `65536` that are currentlyvalid) will essentially just involve updating `wasmparser`'s validation andremoving some debug asserts in Wasmtime.* Update error string expectation* Remove debug logging* Use a right shift instead of a division* fix error message expectation again* remove page size from VMMemoryDefinition* fix size of VMMemoryDefinition again* Only dynamically check for `-1` sentinel for 1-byte page sizes* Import functions that are used a few times* Better handle overflows when rounding up to the host page sizePropagate errors instead of returning a value that is not actually a rounded upversion of the input.Delay rounding up various config sizes until runtime instead of eagerly doing itat config time (which isn't even guaranteed to work, so we already had to have abackup plan to round up at runtime, since we might be cross-compiling wasm ornot have the runtime feature enabled).* Fix some anyhow and nostd errors* Add missing rounding up to host page size at runtime* Add validate feature to wasmparser dep* Add some new rounding in a few places, due to no longer rounding in config methods* Avoid actually trying to allocate the whole address space in the `massive_64_bit_still_limited` testThe point of the test is to ensure that we hit the limiter, so just cancel theallocation from the limiter, and otherwise avoid MIRI attempting to allocate abunch of memory after we hit the limiter.* prtest:full* Revert "Avoid actually trying to allocate the whole address space in the `massive_64_bit_still_limited` test"This reverts commit ccfa34a78dd3d53e49a6158ca03077d42ce8bcd7.* miri: don't attempt to allocate more than 4GiB of memoryIt seems that rather than returning a null pointer from `std::alloc::alloc`,miri will sometimes choose to simply crash the whole program.* remove duplicate prelude import after rebasing List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

70b076d3 - Migrate all Winch filetests to `tests/disas` (#8243)

Wed, 27 Mar 2024 14:44:46 +0000

Migrate all Winch filetests to `tests/disas` (#8243)* Switch Winch tests to ATT syntax* Update all test expectations* Move all winch tests to `disas` folder* Add `test = "winch"` to `disas`* Add `test = "winch"` to all winch test files* Stub out bits to get AArch64 Winch tests working* Update expectations for all aarch64 winch tests* Update flags in Winch testsUse CLI syntax as that's what `flags` was repurposes as in the new testsuite.* Update all test expectations for x64 winch* Omit more offsets by default* Delete now-dead code* Update an error message* Update non-winch test expectations List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

f466aa26 - Skeleton and initial support for proof-carrying code. (#7165)

Fri, 06 Oct 2023 22:31:23 +0000

Skeleton and initial support for proof-carrying code. (#7165)* WIP veriwasm 2.0Co-Authored-By: Chris Fallin * PCC: successfully parse some simple facts.Co-authored-by: Nick Fitzgerald * PCC: plumb facts through VCode and add framework on LowerBackend to check them.Co-authored-by: Nick Fitzgerald * PCC: code is carrying some proofs! Very simple test-case.Co-authored-by: Nick Fitzgerald * PCC: add a `safe` flag for checked memory accesses.* PCC: add pretty-printing of facts to CLIF output.* PCC: misc. cleanups.* PCC: lots of cleanup.* Post-rebase fixups and some misc. fixes.* Add serde traits to facts.* PCC: add succeed and fail tests.* Review feedback: rename `safe` memflag to `checked`.* Review feedback.---------Co-authored-by: Nick Fitzgerald List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

5c8a603a - Make MachineEnv a per-ABI property (#6957)

Tue, 12 Sep 2023 19:17:53 +0000

Make MachineEnv a per-ABI property (#6957)The MachineEnv structure contains the allocatable and preferredregister sets. This is currently fixed per TargetIsa - however,conceptually these register sets can differ between ABIs on thesame ISA.To allow for this, replace the TargetIsa machine_env routine withan ABIMachineSpec get_machine_env routine. To ensure the structureis still only allocated once, cache it via static OnceLock variables.No functional change intended. List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

7b16eccd - Support referencing stack slots in the DWARF debug info (#6960)

Tue, 05 Sep 2023 21:11:53 +0000

Support referencing stack slots in the DWARF debug info (#6960)* Add a test* Disable test* Add support for specifying stack locations in debug infoAlways emit SysV-style CFI unwind info if we need debug info,and reference it in the debug info using DW_OP_call_frame_cfa.* Add toolchain comment to the test* Add a comment and assert List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs

82c32923 - x64: Fix ISA requirement for `pmaddubsw` (#6629)

Thu, 22 Jun 2023 23:58:15 +0000

x64: Fix ISA requirement for `pmaddubsw` (#6629)* x64: Fix ISA requirement for `pmaddubsw`This was erroneously listed as SSE2 but this is actually an SSSE3instruction. This commit updates the ISA requirement as well as relatedlowerings to have everything work with an SSE2 baseline as well which ismostly plumbing to make sure the relaxed-simd dot product instructionsuse it when it's available but otherwise fall-back to the deterministiclowering.* Add require ssse3 feature* Fix preexisting wat test List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/mod.rs