Changes in generated_code.rs

099102d9 - Remove `expect(clippy::allow_attributes_without_reason)` from cranelift-codegen (#11182)

Mon, 07 Jul 2025 17:25:40 +0000

Remove `expect(clippy::allow_attributes_without_reason)` from cranelift-codegen (#11182)* Remove `expect(clippy::allow_attributes_without_reason)` from cranelift-codegenThis commit gets around to migrating the `cranelift-codegen` crate torequire a reason on lint directives and additionally switch to`#[expect]` where possible.prtest:full* Move x64-only item to x64 backend List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs

0c0153c1 - Enforce `clippy::clone_on_copy` for the workspace (#9025)

Sat, 27 Jul 2024 01:11:06 +0000

Enforce `clippy::clone_on_copy` for the workspace (#9025)* Derive `Copy` for `Val`* Fix `clippy::clone_on_copy` for the whole repo* Enforce `clippy::clone_on_copy` for the workspace* fix some more clippy::clone_on_copy that got missed List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs

f0979af1 - cranelift-codegen: Prepare aarch64 for usage from Winch (#5570)

Fri, 13 Jan 2023 19:46:25 +0000

cranelift-codegen: Prepare aarch64 for usage from Winch (#5570)This commit exposes the necessary aarch64 pieces to be used by Winch for binary emission. List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs

b652ce2f - ISLE: add support for multi-extractors and multi-constructors. (#4908)

Wed, 21 Sep 2022 23:36:50 +0000

ISLE: add support for multi-extractors and multi-constructors. (#4908)* ISLE: add support for multi-extractors and multi-constructors. This support allows for rules that process multiple matching values per extractor call on the left-hand side, and as a result, can produce multiple values from the constructor whose body they define. This is useful in situations where we are matching on an input data structure that can have multiple "nodes" for a given value or ID, for example in an e-graph. * Review feedback: all multi-ctors and multi-etors return iterators; no `Vec` case. * Add additional warning suppressions to generated-code toplevels to be consistent with new islec output. List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs

5d671952 - Cranelift: do not check in generated ISLE code; regenerate on every compile. (#4143)

Thu, 12 May 2022 05:25:24 +0000

Cranelift: do not check in generated ISLE code; regenerate on every compile. (#4143)This PR fixes #4066: it modifies the Cranelift `build.rs` workflow to invoke the ISLE DSL compiler on every compilation, rather than only when the user specifies a special "rebuild ISLE" feature. The main benefit of this change is that it vastly simplifies the mental model required of developers, and removes a bunch of failure modes we have tried to work around in other ways. There is now just one "source of truth", the ISLE source itself, in the repository, and so there is no need to understand a special "rebuild" step and how to handle merge errors. There is no special process needed to develop the compiler when modifying the DSL. And there is no "noise" in the git history produced by constantly-regenerated files. The two main downsides we discussed in #4066 are: - Compile time could increase, by adding more to the "meta" step before the main build; - It becomes less obvious where the source definitions are (everything becomes more "magic"), which makes exploration and debugging harder. This PR addresses each of these concerns: 1. To maintain reasonable compile time, it includes work to cut down the dependencies of the `cranelift-isle` crate to *nothing* (only the Rust stdlib), in the default build. It does this by putting the error-reporting bits (`miette` crate) under an optional feature, and the logging (`log` crate) under a feature-controlled macro, and manually writing an `Error` impl rather than using `thiserror`. This completely avoids proc macros and the `syn` build slowness. The user can still get nice errors out of `miette`: this is enabled by specifying a Cargo feature `--features isle-errors`. 2. To allow the user to optionally inspect the generated source, which nominally lives in a hard-to-find path inside `target/` now, this PR adds a feature `isle-in-source-tree` that, as implied by the name, moves the target for ISLE generated source into the source tree, at `cranelift/codegen/isle_generated_source/`. It seems reasonable to do this when an explicit feature (opt-in) is specified because this is how ISLE regeneration currently works as well. To prevent surprises, if the feature is *not* specified, the build fails if this directory exists. List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs

eb435f30 - x64: use constant pool for u64 constants rather than `movabs`. (#4088)

Tue, 10 May 2022 16:21:05 +0000

x64: use constant pool for u64 constants rather than `movabs`. (#4088)* Allow emitting u64 constants into constant pool. * Use constant pool for constants on x64 that do not fit in a simm32 and are needed as a RegMem or RegMemImm. * Fix rip-relative addressing bug in pinsrd emission. List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs

f85047b0 - Rework x64 addressing-mode lowering to be slightly more flexible. (#4080)

Mon, 02 May 2022 23:20:39 +0000

Rework x64 addressing-mode lowering to be slightly more flexible. (#4080)This PR refactors the x64 backend address-mode lowering to use an incremental-build approach, where it considers each node in a tree of `iadd`s that feed into a load/store address and, at each step, builds the best possible `Amode`. It will combine an arbitrary number of constant offsets (an extension beyond the current rules), and can capture a left-shifted (scaled) index in any position of the tree (another extension). This doesn't have any measurable performance improvement on our Wasm benchmarks in Sightglass, unfortunately, because the IR lowered from wasm32 will do address computation in 32 bits and then `uextend` it to add to the 64-bit heap base. We can't quite lift the 32-bit adds to 64 bits because this loses the wraparound semantics. (We could label adds as "expected not to overflow", and allow *those* to be lifted to 64 bit operations; wasm32 heap address computation should fit this. This is `add nuw` (no unsigned wrap) in LLVM IR terms. That's likely my next step.) Nevertheless, (i) this generalizes the cases we can handle, which should be a good thing, all other things being equal (and in this case, no compile time impact was measured); and (ii) might benefit non-Wasm frontends. List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs

03793b71 - ISLE: remove all uses of argument polarity, and remove it from the language. (#4091)

Mon, 02 May 2022 16:52:12 +0000

ISLE: remove all uses of argument polarity, and remove it from the language. (#4091)This PR removes "argument polarity": the feature of ISLE extractors that lets them take inputs aside from the value to be matched. Cases that need this expressivity have been subsumed by #4072 with if-let clauses; we can now finally remove this misfeature of the language, which has caused significant confusion and has always felt like a bit of a hack. This PR (i) removes the feature from the ISLE compiler; (ii) removes it from the reference documentation; and (iii) refactors away all uses of the feature in our three existing backends written in ISLE. List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs

eceb433b - Remove `=x` uses from ISLE, and remove support from the DSL compiler. (#4078)

Thu, 28 Apr 2022 18:17:08 +0000

Remove `=x` uses from ISLE, and remove support from the DSL compiler. (#4078)This is a follow-up on #4074: now that we have the simplified syntax, we can remove the old, redundant syntax. List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs

12b4374c - [AArch64] Port atomic rmw to ISLE (#4021)

Wed, 27 Apr 2022 20:13:59 +0000

[AArch64] Port atomic rmw to ISLE (#4021)Also fix and extend the current implementation: - AtomicRMWOp::Clr != AtomicRmwOp::And, as the input needs to be inverted first. - Inputs to the cmp for the RMWLoop case are sign-extended when needed. - Lower Xchg to Swp. - Lower Sub to Add with a negated input. - Added more runtests. Copyright (c) 2022, Arm Limited. List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs

164bfeaf - x64 backend: migrate stores, and remainder of loads (I128 case), to ISLE. (#4069)

Tue, 26 Apr 2022 16:50:46 +0000

x64 backend: migrate stores, and remainder of loads (I128 case), to ISLE. (#4069) List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs

cf533a80 - [AArch64] Merge Fcmp32 and Fcmp64 (#4032)

Thu, 14 Apr 2022 22:39:43 +0000

682ef7b4 - [AArch64] Refactor Mov instructions (#4033)

Thu, 14 Apr 2022 21:51:12 +0000

[AArch64] Refactor Mov instructions (#4033)Merge Mov32 and Mov64 into a single instruction parameterized by a new OperandSize field. Also combine the Mov[K,N,Z] into a single instruction with a new opcode to select between the operations. Copyright (c) 2022, Arm Limited. List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs

dd442a4d - [AArch64] Merge 32- and 64-bit FPUOp1 (#4031)

Thu, 14 Apr 2022 21:00:48 +0000

7c0ea28f - [AArch64] Merge 32- and 64-bit FPUOp2 (#4029)

Thu, 14 Apr 2022 20:07:00 +0000

[AArch64] Merge 32- and 64-bit FPUOp2 (#4029)And remove the unused saturating add/sub opcodes. Copyright (c) 2022, Arm Limited. List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs

e142f587 - [AArch64] Refactor ALUOp3 (#3950)

Thu, 14 Apr 2022 19:16:56 +0000

[AArch64] Refactor ALUOp3 (#3950)As well as adding generic pattern for msub along with runtests for madd and msub. Copyright (c) 2022, Arm Limited. List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs

a0318f36 - Switch Cranelift over to regalloc2. (#3989)

Thu, 14 Apr 2022 17:28:21 +0000

Switch Cranelift over to regalloc2. (#3989)This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ``` List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs

f62199da - x64: port `load` to ISLE (#3993)

Fri, 08 Apr 2022 01:31:22 +0000

x64: port `load` to ISLE (#3993)This change moves the majority of the lowerings for CLIF's `load` instruction over to ISLE. To do so, it also migrates the previous mechanism for creating an `Amode` (`lower_to_amode`) to several ISLE rules (see `to_amode`). List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs

5d8dd648 - x64: port `fcmp` to ISLE (#3967)

Tue, 29 Mar 2022 22:41:49 +0000

x64: port `fcmp` to ISLE (#3967)* x64: port scalar `fcmp` to ISLE Implement the CLIF lowering for the `fcmp` to ISLE. This adds a new type-matcher, `ty_scalar_float`, for detecting uses of `F32` and `F64`. * isle: rename `vec128` to `ty_vec12` This refactoring changes the name of the `vec128` matcher function to follow the `ty_*` convention of the other type matchers. It also makes the helper an inline function call. * x64: port vector `fcmp` to ISLE List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs

13b93969 - Add vector compare to 0 optims (#3887)

Thu, 10 Mar 2022 00:20:06 +0000

Add vector compare to 0 optims (#3887)Signed-off-by: Freddie Liardet List of files: /wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs