Changes in gen_asm.rs

2a2e8f62 - Couple cleanups to the flags/settings handling in Cranelift (#11744)

Wed, 01 Oct 2025 14:17:11 +0000

Couple cleanups to the flags/settings handling in Cranelift (#11744)* Remove unused shared flags* Get rid of predicate settingsThey were important in the old backend framework, but with the newbackend framework if we need a combination of multiple settings, thatcan just be done as a regular extractor doing &&. This simplifies thesettings implementation. List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

380bf125 - x64: Migrate `setcc` instructions to the new assembler (#11112)

Tue, 24 Jun 2025 15:40:42 +0000

x64: Migrate `setcc` instructions to the new assembler (#11112)These instructions were relatively straightforward and the notable partshere are:* The manual doesn't have `/0` but these instructions use `.digit(0)`, but the manual also says the reg bits are ignored in the ModR/M byte so it doesn't actually matter what we put in these bits, just need to put something in there.* The previous implementation in `emit.rs` unconditionally emitted a REX byte but this was not necessary for some registers, so many binary offsets have changed in tests as some unnecessary REX bytes are now omitted.* As with `cmov*` instructions in #11095 some mnemonics that Cranelift uses differ from the canonical ones that Capstone disassembles, so there are some naming discrepancies which are documented inline as well. List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

79cf7e8e - x64: Migrate `cmov*` to the new assembler (#11095)

Sat, 21 Jun 2025 19:11:45 +0000

x64: Migrate `cmov*` to the new assembler (#11095)This commit adds all `cmov*` variants from the Intel manual to the newassembler. This then additionally removes the `Cmove` pseudo-inst infavor of these new instructions. One difference from before is that thenaming in the `CC` enum does not exactly match what mnemonics Capstoneuses to disassemble. For example `CC.NB` in ISLE corresponds to theIntel instruction `CMOVNB`. This instruction, however, has the sameencoding as `CMOVAE` and Capstone disassembles as `CMOVAE`. This meansthat the instruction selection in ISLE isn't a 1:1 match with mnemonics.This additionally adds support in the assembler ISLE generation tounderstand that instructions which read EFLAGS generate a`ConsumesFlags` variant in their instruction helpers. List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

a5a15bd2 - x64: convert unary VEX instructions (#11088)

Fri, 20 Jun 2025 18:37:47 +0000

x64: convert unary VEX instructions (#11088)* asm: cover more of SSE in `Features::is_sse()`* asm: add `VexPrefix::two_op`This is simply a convenience method when `vvvv` is unspecified.* asm: print failing instruction in SSE-to-AVX alternate mapping* asm: fill out AVX functionality for unary VEX instructionsThese include `vmov*`, `vpmov*`, `vsqrt`, and some lane operations.* asm: add `Location::xmm_m8`* asm: add av2 feature* asm: add AVX broadcast instructions* x64: add `is_mem` for extracting addresses from `XmmMem`* x64: convert unary VEX instructions* x64: bless Cranelift filetests* x64: use alternate AVX version for `pabs*`* x64: bless `pabs*` Cranelift filetests* x64: remove `XmmUnaryRmRVex` and now-unnecessary `AvxOpcode`s* winch: convert `XmmUnaryRmRVex` instructions List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

f101b987 - x64: Migrate cmp/test to the new assembler (#11072)

Thu, 19 Jun 2025 13:49:37 +0000

x64: Migrate cmp/test to the new assembler (#11072)* x64: Migrate cmp/test to the new assemblerThis commit migrates the `cmp` and `test` family of instructions, the`CmpRmiR` variant in ISLE, to the new assembler. This requiredfiddling with various helpers for immediates and such throughout a fewlocations and refactoring various callsites of creating theseinstructions to fit nicely into these new idioms. EFLAGS-writinginstructions with no other results are now also modeled in the assembleras `ProducesFlags` rather than `SideEffectNoResult` as their base caseenabling using the generated constructors a bit more too.No functional change is expected from this, it should just be internalrefactoring.* Swap between rm and mr encodings List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

c54fcb2c - x64: Migrate `cmpxchg{,16b}` to the new assembler (#11035)

Fri, 13 Jun 2025 16:44:53 +0000

x64: Migrate `cmpxchg{,16b}` to the new assembler (#11035)* x64: Migrate `cmpxchg{,16b}` to the new assemblerA few new operands were needed to define this as well as a number of newinstruction "shapes" in a few locations, but nothing too too radical.* Fix emit test List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

92b9f97b - x64: Migrate `LockXadd` to the new assembler (#11032)

Fri, 13 Jun 2025 15:40:37 +0000

x64: Migrate `LockXadd` to the new assembler (#11032)* x64: Migrate `LockXadd` to the new assemblerThis required a custom mnemonic implementation to handle the `lock`prefix and then this also required a custom visit implementation becauseIntel says the memory operand comes first but regalloc requires theregister operand comes first.* Remove unused variables List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

e5d346c2 - x64: Migrate `xchg` to the new assembler (#11008)

Fri, 13 Jun 2025 00:08:07 +0000

x64: Migrate `xchg` to the new assembler (#11008)This required a custom visit function because printing operands has tohappen in one order to match Capstone but allocating operations has tohappen in another order to satisfy regalloc, so so one of the two has tobe custom. List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

cd1615de - x64: Convert `compare` instructions to the new assembler (#10836)

Thu, 12 Jun 2025 21:19:35 +0000

x64: Convert `compare` instructions to the new assembler (#10836)* Implement compare instructions for new assembler, implement eflags logic, custom display logic for operands* clippy lints fix* add custom:display for compare instructions* nit change panic message* format fix, bless tests, prtest:full List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

09cfb907 - x64: generate rules to pick between SSE or AVX instructions (#10942)

Mon, 09 Jun 2025 17:50:10 +0000

x64: generate rules to pick between SSE or AVX instructions (#10942)* asm: introduce `Inst::alternate`, with auto-assignment of AVX to SSEThis adds the ability for an instruction to track an alternate versionof itself. This is helpful for connecting SSE instructions to theirupgraded AVX version. The logic here compares the mnemonic name minusthe `v` prefix and checks that the opcodes are the same. Thisauto-assignment cautiously limits us to SSE instructions like `rw(xmm),r(xmm_m*)`, which have a most regular SSE-AVX relationship.To see the list of instructions that have been assigned alternates, fromthe `cranelift/assembler-x64/meta` directory, run:```console$ cargo run | grep alternate```* x64: use generated `x64_..._or_avx` rule to lower `x64_addp*`This change updates `gen_asm.rs` to emit an extra rule for instructionsthat have an AVX alternate: `x64__or_avx`. The rule logic has thesame shape as what we currently hand-write ~180 times in `inst.isle`(!).* review: make SSE-to-AVX replacements explicitThis change uses `Inst::alt()` to explicitly mark which instructionshave an AVX alternate. This retains the strict checks preventing us frommanually making a mistake. It also passes along the `Feature` in an`Alternate` structure to make this easier to extend later.* review: move opcode calculation List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

50264ae8 - x64: Migrate push/pop to the new assembler (#10977)

Mon, 09 Jun 2025 17:35:48 +0000

x64: Migrate push/pop to the new assembler (#10977)* x64: Migrate push/pop to the new assemblerFigured these would be some interesting instruction shapes. This adds ahelper to the ISLE generation to skip some instructions and the "push"instructions are skipped as they're not needed in ISLE and wouldotherwise require binding new instruction shapes which didn't seem worthit. Additionally many items in `gen_asm.rs` were made private (removed`pub`).* Update test expectations List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

4955f5a7 - x64: Migrate `mulx` to the new assembler (#10887)

Mon, 02 Jun 2025 20:14:46 +0000

x64: Migrate `mulx` to the new assembler (#10887)* x64: Migrate `mulx` to the new assemblerThis is an interesting instruction as it has a relatively unique shapecompared to many others. The VEX encoding is used to give it a 3-operandform, although it still has an implicit 4th operand as well. The otherunique part about this instruction is that if the two write-onlyoperands are the same then that has a different semantic meaning than ifthey are different.Modeling the two-output form of the instruction was pretty easy, theonly changes needed were to add the `r32a` and `r32b` locations aspreviously only `r32` was available. Modeling the one-output form of theinstruction led to a "hook" where these instructions specify that theyuse a custom regalloc function. That skips the auto-generated regallocentirely and defers to a new `custom` submodule in the assembler crate.These custom variants handle only having a single write operand on theinstruction.* Fix fuzz build List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

63a8ce3d - x64: Migrate xmm mov-family instructions to new assembler (#10834)

Wed, 28 May 2025 17:27:16 +0000

x64: Migrate xmm mov-family instructions to new assembler (#10834)* x64: Migrate xmm mov-family instructions to new assemblerThis commit migrates xmm movement-style instructions, such as`mov{s{s,d},{a,u}p{s,d},dq{a,u}}` to the new assembler. This enablesdeleting the `XmmMovRM` class of instructions in ISLE. Along the way anumber of notable changes were made:* ISLE constructors for assembler instructions now take `SyntheticAmode` instead of `Amode` since it's already supported anyway and it's a more flexible argument to take.* The conversion from `SyntheticAmode` to the assembler `Amode` was fixed where one variant needed to use `rsp` instead of `rbp`.* The `is_move` method was updated to ignore `movss` and `movsd` instructions since they're not true movement-related instructions in register-to-register situations.* Use `gen_move` helper in Winch List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

10e71fa8 - x64: Convert some lane-manipulation instructions to the new assembler (#10825)

Fri, 23 May 2025 21:17:46 +0000

x64: Convert some lane-manipulation instructions to the new assembler (#10825)* x64: Convert some lane-manipulation instructions to the new assemblerThis was mostly straightforward but ended up requiring handling for anew style of instruction not previously before-seen: a write-only`GprMem` operand. This needed some extra treatment/helpers in the ISLEintegration to ensure that this was all hooked up correctly from ISLEconstructors down to the assembler instructions.* Remove `GprToXmm` as wellAlready have mappings for `movd` and `movq`, so let's migrate this as well.* Remove some old emit tests List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

b4f041f8 - x64: Migrate div instructions to the new assembler (#10820)

Thu, 22 May 2025 15:51:40 +0000

x64: Migrate div instructions to the new assembler (#10820)* x64: Migrate div instructions to the new assemblerThis mostly required adding a new kind of operand representing a`TrapCode` and plumbing around a few bits and bobs to ensure that thiscompile-time-only-abstraction does not need to be accounted for in allthe encoding bits.* Fix doc tests* Shrink the size of `Amode`Reduces the size of `KnownOffset` so `Option` doesn't havesuch a high alignment or size, greatly shrinking the size of theinstruction and prevents the changes to `Div` from increasing the sizeof the overall `Inst` enum. In fact it now shrinks!* Don't model a trap code as an operand* Render trap information in `Display` List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

7ea7ebcc - x64: convert all multiplication-related instructions (#10782)

Mon, 19 May 2025 20:01:44 +0000

x64: convert all multiplication-related instructions (#10782)* asm: add SSE4.1 feature* asm: refactor format constructors with expanding structs* asm: add implicit operandsImplicit operands are used by an instruction but not present in itsdisassembled output. Instructions like `mul`, e.g., will write to the`%rax` and `%rdx` registers, but this is all invisible in disassembly.Implicit operands are always fixed (i.e., the register is known), butnot all fixed operands are implicit (i.e., some fixed registers _are_disassembled).* asm: add `mul*` instructions, vector and scalar* asm: generate ISLE for multi-return constructors--`AssemblerOutputs::RetValueRegs`Certain `mul*` instructions write to multiple registers. For registerallocation, Cranelift needs to know about all of these registers. Thischange uses the pre-existing pattern of returning a `ValueRegs` type toindicate this. This change is limited to what is needed now: the onlymulti-return needed now uses two fixed registers.* x64: convert SSE multiplications* x64: convert scalar multiplications* x64: remove old `Inst::Mul*` variants* winch: convert multiplicationsThis does not include any special "small immediate resizing" rules forWinch, so the Winch disassembly tests gain a few bytes (e.g., someimmediates that _could_ fit in 8 bits are emitted as the full 32 bits).* refactor: move `i32`-related extractors to `prelude.isle`* review: print the implicit registers as well* fix: the instruction size has changed (again) List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

90ac295e - Update Wasmtime to the 2024 Rust Edition (#10806)

Mon, 19 May 2025 16:40:55 +0000

Update Wasmtime to the 2024 Rust Edition (#10806)* Update Wasmtime to the 2024 Rust EditionNow that our MSRV supports the 2024 edition it's possible to make thisswitch. This commit moves Wasmtime to the 2024 Edition to keepup-to-date with Rust idioms and access many of the edition featuresexclusive to the 2024 edition.prtest:full* Reformat with the 2024 edition List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

d9468c6e - asm: implement write-only operands (#10759)

Fri, 09 May 2025 21:58:03 +0000

asm: implement write-only operands (#10759)* asm: implement write-only operandsThis change adds support to the new assembler for write-only operands.This implementation appeared first in [#10754] but is split out here tounblock implementation of instructions that require it: multiplication,conversions, moves, etc. This starts roughly the same as what wasimplemented for write-only XMMs in [#10754] but includes support forwrite-only GPRs as well and generates the temporary registers which areneeded.[#10754]: https://github.com/bytecodealliance/wasmtime/pull/10754Co-authored-by: Johnnie Birch * fix: use `to_reg()` to extract the Cranelift type from `Writable`---------Co-authored-by: Johnnie Birch List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

19ad7b3c - asm: refactor using `RegClass` and `xmm_m{32|64|128}` (#10716)

Fri, 02 May 2025 20:11:01 +0000

asm: refactor using `RegClass` and `xmm_m{32|64|128}` (#10716)This change involves no change in functionality but does pave the wayfor defining more SSE instructions in two ways:- it adds the `xmm_m32` and `xmm_m64` variants as locations and changes `rm128` to read `xmm_m128` to match; this is necessary for SSE `*ss` and `*sd` instructions that load 32- and 64-bit values into XMM registers- by returning `RegClass` from `Location::reg_class` it is much easier to distinguish what kind of a register an operand is using: previously this matched on the number of bits (i.e., 128) which does no longer makes sense for `xmm_m32` and `xmm_m64`. List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs

420f7453 - asm: plumb fixed registers through (#10629)

Tue, 22 Apr 2025 00:25:48 +0000

asm: plumb fixed registers through (#10629)* asm: plumb fixed registers throughThis change introduces a new `Fixed` wrapper type that allows us toplumb fixed registers through the assembler. These instructions are notyet used by `cranelift-codegen`, but will be necessary at some point asdescribed in [#10238]. The end result of this is that up at the`cranelift-codegen` level, fixed registers should look likerun-of-the-mill virtual registers using the appropriate types, but downin `cranelift-assembler-x64` we panic if the register allocator does notgive them the correct register.[#10238]: https://github.com/bytecodealliance/wasmtime/issues/10238* fix: reduce `size_of::` testIt is unclear why adding more `Fixed` fields would somehow _reduce_the size of `Inst`. What is quite clear is that I do not understand howRust chooses to lay out these fields. List of files: /wasmtime-44.0.1/cranelift/codegen/meta/src/gen_asm.rs