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    <title>Changes in cap-exp-rev-slot</title>
    <description></description>
    <language>en</language>
    <copyright>Copyright 2015</copyright>
    <generator>Java</generator><item>
        <title>f41bb847 - lspci: Decode &quot;Slot Implemented&quot; for PCI/PCI-X to PCIe Bridges</title>
        <link>http://172.16.0.5:8080/history/pciutils/tests/cap-exp-rev-slot#f41bb847</link>
        <description>lspci: Decode &quot;Slot Implemented&quot; for PCI/PCI-X to PCIe BridgesThe secondary side of a PCI/PCI-X to PCIe Bridge (a &quot;reverse bridge&quot;) is aPCIe Downstream Port and could support a slot just like Root Ports andSwitch Downstream Ports.Decode &quot;Slot Implemented&quot; for reverse bridges and, if true, the SlotCapabilities, Control, and Status registers.For a reverse bridge with no slot, the difference in the &quot;lspci -vv&quot; outputlooks like this:-    Capabilities: [40] Express (v2) PCI/PCI-X to PCI-Express Bridge, MSI 00+    Capabilities: [40] Express (v2) PCI/PCI-X to PCI-Express Bridge (Slot-), MSI 00Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;

            List of files:
            /pciutils/tests/cap-exp-rev-slot</description>
        <pubDate>Fri, 21 Apr 2017 19:32:18 +0000</pubDate>
        <dc:creator>Bjorn Helgaas &lt;bhelgaas@google.com&gt;</dc:creator>
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