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<rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/">
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    <title>Changes in pciutils</title>
    <description></description>
    <language>en</language>
    <copyright>Copyright 2015</copyright>
    <generator>Java</generator><item>
        <title>6fdd4034 - Added test cases for topology computation</title>
        <link>http://172.16.0.5:8080/history/pciutils/#6fdd4034</link>
        <description>Added test cases for topology computationContributed by Matthew Wilcox

            List of files:
            /pciutils/tests/tree-asus-p6t6/pciutils/tests/tree-fujitsu-p8010</description>
        <pubDate>Sun, 12 Aug 2018 10:00:00 +0000</pubDate>
        <dc:creator>Martin Mares &lt;mj@ucw.cz&gt;</dc:creator>
    </item>
<item>
        <title>fe4074e5 - Man pages: clarify pci.ids location</title>
        <link>http://172.16.0.5:8080/history/pciutils/#fe4074e5</link>
        <description>Man pages: clarify pci.ids locationInclude both the path and filename of pci.ids in the pci.ids man pageand the update-pciids man page

            List of files:
            /pciutils/update-pciids.man</description>
        <pubDate>Wed, 03 Mar 2021 20:00:00 +0000</pubDate>
        <dc:creator>Robert Elliott &lt;elliott@hpe.com&gt;</dc:creator>
    </item>
<item>
        <title>38df5682 - Add test case with multidomain Freescale P2020 PCIe hierarchy</title>
        <link>http://172.16.0.5:8080/history/pciutils/#38df5682</link>
        <description>Add test case with multidomain Freescale P2020 PCIe hierarchy

            List of files:
            /pciutils/tests/tree-fsl-p2020</description>
        <pubDate>Sat, 29 Apr 2023 11:00:00 +0000</pubDate>
        <dc:creator>Pali Roh&#225;r &lt;pali@kernel.org&gt;</dc:creator>
    </item>
<item>
        <title>7ec58f1c - update-pciids: Report itself as an user agent, version included</title>
        <link>http://172.16.0.5:8080/history/pciutils/#7ec58f1c</link>
        <description>update-pciids: Report itself as an user agent, version includedUnfortunately, this leads to the User-Agent not containing versionof curl/wget/lynx we used.

            List of files:
            /pciutils/update-pciids.sh</description>
        <pubDate>Sun, 23 Jul 2023 13:00:00 +0000</pubDate>
        <dc:creator>Martin Mares &lt;mj@ucw.cz&gt;</dc:creator>
    </item>
<item>
        <title>2898e33f - lspci: Add test case for Physical Layer 16 GT/s and 32 GT/s extended capability registers</title>
        <link>http://172.16.0.5:8080/history/pciutils/#2898e33f</link>
        <description>lspci: Add test case for Physical Layer 16 GT/s and 32 GT/s extended capability registers

            List of files:
            /pciutils/tests/cap-phy32</description>
        <pubDate>Mon, 09 Jun 2025 18:00:00 +0000</pubDate>
        <dc:creator>Tristan Watts-Willis &lt;tristan.watts-willis@teledyne.com&gt;</dc:creator>
    </item>
<item>
        <title>568ec6c7 - Added a test case for the VC capability with a port arbitration table</title>
        <link>http://172.16.0.5:8080/history/pciutils/#568ec6c7</link>
        <description>Added a test case for the VC capability with a port arbitration tableThanks to John Burr for the dump.

            List of files:
            /pciutils/tests/cap-vc-pat</description>
        <pubDate>Sun, 31 Jan 2010 17:00:00 +0000</pubDate>
        <dc:creator>Martin Mares &lt;mj@ucw.cz&gt;</dc:creator>
    </item>
<item>
        <title>c0d9545c - lspci: Decode Multicast Extended Capability</title>
        <link>http://172.16.0.5:8080/history/pciutils/#c0d9545c</link>
        <description>lspci: Decode Multicast Extended CapabilityDecode the Multicast Extended Capability described in PCIe r4.0, sec7.9.11.Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;

            List of files:
            /pciutils/tests/cap-multicast</description>
        <pubDate>Tue, 06 Nov 2018 21:00:00 +0000</pubDate>
        <dc:creator>Bjorn Helgaas &lt;bhelgaas@google.com&gt;</dc:creator>
    </item>
<item>
        <title>77e6d8e9 - Added a test case for Virtual Channel and Root Complex Link caps</title>
        <link>http://172.16.0.5:8080/history/pciutils/#77e6d8e9</link>
        <description>Added a test case for Virtual Channel and Root Complex Link caps

            List of files:
            /pciutils/tests/cap-vc-and-rcl</description>
        <pubDate>Sat, 23 Jan 2010 20:00:00 +0000</pubDate>
        <dc:creator>Martin Mares &lt;mj@ucw.cz&gt;</dc:creator>
    </item>
<item>
        <title>5f6aca18 - Fix spelling of surprise</title>
        <link>http://172.16.0.5:8080/history/pciutils/#5f6aca18</link>
        <description>Fix spelling of surpriseIt&apos;s surprise, not surpise or suprise.Signed-off-by: Ed Swierk &lt;eswierk@aristanetworks.com&gt;

            List of files:
            /pciutils/tests/cap-pcie-1</description>
        <pubDate>Thu, 20 Aug 2009 22:00:00 +0000</pubDate>
        <dc:creator>Ed Swierk &lt;eswierk@aristanetworks.com&gt;</dc:creator>
    </item>
<item>
        <title>44c6c7fc - lspci: Decode the (virtual) resizeble BAR capability</title>
        <link>http://172.16.0.5:8080/history/pciutils/#44c6c7fc</link>
        <description>lspci: Decode the (virtual) resizeble BAR capabilityA patch by Paul Blinzer.

            List of files:
            /pciutils/tests/cap-rebar</description>
        <pubDate>Mon, 25 May 2020 13:00:00 +0000</pubDate>
        <dc:creator>Martin Mares &lt;mj@ucw.cz&gt;</dc:creator>
    </item>
<item>
        <title>c5db7af4 - lspci: Update tests files with VF 10-Bit Tag Requester</title>
        <link>http://172.16.0.5:8080/history/pciutils/#c5db7af4</link>
        <description>lspci: Update tests files with VF 10-Bit Tag RequesterUpdate the tests files with the new field 10BitTagReqin SR-IOV Capabilities Register.Signed-off-by: Dongdong Liu &lt;liudongdong3@huawei.com&gt;

            List of files:
            /pciutils/tests/cap-ea-1/pciutils/tests/cap-pcie-2</description>
        <pubDate>Tue, 09 Mar 2021 13:00:00 +0000</pubDate>
        <dc:creator>Dongdong Liu &lt;liudongdong3@huawei.com&gt;</dc:creator>
    </item>
<item>
        <title>e12bd01e - pciutils: Add decode support for RCECs</title>
        <link>http://172.16.0.5:8080/history/pciutils/#e12bd01e</link>
        <description>pciutils: Add decode support for RCECsRoot Complex Event Collectors provide support for terminating errorand PME messages from RCiEPs.  This patch provides basic decoding forthe lspci RCEC Endpoint Association Extended Capability. See PCIe 5.0-1,sec 7.9.10 for further details.Suggested-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;Signed-off-by: Sean V Kelley &lt;sean.v.kelley@linux.intel.com&gt;

            List of files:
            /pciutils/tests/cap-rcec</description>
        <pubDate>Wed, 24 Jun 2020 22:00:00 +0000</pubDate>
        <dc:creator>Sean V Kelley &lt;sean.v.kelley@linux.intel.com&gt;</dc:creator>
    </item>
<item>
        <title>89769a1a - lspci: Add test case for PTM</title>
        <link>http://172.16.0.5:8080/history/pciutils/#89769a1a</link>
        <description>lspci: Add test case for PTMThese are the software dummy PTM master and endpoints, but shouldbe enough to test register decoding.Signed-off-by: Yong, Jonathan &lt;jonathan.yong@intel.com&gt;

            List of files:
            /pciutils/tests/cap-ptm-1/pciutils/tests/cap-ptm-2</description>
        <pubDate>Wed, 18 May 2016 07:00:00 +0000</pubDate>
        <dc:creator>Yong, Jonathan &lt;jonathan.yong@intel.com&gt;</dc:creator>
    </item>
<item>
        <title>1bfc2be0 - lspci: add VirtIO SharedMemory capability support</title>
        <link>http://172.16.0.5:8080/history/pciutils/#1bfc2be0</link>
        <description>lspci: add VirtIO SharedMemory capability supportThis patch adds the support for VirtIO share memory capability [1].A shared memory region is defined in a `struct virtio_pci_cap64`where the highest 32 bits of `offset` and `size` are appened to theoriginal `struct virtio_pci_cap`.With this patch, a VirtIO PMEM device (ID 27) shows like thefollowing:```00:02.0 Class ffff: Device 1af4:105b (rev 01)        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast &gt;TAbort- &lt;TAbort- &lt;MAbort- &gt;SERR- &lt;PERR- INTx-        Latency: 0        Region 0: Memory at 100001000 (64-bit, non-prefetchable) [size=4K]        Region 2: Memory at 101000000 (64-bit, non-prefetchable) [size=16M]        Capabilities: [40] Vendor Specific Information: VirtIO: CommonCfg                BAR=0 offset=00000000 size=0000003c        Capabilities: [50] Vendor Specific Information: VirtIO: ISR                BAR=0 offset=0000003c size=00000001        Capabilities: [60] Vendor Specific Information: VirtIO: Notify                BAR=0 offset=00000040 size=00000002 multiplier=00000002        Capabilities: [78] MSI-X: Enable+ Count=2 Masked-                Vector table: BAR=0 offset=00000058                PBA: BAR=0 offset=00000078        Capabilities: [88] Vendor Specific Information: VirtIO: DeviceCfg                BAR=0 offset=00000044 size=00000010        Capabilities: [98] Vendor Specific Information: VirtIO: SharedMemory                BAR=2 offset=0000000000000000 size=0000000001000000 id=0        Kernel driver in use: virtio-pci```[1] Sec 4.1.4.7 https://docs.oasis-open.org/virtio/virtio/v1.2/csd01/virtio-v1.2-csd01.html#x1-1240004Signed-off-by: Changyuan Lyu &lt;changyuan.lv@gmail.com&gt;

            List of files:
            /pciutils/tests/cap-vendor-virtio</description>
        <pubDate>Sat, 30 Dec 2023 01:00:00 +0000</pubDate>
        <dc:creator>Changyuan Lyu &lt;changyuan.lv@gmail.com&gt;</dc:creator>
    </item>
<item>
        <title>a858df0d - Decode PASID and PRI extended capabilities</title>
        <link>http://172.16.0.5:8080/history/pciutils/#a858df0d</link>
        <description>Decode PASID and PRI extended capabilities

            List of files:
            /pciutils/tests/cap-pasid-pri</description>
        <pubDate>Thu, 15 Oct 2015 18:00:00 +0000</pubDate>
        <dc:creator>David Woodhouse &lt;dwmw2@infradead.org&gt;</dc:creator>
    </item>
<item>
        <title>548a6e3b - Subject: lspci: Display PASID required attribute in Page Status Register.</title>
        <link>http://172.16.0.5:8080/history/pciutils/#548a6e3b</link>
        <description>Subject: lspci: Display PASID required attribute in Page Status Register.Display the PASID required attribute in the Page Request Status Register.When set, the function expects a PASID on Page Group Response (PRG)messages when the corresponding page request had a PASID.Signed-off-by: Ashok Raj &lt;ashok.raj@intel.com&gt;

            List of files:
            /pciutils/tests/pri-pasid</description>
        <pubDate>Wed, 18 Oct 2023 21:00:00 +0000</pubDate>
        <dc:creator>Ashok Raj &lt;ashok.raj@intel.com&gt;</dc:creator>
    </item>
<item>
        <title>33f77200 - pciutils: Update the tests/cap-l1-pm with actual device data</title>
        <link>http://172.16.0.5:8080/history/pciutils/#33f77200</link>
        <description>pciutils: Update the tests/cap-l1-pm with actual device dataUpdate the test data using lspci output taken from a card that supportsL1 PM supstates.Signed-off-by: Rajat Jain &lt;rajatja@google.com&gt;

            List of files:
            /pciutils/tests/cap-l1-pm</description>
        <pubDate>Sat, 01 Oct 2016 00:00:00 +0000</pubDate>
        <dc:creator>Rajat Jain &lt;rajatja@google.com&gt;</dc:creator>
    </item>
<item>
        <title>ebcc5e95 - Added a test case for the PCI AF capability</title>
        <link>http://172.16.0.5:8080/history/pciutils/#ebcc5e95</link>
        <description>Added a test case for the PCI AF capability(an integrated USB controller on Intel DX58SO motherboard)Signed-off-by: Yu Zhao &lt;yu.zhao@intel.com&gt;

            List of files:
            /pciutils/tests/cap-pci-af</description>
        <pubDate>Fri, 26 Jun 2009 02:00:00 +0000</pubDate>
        <dc:creator>Yu Zhao &lt;yu.zhao@intel.com&gt;</dc:creator>
    </item>
<item>
        <title>0089d489 - lspci: Avoid &quot;%1$c&quot; style format strings in HT capability</title>
        <link>http://172.16.0.5:8080/history/pciutils/#0089d489</link>
        <description>lspci: Avoid &quot;%1$c&quot; style format strings in HT capabilityThis kind of format strings is not available on some compilers.Also added a test case for the HT capability.

            List of files:
            /pciutils/tests/cap-ht</description>
        <pubDate>Sat, 24 Mar 2018 15:00:00 +0000</pubDate>
        <dc:creator>Martin Mares &lt;mj@ucw.cz&gt;</dc:creator>
    </item>
<item>
        <title>de91b6f2 - Add support for Downstream Port Containment</title>
        <link>http://172.16.0.5:8080/history/pciutils/#de91b6f2</link>
        <description>Add support for Downstream Port ContainmentThe PCI SIG added the Downstream Port Containment capability. This patchdecodes this for lspci, and defines the extended capability for setpci.Signed-off-by: Keith Busch &lt;keith.busch@intel.com&gt;

            List of files:
            /pciutils/tests/cap-dpc</description>
        <pubDate>Tue, 26 Apr 2016 22:00:00 +0000</pubDate>
        <dc:creator>Keith Busch &lt;keith.busch@intel.com&gt;</dc:creator>
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</channel>
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