en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s#50bd6866 Add support for branch forms of ALU instructions to Cortex-A57 modelPatch fixes scheduling of ALU instructions which modify pc register. Patchalso fixes computation of mutually exclusive predicates for sequences ofvariants to be properly expandedDifferential revision: https://reviews.llvm.org/D91266 List of files: /llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s Tue, 24 Nov 2020 08:43:51 +0000 Evgeny Leviant <eleviant@accesssoftek.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s#885d3f41 [llvm-mca] Add branch forms of ALU instructions to Cortex-A57 test List of files: /llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s Mon, 09 Nov 2020 13:53:50 +0000 Evgeny Leviant <eleviant@accesssoftek.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s#cc96a822 [TableGen][SchedModels] Fix read/write variant substitutionPatch fixes case when sched class has write and read variants belongingto different processor models.Differential revision: https://reviews.llvm.org/D89777 List of files: /llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s Mon, 02 Nov 2020 14:39:04 +0000 Evgeny Leviant <eleviant@accesssoftek.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s#a877bda3 Fix issue in cortex-a57 sched modelDifferential revision: https://reviews.llvm.org/D90152 List of files: /llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s Mon, 26 Oct 2020 17:16:40 +0000 Evgeny Leviant <eleviant@accesssoftek.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s#7a78073b [ARM][SchedModels] Let ldm* instruction scheduling use MCSchedPredicateDifferential revision: https://reviews.llvm.org/D89957 List of files: /llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s Fri, 23 Oct 2020 07:33:20 +0000 Evgeny Leviant <eleviant@accesssoftek.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s#991e8615 [ARM][SchedModels] Convert IsCPSRDefinedPred to MCSchedPredicateDifferential revision: https://reviews.llvm.org/D89460 List of files: /llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s Tue, 20 Oct 2020 08:14:21 +0000 Evgeny Leviant <eleviant@accesssoftek.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s#8a7ca143 [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicateDifferential revision: https://reviews.llvm.org/D89553 List of files: /llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s Mon, 19 Oct 2020 08:37:54 +0000 Evgeny Leviant <eleviant@accesssoftek.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s#6e56046f [TableGen][SchedModels] Fix aliasing of SchedWriteVariantDifferential revision: https://reviews.llvm.org/D89114 List of files: /llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s Tue, 13 Oct 2020 10:05:24 +0000 Evgeny Leviant <eleviant@accesssoftek.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s#71027930 Add test for cortex-a57/ARM sched model. NFC List of files: /llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s Mon, 12 Oct 2020 09:49:56 +0000 Evgeny Leviant <eleviant@accesssoftek.com>