en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected#f0dd12ec [x86] use zero-extending load of a byte outside of loops too (2nd try)The first attempt missed changing test files for tools(update_llc_test_checks.py).Original commit message:This implements the main suggested change from issue #56498.Using the shorter (non-extending) instruction with only-Oz ("minsize") rather than -Os ("optsize") is left as apossible follow-up.As noted in the bug report, the zero-extending load may haveshorter latency/better throughput across a wide range of x86micro-arches, and it avoids a potential false dependency.The cost is an extra instruction byte.This could cause perf ups and downs from secondary effects,but I don't think it is possible to account for those inadvance, and that will likely also depend on exact micro-arch.This does bring LLVM x86 codegen more in line with existinggcc codegen, so if problems are exposed they are more likelyto occur for both compilers.Differential Revision: https://reviews.llvm.org/D129775 List of files: /llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected Wed, 20 Jul 2022 01:25:41 +0000 Sanjay Patel <spatel@rotateright.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected#c11051a4 [SelectionDAG] Add a freeze to ISD::ABS expansion.I had initially assumed this was the problem withhttps://github.com/llvm/llvm-project/issues/55271#issuecomment-1133426243But it turns out that was a simpler issue. This patch is stillmore correct than what we were doing before so figured I'd submitit anyway.No test case because I'm not sure how to get an undef arounduntil expansion.Looking at the test deltas I wonder if it be valid to combine(sext_inreg (freeze (aextload X))) -> (freeze (sextload X)).Reviewed By: efriedmaDifferential Revision: https://reviews.llvm.org/D126175 List of files: /llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected Sun, 22 May 2022 21:13:30 +0000 Craig Topper <craig.topper@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected#8e132c5c [LegalizeTypes][ARM][X86] Change ExpandIntRes_ABS to use sra+xor+sub.Previously we used sra+add+xor if ADDCARRY is supported. This changesto sra+xor+sub is SUBCARRY is available.This is consistent with the recent change to the default expansionin LegalizeDAG.Differential Revision: https://reviews.llvm.org/D121039 List of files: /llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected Sat, 05 Mar 2022 02:53:54 +0000 Craig Topper <craig.topper@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected#440c4b70 [SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs expansion to use sra (X, size(X)-1); sub (xor (X, Y), Y).Previous we used sra (X, size(X)-1); xor (add (X, Y), Y).By placing sub at the end, we allow RISCV to combine sign_extend_inregwith it to form subw.Some X86 tests for Z - abs(X) seem to have improved as well.Other targets look to be a wash.I had to modify ARM's abs matching code to match from sub instead ofxor. Maybe instead ISD::ABS should be made legal. I'll try that inparallel to this patch.This is an alternative to D119099 which was focused on RISCV only.Reviewed By: RKSimonDifferential Revision: https://reviews.llvm.org/D119171 List of files: /llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected Mon, 21 Feb 2022 05:11:21 +0000 Craig Topper <craig.topper@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected#3ff9cc01 [X86] Use CMOVNS for abs instead of CMOVGE.CMOVGE reads SF and OF. CMOVNS only reads SF. This matches withother recent changes to use a single flag where possible. It alsomatches gcc codegen.I believe this technically changes whether the conditioanl move happenson INT_MIN, but for INT_MIN both registers are the same so it doesn'tmatter.Differential Revision: https://reviews.llvm.org/D111826 List of files: /llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected Thu, 14 Oct 2021 18:23:42 +0000 Craig Topper <craig.topper@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected#a80afc03 [UpdateTestChecks] Add UTC_ARGS support for update_{llc,cc}_test_checks.pyhttps://reviews.llvm.org/D69701 added support for on-the-fly argumentchanges for update scripts. I recently wanted to keep some manual checklines in a test generated by update_cc_test_checks.py in our CHERI fork, sothis commit adds support for UTC_ARGS in update_cc_test_checks.py. And sinceI was refactoring the code to be in common.py, I also added it forupdate_llc_test_checks.py.Reviewed By: jdoerfert, MaskRayDifferential Revision: https://reviews.llvm.org/D78478 List of files: /llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected Wed, 08 Jul 2020 09:59:50 +0000 Alex Richardson <Alexander.Richardson@cl.cam.ac.uk> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected#240aff80 Add initial tests for update_{llc_,cc_,}test_checks.pySummary:This commit adds basic tests for these update script to validate thatthey still work as expected. In the future we could extend these testswhenever new features are added to avoid introducing regressions.Reviewers: xbolva00, MaskRay, jdoerfertReviewed By: jdoerfertSubscribers: llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D70660 List of files: /llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected Fri, 13 Dec 2019 10:25:15 +0000 Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>