Changes in horizontal-store.ll

7d8060bc - [SLP]Improve reductions vectorization.

Tue, 05 Oct 2021 12:55:48 +0000

[SLP]Improve reductions vectorization.The pattern matching and vectgorization for reductions was not veryeffective. Some of of the possible reduction values were marked asexternal arguments, SLP could not find some reduction patterns becauseof too early attempt to vectorize pair of binops arguments, the cost ofconsts reductions was not correct. Patch addresses these issues andimproves the analysis/cost estimation and vectorization of thereductions.The most significant changes in SLP.NumVectorInstructions:Metric: SLP.NumVectorInstructions [140/14396]Program results results0 diff test-suite :: SingleSource/Benchmarks/Adobe-C++/loop_unroll.test 920.00 3548.00 285.7% test-suite :: SingleSource/Benchmarks/BenchmarkGame/n-body.test 66.00 122.00 84.8% test-suite :: MultiSource/Benchmarks/DOE-ProxyApps-C/miniGMG/miniGMG.test 100.00 128.00 28.0% test-suite :: MultiSource/Benchmarks/Prolangs-C/TimberWolfMC/timberwolfmc.test 664.00 810.00 22.0% test-suite :: MultiSource/Benchmarks/mafft/pairlocalalign.test 592.00 687.00 16.0% test-suite :: MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame.test 402.00 426.00 6.0% test-suite :: MultiSource/Applications/JM/lencod/lencod.test 1665.00 1745.00 4.8% test-suite :: External/SPEC/CINT2017rate/500.perlbench_r/500.perlbench_r.test 135.00 139.00 3.0% test-suite :: External/SPEC/CINT2017speed/600.perlbench_s/600.perlbench_s.test 135.00 139.00 3.0% test-suite :: MultiSource/Benchmarks/7zip/7zip-benchmark.test 388.00 397.00 2.3% test-suite :: MultiSource/Applications/JM/ldecod/ldecod.test 895.00 914.00 2.1% test-suite :: MultiSource/Benchmarks/MiBench/telecomm-gsm/telecomm-gsm.test 240.00 244.00 1.7% test-suite :: MultiSource/Benchmarks/mediabench/gsm/toast/toast.test 240.00 244.00 1.7% test-suite :: External/SPEC/CINT2017speed/602.gcc_s/602.gcc_s.test 820.00 832.00 1.5% test-suite :: External/SPEC/CINT2017rate/502.gcc_r/502.gcc_r.test 820.00 832.00 1.5% test-suite :: External/SPEC/CFP2017rate/526.blender_r/526.blender_r.test 14804.00 14914.00 0.7% test-suite :: MultiSource/Benchmarks/Bullet/bullet.test 8125.00 8183.00 0.7% test-suite :: External/SPEC/CINT2017speed/625.x264_s/625.x264_s.test 1330.00 1338.00 0.6% test-suite :: External/SPEC/CINT2017rate/525.x264_r/525.x264_r.test 1330.00 1338.00 0.6% test-suite :: External/SPEC/CFP2017rate/510.parest_r/510.parest_r.test 9832.00 9880.00 0.5% test-suite :: External/SPEC/CFP2017rate/511.povray_r/511.povray_r.test 5267.00 5291.00 0.5% test-suite :: External/SPEC/CFP2017rate/538.imagick_r/538.imagick_r.test 4018.00 4024.00 0.1% test-suite :: External/SPEC/CFP2017speed/638.imagick_s/638.imagick_s.test 4018.00 4024.00 0.1% test-suite :: External/SPEC/CFP2017speed/644.nab_s/644.nab_s.test 426.00 424.00 -0.5% test-suite :: External/SPEC/CFP2017rate/544.nab_r/544.nab_r.test 426.00 424.00 -0.5% test-suite :: External/SPEC/CINT2017rate/541.leela_r/541.leela_r.test 201.00 192.00 -4.5% test-suite :: External/SPEC/CINT2017speed/641.leela_s/641.leela_s.test 201.00 192.00 -4.5%644.nab_s and 544.nab_r - reduced number of shuffles but increased numberof useful vectorized instructions.641.leela_s and 541.leela_r - the function`@_ZN9FastBoard25get_pattern3_augment_specEiib` is not inlined anymorebut its body gets vectorized successfully. Before, the function wasinlined twice and vectorized just after inlining, currently it is notrequired. The vector code looks pretty similar, just like as it was before.Differential Revision: https://reviews.llvm.org/D111574 List of files: /llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll

79b1b4a5 - [Vectorizers][TTI] remove option to bypass creation of vector reduction intrinsics

Fri, 12 Feb 2021 13:07:29 +0000

[Vectorizers][TTI] remove option to bypass creation of vector reduction intrinsicsThe vector reduction intrinsics started life as experimental ops, so backend supportwas lacking. As part of promoting them to 1st-class intrinsics, however, codegensupport was added/improved:D58015D90247So I think it is safe to now remove this complication from IR.Note that we still have an IR-level codegen expansion pass for these as discussedin D95690. Removing that is another step in simplifying the logic. Also note thatx86 was already unconditionally forming reductions in IR, so there should be nodifference for x86.I spot checked a couple of the tests here by running them through opt+llc and didnot see any asm diffs.If we do find functional differences for other targets, it should be possibleto (at least temporarily) restore the shuffle IR with the ExpandReductions IRpass.Differential Revision: https://reviews.llvm.org/D96552 List of files: /llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll

9b296102 - Use unary CreateShuffleVector if possible

Tue, 29 Dec 2020 22:28:17 +0000

Use unary CreateShuffleVector if possibleAs mentioned in D93793, there are quite a few places where unary `IRBuilder::CreateShuffleVector(X, Mask)` can be usedinstead of `IRBuilder::CreateShuffleVector(X, Undef, Mask)`.Let's update them.Actually, it would have been more natural if the patches were made in this order:(1) let them use unary CreateShuffleVector first(2) update IRBuilder::CreateShuffleVector to use poison as a placeholder value (D93793)The order is swapped, but in terms of correctness it is still fine.Reviewed By: spatelDifferential Revision: https://reviews.llvm.org/D93923 List of files: /llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll

c195ae2f - [SLPVectorizer][X86][AMDGPU] Remove fcmp+select to fmin/fmax reduction support.

Wed, 09 Sep 2020 20:45:36 +0000

[SLPVectorizer][X86][AMDGPU] Remove fcmp+select to fmin/fmax reduction support.Previously we could match fcmp+select to a reduction if the fcmp hadthe nonans fast math flag. But if the select had the nonans fastmath flag, InstCombine would turn it into a fminnum/fmaxnum intrinsicbefore SLP gets to it. Seems fairly likely that if one of thefcmp+select pair have the fast math flag, they both would.My plan is to start vectorizing the fmaxnum/fminnum version soon,but I wanted to get this code out as it had some of the strangestfast math flag behaviors. List of files: /llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll

cee313d2 - Revert "Temporarily Revert "Add basic loop fusion pass.""

Wed, 17 Apr 2019 04:52:47 +0000

Revert "Temporarily Revert "Add basic loop fusion pass.""The reversion apparently deleted the test/Transforms directory.Will be re-reverting again.llvm-svn: 358552 List of files: /llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll

3b416db1 - [SLP] Recognize min/max pattern using instructions producing same values.

Mon, 02 Jul 2018 17:55:31 +0000

[SLP] Recognize min/max pattern using instructions producing same values.Summary: It is common to have the following min/max pattern during the intermediate stages of SLP since we only optimize at the end. This patch tries to catch such patterns and allow more vectorization. %1 = extractelement <2 x i32> %a, i32 0 %2 = extractelement <2 x i32> %a, i32 1 %cond = icmp sgt i32 %1, %2 %3 = extractelement <2 x i32> %a, i32 0 %4 = extractelement <2 x i32> %a, i32 1 %select = select i1 %cond, i32 %3, i32 %4Author: FarhanaAleenReviewed By: ABataev, RKSimon, spatelDifferential Revision: https://reviews.llvm.org/D47608llvm-svn: 336130 List of files: /llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll

078cd48a - [SLP] Add testcases of min/max reduction pattern for AMDGPU.

Mon, 11 Jun 2018 20:29:31 +0000

[SLP] Add testcases of min/max reduction pattern for AMDGPU.Author: FarhanaAleenllvm-svn: 334435 List of files: /llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll