<?xml version="1.0"?>
<?xml-stylesheet type="text/xsl" href="/rss.xsl.xml"?>
<rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/">
<channel>
    <title>Changes in vplan_hcfg_stress_test.ll</title>
    <description></description>
    <language>en</language>
    <copyright>Copyright 2015</copyright>
    <generator>Java</generator><item>
        <title>cee313d2 - Revert &quot;Temporarily Revert &quot;Add basic loop fusion pass.&quot;&quot;</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/vplan_hcfg_stress_test.ll#cee313d2</link>
        <description>Revert &quot;Temporarily Revert &quot;Add basic loop fusion pass.&quot;&quot;The reversion apparently deleted the test/Transforms directory.Will be re-reverting again.llvm-svn: 358552

            List of files:
            /llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/vplan_hcfg_stress_test.ll</description>
        <pubDate>Wed, 17 Apr 2019 04:52:47 +0000</pubDate>
        <dc:creator>Eric Christopher &lt;echristo@gmail.com&gt;</dc:creator>
    </item>
<item>
        <title>168d04d5 - [VPlan] Reland r332654 and silence unused func warning</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/vplan_hcfg_stress_test.ll#168d04d5</link>
        <description>[VPlan] Reland r332654 and silence unused func warningr332654 was reverted due to an unused function warning inrelease build. This commit includes the same code with thewarning silenced.Differential Revision: https://reviews.llvm.org/D44338llvm-svn: 332860

            List of files:
            /llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/vplan_hcfg_stress_test.ll</description>
        <pubDate>Mon, 21 May 2018 18:14:23 +0000</pubDate>
        <dc:creator>Diego Caballero &lt;diego.caballero@intel.com&gt;</dc:creator>
    </item>
<item>
        <title>f58ad312 - [LV][VPlan] Build plain CFG with simple VPInstructions for outer loops.</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/vplan_hcfg_stress_test.ll#f58ad312</link>
        <description>[LV][VPlan] Build plain CFG with simple VPInstructions for outer loops.Patch #3 from VPlan Outer Loop Vectorization Patch Series #1(RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119523.html).Expected to be NFC for the current inner loop vectorization path. Itintroduces the basic algorithm to build the VPlan plain CFG (single-levelCFG, no hierarchical CFG (H-CFG), yet) in the VPlan-native vectorizationpath using VPInstructions. It includes:  - VPlanHCFGBuilder: Main class to build the VPlan H-CFG (plain CFG without nested regions, for now).  - VPlanVerifier: Main class with utilities to check the consistency of a H-CFG.  - VPlanBlockUtils: Main class with utilities to manipulate VPBlockBases in VPlan.Reviewers: rengolin, fhahn, mkuper, mssimpso, a.elovikov, hfinkel, aprantl.Differential Revision: https://reviews.llvm.org/D44338llvm-svn: 332654

            List of files:
            /llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/vplan_hcfg_stress_test.ll</description>
        <pubDate>Thu, 17 May 2018 19:24:47 +0000</pubDate>
        <dc:creator>Diego Caballero &lt;diego.caballero@intel.com&gt;</dc:creator>
    </item>
</channel>
</rss>
