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    <title>Changes in cde-integer.s</title>
    <description></description>
    <language>en</language>
    <copyright>Copyright 2015</copyright>
    <generator>Java</generator><item>
        <title>dd4d0937 - [ARM] Add initial support for Custom Datapath Extension (CDE)</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/MC/ARM/cde-integer.s#dd4d0937</link>
        <description>[ARM] Add initial support for Custom Datapath Extension (CDE)Summary:This patch adds assembly-level support for a new Arm M-profilearchitecture extension, Custom Datapath Extension (CDE).A brief description of the extension is available athttps://developer.arm.com/architectures/instruction-sets/custom-instructionsThe latest specification for CDE is currently a beta release and isavailable athttps://static.docs.arm.com/ddi0607/aa/DDI0607A_a_armv8m_arm_supplement_cde.pdfCDE allows chip vendors to add custom CPU instructions.  The CDEinstructions re-use the same encoding space as existing coprocessorinstructions (such as MRC, MCR, CDP etc.). Each coprocessor in rangecp0-cp7 can be configured as either general purpose (GCP) or customdatapath (CDEv1).  This configuration is defined by the CPU vendor andis provided to LLVM using 8 subtarget features: cdecp0 ... cdecp7.The semantics of CDE instructions are implementation-defined, but theinstructions are guaranteed to be pure (that is, they are stateless,they do not access memory or any registers except their explicitinputs/outputs).CDE requires the CPU to support at least Armv8.0-M mainlinearchitecture. CDE includes 3 sets of instructions:* Instructions that operate on general purpose registers and NZCV  flags* Instructions that operate on the S or D register file (require  either FP or MVE extension)* Instructions that operate on the Q register file, require MVEThe user-facing names that can be specified on the command line arethe same as the 8 subtarget feature names. For example:    $ clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3tells the compiler that the coprocessors 0 and 3 are configured asCDEv1 and the remaining coprocessors are configured as GCP (which isthe default).Reviewers: simon_tatham, ostannard, dmgreen, eli.friedmanReviewed By: simon_tathamSubscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commitsTags: #clang, #llvmDifferential Revision: https://reviews.llvm.org/D74044

            List of files:
            /llvm-project-15.0.7/llvm/test/MC/ARM/cde-integer.s</description>
        <pubDate>Mon, 17 Feb 2020 15:37:49 +0000</pubDate>
        <dc:creator>Mikhail Maltsev &lt;mikhail.maltsev@arm.com&gt;</dc:creator>
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