en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir#d391e4fe [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFCBe more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth.Helps prevent future scheduler model mismatches like those that were only addressed in D44687.Differential Revision: https://reviews.llvm.org/D113302 List of files: /llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir Sun, 07 Nov 2021 15:06:54 +0000 Simon Pilgrim <llvm-dev@redking.me.uk> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir#fae05692 CodeGen: Print/parse LLTs in MachineMemOperandsThis will currently accept the old number of bytes syntax, and convertit to a scalar. This should be removed in the near future (I think Iconverted all of the tests already, but likely missed a few).Not sure what the exact syntax and policy should be. We can continueprinting the number of bytes for non-generic instructions to avoidtest churn and only allow non-scalar types for generic instructions.This will currently print the LLT in parentheses, but accept parsingthe existing integers and implicitly converting to scalar. Theparentheses are a bit ugly, but the parser logic seems unable to dealwithout either parentheses or some keyword to indicate the start of atype. List of files: /llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir Thu, 20 May 2021 02:25:51 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir#48904e94 [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsingSummary:This catches malformed mir files which specify alignment as log2 instead of pow2.See https://reviews.llvm.org/D65945 for reference,This is patch is part of a series to introduce an Alignment type.See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.htmlSee this patch for the introduction of the type: https://reviews.llvm.org/D64790Reviewers: courbetSubscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D67433llvm-svn: 371608 List of files: /llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir Wed, 11 Sep 2019 11:16:48 +0000 Guillaume Chatelet <gchatelet@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir#80aa2290 [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.Summary:This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimonReviewed By: RKSimonSubscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D60228llvm-svn: 357802 List of files: /llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir Fri, 05 Apr 2019 19:28:09 +0000 Craig Topper <craig.topper@intel.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir#8b2ab91a [DebugInfo][X86] Add start-after flags to MIR testsThese tests would fail with -verify-machineinstrs because the MIgenerated from the IR would be merged with the one already in the MIRfiles, and we get the following error:```*** Bad machine code: Function has NoVRegs property but there are VReg operands ***- function: f```Differential Revision: https://reviews.llvm.org/D49191llvm-svn: 336907 List of files: /llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir Thu, 12 Jul 2018 14:36:48 +0000 Francis Visoiu Mistrih <francisvm@yahoo.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir#2c864551 [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.In order to set breakpoints on labels and list source code aroundlabels, we need collect debug information for labels, i.e., labelname, the function label belong, line number in the file, and theaddress label located. In order to keep these information in LLVMIR and to allow backend to generate debug information correctly.We create a new kind of metadata for labels, DILabel. The formatof DILabel is!DILabel(scope: !1, name: "foo", file: !2, line: 3)We hope to keep debug information as much as possible even thecode is optimized. So, we create a new kind of intrinsic for labelmetadata to avoid the metadata is eliminated with basic block.The intrinsic will keep existing if we keep it from optimized out.The format of the intrinsic isllvm.dbg.label(metadata !1)It has only one argument, that is the DILabel metadata. Theintrinsic will follow the label immediately. Backend could get thelabel metadata through the intrinsic's parameter.We also create DIBuilder API for labels to be used by Frontend.Frontend could use createLabel() to allocate DILabel objects, and useinsertLabel() to insert llvm.dbg.label intrinsic in LLVM IR.Differential Revision: https://reviews.llvm.org/D45024Patch by Hsiangkai Wang.llvm-svn: 331841 List of files: /llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir Wed, 09 May 2018 02:40:45 +0000 Shiva Chen <shiva0217@gmail.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir#43e94b15 Followup on Proposal to move MIR physical register namespace to '$' sigil.Discussed here:http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.htmlIn preparation for adding support for named vregs we are changing the sigil forphysical registers in MIR to '$' from '%'. This will prevent name clashes ofnamed physical register with named vregs.llvm-svn: 323922 List of files: /llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir Wed, 31 Jan 2018 22:04:26 +0000 Puyan Lotfi <puyan@puyan.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir#26f9a0c5 [dwarfdump] Add verbose output for .debug-line sectionThis patch adds dumping of line table instructions as well as the finalstate at each specified pc value in verbose mode. This is essentiallythe same as the default in Darwin's dwarfdump. Dumping the actual linetable opcodes can be particularly useful for something like debugging abad `.debug_line` section.Differential revision: https://reviews.llvm.org/D37971llvm-svn: 313910 List of files: /llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir Thu, 21 Sep 2017 20:15:30 +0000 Jonas Devlieghere <jonas@devlieghere.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir#16aa4cf7 llvm-dwarfdump: Make -brief the default and add a -verbose option instead.Differential Revision: https://reviews.llvm.org/D37717llvm-svn: 312972 List of files: /llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir Mon, 11 Sep 2017 23:05:20 +0000 Adrian Prantl <aprantl@apple.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir#fb26d9a2 MIR: remove explicit "noVRegs" property.We can infer this from the incoming MIR, so there's no reason torepresent it with a special flag.llvm-svn: 304246 List of files: /llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir Tue, 30 May 2017 21:28:57 +0000 Tim Northover <tnorthover@apple.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir#fb31da13 Don't generate line&scope debug info for meta-instructions.MachineInstructions that don't generate any code (such asIMPLICIT_DEFs) should not generate any debug info either.Fixes PR33107.https://bugs.llvm.org/show_bug.cgi?id=33107This reapplies r303566 without any modifications. The stage2 buildfailures persisted even after reverting this patch, and looking backthrough history, it looks like these tests are flaky.llvm-svn: 303575 List of files: /llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir Mon, 22 May 2017 20:47:09 +0000 Adrian Prantl <aprantl@apple.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir#4c047f89 Don't generate line&scope debug info for meta-instructions.MachineInstructions that don't generate any code (such asIMPLICIT_DEFs) should not generate any debug info either.Fixes PR33107.https://bugs.llvm.org/show_bug.cgi?id=33107llvm-svn: 303566 List of files: /llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/empty-inline.mir Mon, 22 May 2017 16:21:02 +0000 Adrian Prantl <aprantl@apple.com>