en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#f510045d [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.Take advantage of D117117 to simplify all {{\[}} to [ and {{\]}} to ].Differential Revision: https://reviews.llvm.org/D117298 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Fri, 14 Jan 2022 11:03:21 +0000 Jay Foad <jay.foad@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#d839749a [DAG] Improve Aliasing of operations to static allocaRe-recommiting after landing DAG extension-crash fix.Recommiting after adding check to avoid miscomputing alias informationon addresses of the same base but different subindices.Memory accesses offset from frame indices may alias, e.g., wemay merge write from function arguments passed on the stack when theyare contiguous. As a result, when checking aliasing, we consider theunderlying frame index's offset from the stack pointer.Static allocs are realized as stack objects in SelectionDAG, but itsoffset is not set until post-DAG causing DAGCombiner's alias check toconsider access to static allocas to frequently alias. Modify isAliasto consider access between static allocas and access from other frameobjects to be considered aliasing.Many test changes are included here. Most are fixes for tests whichindirectly relied on our aliasing ability and needed to be modified topreserve their original intent.The remaining tests have minor improvements due to relaxedordering. The exception is CodeGen/X86/2011-10-19-widen_vselect.llwhich has a minor degradation dispite though the pre-legalized DAG isimproved.Reviewers: rnk, mkuper, jonpa, hfinkel, uweigandReviewed By: rnkSubscribers: sdardis, nemanjai, javed.absar, llvm-commitsDifferential Revision: https://reviews.llvm.org/D33345llvm-svn: 308350 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Tue, 18 Jul 2017 20:06:24 +0000 Nirav Dave <niravd@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#a15e080b Revert r308025 due to uncovering a crash in SelectionDAG. This is filedwith a minimal test case in http://llvm.org/PR33833.Original commit message: Improve Aliasing of operations to static allocallvm-svn: 308271 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Tue, 18 Jul 2017 07:53:47 +0000 Chandler Carruth <chandlerc@gmail.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#a8f63af9 Improve Aliasing of operations to static allocaRecommiting after adding check to avoid miscomputing alias informationon addresses of the same base but different subindices.Memory accesses offset from frame indices may alias, e.g., wemay merge write from function arguments passed on the stack when theyare contiguous. As a result, when checking aliasing, we consider theunderlying frame index's offset from the stack pointer.Static allocs are realized as stack objects in SelectionDAG, but itsoffset is not set until post-DAG causing DAGCombiner's alias check toconsider access to static allocas to frequently alias. Modify isAliasto consider access between static allocas and access from other frameobjects to be considered aliasing.Many test changes are included here. Most are fixes for tests whichindirectly relied on our aliasing ability and needed to be modified topreserve their original intent.The remaining tests have minor improvements due to relaxedordering. The exception is CodeGen/X86/2011-10-19-widen_vselect.llwhich has a minor degradation dispite though the pre-legalized DAG isimproved.Reviewers: rnk, mkuper, jonpa, hfinkel, uweigandReviewed By: rnkSubscribers: sdardis, nemanjai, javed.absar, llvm-commitsDifferential Revision: https://reviews.llvm.org/D33345llvm-svn: 308025 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Fri, 14 Jul 2017 13:56:21 +0000 Nirav Dave <niravd@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#b3873670 Revert "[DAG] Improve Aliasing of operations to static alloca"Reverting as it breaks tramp3d-v4 in the llvm test-suite. I added somecomments to https://reviews.llvm.org/D33345 about it.This reverts commit r307546.llvm-svn: 307589 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Mon, 10 Jul 2017 20:51:30 +0000 Matthias Braun <matze@braunis.de> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#163e1ad9 [DAG] Improve Aliasing of operations to static allocaMemory accesses offset from frame indices may alias, e.g., wemay merge write from function arguments passed on the stack when theyare contiguous. As a result, when checking aliasing, we consider theunderlying frame index's offset from the stack pointer.Static allocs are realized as stack objects in SelectionDAG, but itsoffset is not set until post-DAG causing DAGCombiner's alias check toconsider access to static allocas to frequently alias. Modify isAliasto consider access between static allocas and access from other frameobjects to be considered aliasing.Many test changes are included here. Most are fixes for tests whichindirectly relied on our aliasing ability and needed to be modified topreserve their original intent.The remaining tests have minor improvements due to relaxedordering. The exception is CodeGen/X86/2011-10-19-widen_vselect.llwhich has a minor degradation dispite though the pre-legalized DAG isimproved.Reviewers: rnk, mkuper, jonpa, hfinkel, uweigandReviewed By: rnkSubscribers: sdardis, nemanjai, javed.absar, llvm-commitsDifferential Revision: https://reviews.llvm.org/D33345llvm-svn: 307546 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Mon, 10 Jul 2017 15:39:41 +0000 Nirav Dave <niravd@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#54e22f33 In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled. Recommiting with compiler time improvements Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner. * Simplify Consecutive Merge Store Candidate Search Now that address aliasing is much less conservative, push through simplified store merging search and chain alias analysis which only checks for parallel stores through the chain subgraph. This is cleaner as the separation of non-interfering loads/stores from the store-merging logic. When merging stores search up the chain through a single load, and finds all possible stores by looking down from through a load and a TokenFactor to all stores visited. This improves the quality of the output SelectionDAG and the output Codegen (save perhaps for some ARM cases where we correctly constructs wider loads, but then promotes them to float operations which appear but requires more expensive constant generation). Some minor peephole optimizations to deal with improved SubDAG shapes (listed below) Additional Minor Changes: 1. Finishes removing unused AliasLoad code 2. Unifies the chain aggregation in the merged stores across code paths 3. Re-add the Store node to the worklist after calling SimplifyDemandedBits. 4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is arbitrary, but seems sufficient to not cause regressions in tests. 5. Remove Chain dependencies of Memory operations on CopyfromReg nodes as these are captured by data dependence 6. Forward loads-store values through tokenfactors containing {CopyToReg,CopyFromReg} Values. 7. Peephole to convert buildvector of extract_vector_elt to extract_subvector if possible (see CodeGen/AArch64/store-merge.ll) 8. Store merging for the ARM target is restricted to 32-bit as some in some contexts invalid 64-bit operations are being generated. This can be removed once appropriate checks are added. This finishes the change Matt Arsenault started in r246307 and jyknight's original patch. Many tests required some changes as memory operations are now reorderable, improving load-store forwarding. One test in particular is worth noting: CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store forwarding converts a load-store pair into a parallel store and a memory-realized bitcast of the same value. However, because we lose the sharing of the explicit and implicit store values we must create another local store. A similar transformation happens before SelectionDAG as well. Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnlellvm-svn: 297695 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Tue, 14 Mar 2017 00:34:14 +0000 Nirav Dave <niravd@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#ce52b807 [SDAG] Revert r296476 (and r296486, r296668, r296690).This patch causes compile times for some patterns to explode. I havea (large, unreduced) test case that slows down by more than 20x andseveral test cases slow down by 2x. I'm sending some of the test casesdirectly to Nirav and following up with more details in the review log,but this should unblock anyone else hitting this.llvm-svn: 296862 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Fri, 03 Mar 2017 10:02:25 +0000 Chandler Carruth <chandlerc@gmail.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#f830dec3 In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled. Recommiting after fixup of 32-bit aliasing sign offset bug in DAGCombiner. * Simplify Consecutive Merge Store Candidate Search Now that address aliasing is much less conservative, push through simplified store merging search and chain alias analysis which only checks for parallel stores through the chain subgraph. This is cleaner as the separation of non-interfering loads/stores from the store-merging logic. When merging stores search up the chain through a single load, and finds all possible stores by looking down from through a load and a TokenFactor to all stores visited. This improves the quality of the output SelectionDAG and the output Codegen (save perhaps for some ARM cases where we correctly constructs wider loads, but then promotes them to float operations which appear but requires more expensive constant generation). Some minor peephole optimizations to deal with improved SubDAG shapes (listed below) Additional Minor Changes: 1. Finishes removing unused AliasLoad code 2. Unifies the chain aggregation in the merged stores across code paths 3. Re-add the Store node to the worklist after calling SimplifyDemandedBits. 4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is arbitrary, but seems sufficient to not cause regressions in tests. 5. Remove Chain dependencies of Memory operations on CopyfromReg nodes as these are captured by data dependence 6. Forward loads-store values through tokenfactors containing {CopyToReg,CopyFromReg} Values. 7. Peephole to convert buildvector of extract_vector_elt to extract_subvector if possible (see CodeGen/AArch64/store-merge.ll) 8. Store merging for the ARM target is restricted to 32-bit as some in some contexts invalid 64-bit operations are being generated. This can be removed once appropriate checks are added. This finishes the change Matt Arsenault started in r246307 and jyknight's original patch. Many tests required some changes as memory operations are now reorderable, improving load-store forwarding. One test in particular is worth noting: CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store forwarding converts a load-store pair into a parallel store and a memory-realized bitcast of the same value. However, because we lose the sharing of the explicit and implicit store values we must create another local store. A similar transformation happens before SelectionDAG as well. Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnlellvm-svn: 296476 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Tue, 28 Feb 2017 14:24:15 +0000 Nirav Dave <niravd@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#73cd0194 Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."This reverts commit r296252 until 256-bit operations are more efficiently generated in X86.llvm-svn: 296279 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Sun, 26 Feb 2017 01:27:32 +0000 Nirav Dave <niravd@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#beabf456 In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled. Recommiting after fixup of 32-bit aliasing sign offset bug in DAGCombiner. * Simplify Consecutive Merge Store Candidate Search Now that address aliasing is much less conservative, push through simplified store merging search and chain alias analysis which only checks for parallel stores through the chain subgraph. This is cleaner as the separation of non-interfering loads/stores from the store-merging logic. When merging stores search up the chain through a single load, and finds all possible stores by looking down from through a load and a TokenFactor to all stores visited. This improves the quality of the output SelectionDAG and the output Codegen (save perhaps for some ARM cases where we correctly constructs wider loads, but then promotes them to float operations which appear but requires more expensive constant generation). Some minor peephole optimizations to deal with improved SubDAG shapes (listed below) Additional Minor Changes: 1. Finishes removing unused AliasLoad code 2. Unifies the chain aggregation in the merged stores across code paths 3. Re-add the Store node to the worklist after calling SimplifyDemandedBits. 4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is arbitrary, but seems sufficient to not cause regressions in tests. 5. Remove Chain dependencies of Memory operations on CopyfromReg nodes as these are captured by data dependence 6. Forward loads-store values through tokenfactors containing {CopyToReg,CopyFromReg} Values. 7. Peephole to convert buildvector of extract_vector_elt to extract_subvector if possible (see CodeGen/AArch64/store-merge.ll) 8. Store merging for the ARM target is restricted to 32-bit as some in some contexts invalid 64-bit operations are being generated. This can be removed once appropriate checks are added. This finishes the change Matt Arsenault started in r246307 and jyknight's original patch. Many tests required some changes as memory operations are now reorderable, improving load-store forwarding. One test in particular is worth noting: CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store forwarding converts a load-store pair into a parallel store and a memory-realized bitcast of the same value. However, because we lose the sharing of the explicit and implicit store values we must create another local store. A similar transformation happens before SelectionDAG as well. Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnlellvm-svn: 296252 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Sat, 25 Feb 2017 11:43:58 +0000 Nirav Dave <niravd@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#93f9d5ce Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."This reverts commit r293893 which is miscompiling lua on ARM andbootstrapping for x86-windows.llvm-svn: 293915 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Thu, 02 Feb 2017 18:24:55 +0000 Nirav Dave <niravd@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#4442667f In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled. Recommiting after fixing X86 inc/dec chain bug. * Simplify Consecutive Merge Store Candidate Search Now that address aliasing is much less conservative, push through simplified store merging search and chain alias analysis which only checks for parallel stores through the chain subgraph. This is cleaner as the separation of non-interfering loads/stores from the store-merging logic. When merging stores search up the chain through a single load, and finds all possible stores by looking down from through a load and a TokenFactor to all stores visited. This improves the quality of the output SelectionDAG and the output Codegen (save perhaps for some ARM cases where we correctly constructs wider loads, but then promotes them to float operations which appear but requires more expensive constant generation). Some minor peephole optimizations to deal with improved SubDAG shapes (listed below) Additional Minor Changes: 1. Finishes removing unused AliasLoad code 2. Unifies the chain aggregation in the merged stores across code paths 3. Re-add the Store node to the worklist after calling SimplifyDemandedBits. 4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is arbitrary, but seems sufficient to not cause regressions in tests. 5. Remove Chain dependencies of Memory operations on CopyfromReg nodes as these are captured by data dependence 6. Forward loads-store values through tokenfactors containing {CopyToReg,CopyFromReg} Values. 7. Peephole to convert buildvector of extract_vector_elt to extract_subvector if possible (see CodeGen/AArch64/store-merge.ll) 8. Store merging for the ARM target is restricted to 32-bit as some in some contexts invalid 64-bit operations are being generated. This can be removed once appropriate checks are added. This finishes the change Matt Arsenault started in r246307 and jyknight's original patch. Many tests required some changes as memory operations are now reorderable, improving load-store forwarding. One test in particular is worth noting: CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store forwarding converts a load-store pair into a parallel store and a memory-realized bitcast of the same value. However, because we lose the sharing of the explicit and implicit store values we must create another local store. A similar transformation happens before SelectionDAG as well. Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnlellvm-svn: 293893 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Thu, 02 Feb 2017 14:39:42 +0000 Nirav Dave <niravd@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#d32a421f Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."This reverts commit r293184 which is failing in LTO buildsllvm-svn: 293188 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Thu, 26 Jan 2017 16:46:13 +0000 Nirav Dave <niravd@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#de6516c4 In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled. * Simplify Consecutive Merge Store Candidate Search Now that address aliasing is much less conservative, push through simplified store merging search and chain alias analysis which only checks for parallel stores through the chain subgraph. This is cleaner as the separation of non-interfering loads/stores from the store-merging logic. When merging stores search up the chain through a single load, and finds all possible stores by looking down from through a load and a TokenFactor to all stores visited. This improves the quality of the output SelectionDAG and the output Codegen (save perhaps for some ARM cases where we correctly constructs wider loads, but then promotes them to float operations which appear but requires more expensive constant generation). Some minor peephole optimizations to deal with improved SubDAG shapes (listed below) Additional Minor Changes: 1. Finishes removing unused AliasLoad code 2. Unifies the chain aggregation in the merged stores across code paths 3. Re-add the Store node to the worklist after calling SimplifyDemandedBits. 4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is arbitrary, but seems sufficient to not cause regressions in tests. 5. Remove Chain dependencies of Memory operations on CopyfromReg nodes as these are captured by data dependence 6. Forward loads-store values through tokenfactors containing {CopyToReg,CopyFromReg} Values. 7. Peephole to convert buildvector of extract_vector_elt to extract_subvector if possible (see CodeGen/AArch64/store-merge.ll) 8. Store merging for the ARM target is restricted to 32-bit as some in some contexts invalid 64-bit operations are being generated. This can be removed once appropriate checks are added. This finishes the change Matt Arsenault started in r246307 and jyknight's original patch. Many tests required some changes as memory operations are now reorderable, improving load-store forwarding. One test in particular is worth noting: CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store forwarding converts a load-store pair into a parallel store and a memory-realized bitcast of the same value. However, because we lose the sharing of the explicit and implicit store values we must create another local store. A similar transformation happens before SelectionDAG as well. Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnlellvm-svn: 293184 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Thu, 26 Jan 2017 16:02:24 +0000 Nirav Dave <niravd@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#f5bf03c7 Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."Reverting due to ARM MCJIT and MIPS LLD error.This reverts commit r289659.llvm-svn: 289667 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Wed, 14 Dec 2016 16:43:44 +0000 Nirav Dave <niravd@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#8527ab0a In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.Retrying after fixing after removing load-store factoring throughtoken factors in favor of improved token factor operand pruningSimplify Consecutive Merge Store Candidate SearchNow that address aliasing is much less conservative, push throughsimplified store merging search which only checks for parallel storesthrough the chain subgraph. This is cleaner as the separation ofnon-interfering loads/stores from the store-merging logic.Whem merging stores, search up the chain through a single load, andfinds all possible stores by looking down from through a load and aTokenFactor to all stores visited. This improves the quality of theoutput SelectionDAG and generally the output CodeGen (with someexceptions).Additional Minor Changes: 1. Finishes removing unused AliasLoad code 2. Unifies the the chain aggregation in the merged stores across code paths 3. Re-add the Store node to the worklist after calling SimplifyDemandedBits. 4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is arbitrary, but seemed sufficient to not cause regressions in tests.This finishes the change Matt Arsenault started in r246307 andjyknight's original patch.Many tests required some changes as memory operations are nowreorderable. Some tests relying on the order were changed to usevolatile memory operationsNoteworthy tests: CodeGen/AArch64/argument-blocks.ll - It's not entirely clear what the test_varargs_stackalign test is supposed to be asserting, but the new code looks right. CodeGen/AArch64/arm64-memset-inline.lli - CodeGen/AArch64/arm64-stur.ll - CodeGen/ARM/memset-inline.ll - The backend now generates *worse* code due to store merging succeeding, as we do do a 16-byte constant-zero store efficiently. CodeGen/AArch64/merge-store.ll - Improved, but there still seems to be an extraneous vector insert from an element to itself? CodeGen/PowerPC/ppc64-align-long-double.ll - Worse code emitted in this case, due to the improved store->load forwarding. CodeGen/X86/dag-merge-fast-accesses.ll - CodeGen/X86/MergeConsecutiveStores.ll - CodeGen/X86/stores-merging.ll - CodeGen/Mips/load-store-left-right.ll - Restored correct merging of non-aligned stores CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll - Improved. Correctly merges buffer_store_dword calls CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll - Improved. Sidesteps loading a stored value and merges two stores CodeGen/X86/pr18023.ll - This test has been removed, as it was asserting incorrect behavior. Non-volatile stores *CAN* be moved past volatile loads, and now are. CodeGen/X86/vector-idiv.ll - CodeGen/X86/vector-lzcnt-128.ll - It's basically impossible to tell what these tests are actually testing. But, looks like the code got better due to the memory operations being recognized as non-aliasing. CodeGen/X86/win32-eh.ll - Both loads of the securitycookie are now merged.Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnleSubscribers: wdng, nhaehnle, nemanjai, arsenm, weimingz, niravd, RKSimon, aemerson, qcolombet, dsanders, resistor, tstellarAMD, t.p.northover, spatelDifferential Revision: https://reviews.llvm.org/D14834llvm-svn: 289659 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Wed, 14 Dec 2016 15:44:26 +0000 Nirav Dave <niravd@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#bedb5d90 Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."This reverts commit r289221 which appears to be triggering an assertionllvm-svn: 289226 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Fri, 09 Dec 2016 17:18:24 +0000 Nirav Dave <niravd@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#fd51ff4f In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.Retrying after fixing overly aggressive load-store forwarding optimization.Simplify Consecutive Merge Store Candidate SearchNow that address aliasing is much less conservative, push throughsimplified store merging search which only checks for parallel storesthrough the chain subgraph. This is cleaner as the separation ofnon-interfering loads/stores from the store-merging logic.Whem merging stores, search up the chain through a single load, andfinds all possible stores by looking down from through a load and aTokenFactor to all stores visited. This improves the quality of theoutput SelectionDAG and generally the output CodeGen (with someexceptions).Additional Minor Changes: 1. Finishes removing unused AliasLoad code 2. Unifies the the chain aggregation in the merged stores across code paths 3. Re-add the Store node to the worklist after calling SimplifyDemandedBits. 4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is arbitrary, but seemed sufficient to not cause regressions in tests.This finishes the change Matt Arsenault started in r246307 andjyknight's original patch.Many tests required some changes as memory operations are nowreorderable. Some tests relying on the order were changed to usevolatile memory operationsNoteworthy tests: CodeGen/AArch64/argument-blocks.ll - It's not entirely clear what the test_varargs_stackalign test is supposed to be asserting, but the new code looks right. CodeGen/AArch64/arm64-memset-inline.lli - CodeGen/AArch64/arm64-stur.ll - CodeGen/ARM/memset-inline.ll - The backend now generates *worse* code due to store merging succeeding, as we do do a 16-byte constant-zero store efficiently. CodeGen/AArch64/merge-store.ll - Improved, but there still seems to be an extraneous vector insert from an element to itself? CodeGen/PowerPC/ppc64-align-long-double.ll - Worse code emitted in this case, due to the improved store->load forwarding. CodeGen/X86/dag-merge-fast-accesses.ll - CodeGen/X86/MergeConsecutiveStores.ll - CodeGen/X86/stores-merging.ll - CodeGen/Mips/load-store-left-right.ll - Restored correct merging of non-aligned stores CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll - Improved. Correctly merges buffer_store_dword calls CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll - Improved. Sidesteps loading a stored value and merges two stores CodeGen/X86/pr18023.ll - This test has been removed, as it was asserting incorrect behavior. Non-volatile stores *CAN* be moved past volatile loads, and now are. CodeGen/X86/vector-idiv.ll - CodeGen/X86/vector-lzcnt-128.ll - It's basically impossible to tell what these tests are actually testing. But, looks like the code got better due to the memory operations being recognized as non-aliasing. CodeGen/X86/win32-eh.ll - Both loads of the securitycookie are now merged.Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnleSubscribers: wdng, nhaehnle, nemanjai, arsenm, weimingz, niravd, RKSimon, aemerson, qcolombet, dsanders, resistor, tstellarAMD, t.p.northover, spatelDifferential Revision: https://reviews.llvm.org/D14834llvm-svn: 289221 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Fri, 09 Dec 2016 16:15:12 +0000 Nirav Dave <niravd@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll#a81682aa Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."This reverts commit r284151 which appears to be triggering a LTOfailures on Hexagonllvm-svn: 284157 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/XCore/varargs.ll Thu, 13 Oct 2016 20:23:25 +0000 Nirav Dave <niravd@google.com>