Changes in vec_shift7.ll

990939c8 - [CodeGen][X86] Remove unused check-prefixes from vec tests. NFCI.

Wed, 11 Nov 2020 07:32:08 +0000

[CodeGen][X86] Remove unused check-prefixes from vec tests. NFCI. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_shift7.ll

5a855551 - [X86] Regenerate vector shift tests. NFCI.

Tue, 27 Oct 2020 12:13:53 +0000

[X86] Regenerate vector shift tests. NFCI.Merge prefixes where possible, use 'X86' instead of 'X32' (which we try to only use for gnux32 triple tests). List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_shift7.ll

0c005be6 - [X86][SSE] getV4X86ShuffleImm8 - canonicalize broadcast masks

Wed, 29 Jul 2020 10:32:07 +0000

[X86][SSE] getV4X86ShuffleImm8 - canonicalize broadcast masksIf the mask input to getV4X86ShuffleImm8 only refers to a single source element (+ undefs) then canonicalize to a full broadcast.getV4X86ShuffleImm8 defaults to inline values for undefs, which can be useful for shuffle widening/narrowing but does leave SimplifyDemanded* calls thinking the shuffle depends on unnecessary elements.I'm still investigating what we should do more generally to avoid these undemanded elements, but broadcast cases was a simpler win. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_shift7.ll

e4d12bb2 - [DAGCombiner] Call SimplifyDemandedVectorElts from EXTRACT_VECTOR_ELT

Tue, 17 Jul 2018 09:45:35 +0000

[DAGCombiner] Call SimplifyDemandedVectorElts from EXTRACT_VECTOR_ELTIf we are only extracting vector elements via EXTRACT_VECTOR_ELT(s) we may be able to use SimplifyDemandedVectorElts to avoid unnecessary vector ops.Differential Revision: https://reviews.llvm.org/D49262llvm-svn: 337258 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_shift7.ll

25528d6d - [CodeGen] Unify MBB reference format in both MIR and debug output

Mon, 04 Dec 2017 17:18:51 +0000

[CodeGen] Unify MBB reference format in both MIR and debug outputAs part of the unification of the debug format and the MIR format, printMBB references as '%bb.5'.The MIR printer prints the IR name of a MBB only for block definitions.* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'* grep -nr 'BB#' and fixDifferential Revision: https://reviews.llvm.org/D40422llvm-svn: 319665 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_shift7.ll

d9fb1578 - [X86][SSE2] Fix asm string for movq (Move Quadword) instruction.

Wed, 26 Apr 2017 07:08:44 +0000

[X86][SSE2] Fix asm string for movq (Move Quadword) instruction.Replace "mov{d|q}" with "movq".Differential Revision: https://reviews.llvm.org/D32220llvm-svn: 301386 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_shift7.ll

5c4efcdd - [X86][SSE] Attempt to extract vector elements through target shuffles

Mon, 27 Feb 2017 21:01:57 +0000

[X86][SSE] Attempt to extract vector elements through target shufflesDAGCombiner already supports peeking thorough shuffles to improve vector element extraction, but legalization often leaves us in situations where we need to extract vector elements after shuffles have already been lowered.This patch adds support for VECTOR_EXTRACT_ELEMENT/PEXTRW/PEXTRB instructions to attempt to handle target shuffles as well. I've covered some basic scenarios including handling shuffle mask scaling and the implicit zero-extension of PEXTRW/PEXTRB, there is more that could be done here (that I've mentioned in TODOs) but I haven't found many cases where its worth it.Differential Revision: https://reviews.llvm.org/D30176llvm-svn: 296381 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_shift7.ll

890b4159 - [X86][SSE] Regenerate vector shift tests

Sat, 09 Jul 2016 20:55:20 +0000

[X86][SSE] Regenerate vector shift testsllvm-svn: 274987 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_shift7.ll

03dd1082 - LegalizeTypes: Handle shift by 0 in ExpandShiftByConstant.

Fri, 06 Mar 2015 01:13:01 +0000

LegalizeTypes: Handle shift by 0 in ExpandShiftByConstant.Though such shifts are usually optimized away by combiner, we still canencounter them after a vector shift is legalized.llvm-svn: 231443 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_shift7.ll