Changes in vec_insert-7.ll

7d8fd4f5 - [DAG] visitINSERT_VECTOR_ELT - attempt to reconstruct BUILD_VECTOR before other fold interfere

Mon, 13 Jun 2022 10:47:14 +0000

[DAG] visitINSERT_VECTOR_ELT - attempt to reconstruct BUILD_VECTOR before other fold interfereAnother issue unearthed by D127115We take a long time to canonicalize an insert_vector_elt chain before being able to convert it into a build_vector - even if they are already in ascending insertion order, we fold the nodes one at a time into the build_vector 'seed', leaving plenty of time for other folds to alter it (in particular recognising when they come from extract_vector_elt resulting in a shuffle_vector that is much harder to fold with).D127115 makes this particularly difficult as we're almost guaranteed to have the lost the sequence before all possible insertions have been folded.This patch proposes to begin at the last insertion and attempt to collect all the (oneuse) insertions right away and create the build_vector before its too late.Differential Revision: https://reviews.llvm.org/D127595 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

50d0804a - [X86] Replace X32 check prefix with X86

Sat, 11 Jun 2022 13:30:27 +0000

[X86] Replace X32 check prefix with X86We try to use X32 only for gnux32 triple cases List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

0aef747b - [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated

Fri, 11 Jun 2021 20:26:17 +0000

[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogeneratedThe motivation is that the update script has at least two deviations(`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) fromwhat pretty much all the checklines were generated with,and most of the tests are still not updated, so each time one of thenon-up-to-date tests is updated to see the effect of the code change,there is a lot of noise. Instead of having to deal with that eachtime, let's just deal with everything at once.This has been done via:```cd llvm-project/llvm/test/CodeGen/X86grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc```Not all tests were regenerated, however. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

af1accdd - [X86] Teach computeKnownBitsForTargetNode that the upper half of X86ISD::MOVQ2DQ is all zero.

Sun, 31 May 2020 00:04:56 +0000

[X86] Teach computeKnownBitsForTargetNode that the upper half of X86ISD::MOVQ2DQ is all zero. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

2a372ba5 - [X86] Add custom type legalization for bitcasting mmx to v2i32/v4i16/v8i8 to use movq2dq instead of going through memory.

Thu, 15 Aug 2019 18:23:37 +0000

[X86] Add custom type legalization for bitcasting mmx to v2i32/v4i16/v8i8 to use movq2dq instead of going through memory.llvm-svn: 369031 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

8b5f2ab2 - Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."

Wed, 07 Aug 2019 16:24:26 +0000

Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."The assert that caused this to be reverted should be fixed now.Original commit message:This patch changes our defualt legalization behavior for 16, 32, and64 bit vectors with i8/i16/i32/i64 scalar types from promotion towidening. For example, v8i8 will now be widened to v16i8 instead ofpromoted to v8i16. This keeps the elements widths the same and padswith undef elements. We believe this is a better legalization strategy.But it carries some issues due to the fragmented vector ISA. Forexample, i8 shifts and multiplies get widened and then later haveto be promoted/split into vXi16 vectors.This has the potential to cause regressions so we wanted to getit in early in the 10.0 cycle so we have plenty of time toaddress them.Next steps will be to merge tests that explicitly test the commandline option. And then we can remove the option and its associatedcode.llvm-svn: 368183 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

bd0d97e1 - Revert "[X86] Enable -x86-experimental-vector-widening-legalization by default."

Tue, 06 Aug 2019 23:00:43 +0000

Revert "[X86] Enable -x86-experimental-vector-widening-legalization by default."This reverts commit 3de33245d2c992c9e0af60372043540b60f3a810.This commit broke the MSan buildbots. Seehttps://reviews.llvm.org/rL367901 for more information.llvm-svn: 368107 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

3de33245 - [X86] Enable -x86-experimental-vector-widening-legalization by default.

Mon, 05 Aug 2019 18:25:36 +0000

[X86] Enable -x86-experimental-vector-widening-legalization by default.This patch changes our defualt legalization behavior for 16, 32, and64 bit vectors with i8/i16/i32/i64 scalar types from promotion towidening. For example, v8i8 will now be widened to v16i8 instead ofpromoted to v8i16. This keeps the elements widths the same and padswith undef elements. We believe this is a better legalization strategy.But it carries some issues due to the fragmented vector ISA. Forexample, i8 shifts and multiplies get widened and then later haveto be promoted/split into vXi16 vectors.This has the potential to cause regressions so we wanted to getit in early in the 10.0 cycle so we have plenty of time toaddress them.Next steps will be to merge tests that explicitly test the commandline option. And then we can remove the option and its associatedcode.llvm-svn: 367901 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

509a8a3c - [DAGCombiner][X86][SystemZ][AArch64] Combine some cases of (bitcast (build_vector constants)) between legalize types and legalize dag.

Mon, 04 Mar 2019 19:12:16 +0000

[DAGCombiner][X86][SystemZ][AArch64] Combine some cases of (bitcast (build_vector constants)) between legalize types and legalize dag.This patch enables combining integer bitcasts of integer build vectors when the new scalar type is legal. I've avoided floating point because the implementation bitcasts float to int along the way and we would need to check the intermediate types for legalityDifferential Revision: https://reviews.llvm.org/D58884llvm-svn: 355324 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

4bb07791 - [X86] Add custom type legalization for v2i32/v4i16/v8i8->mmx bitcasts to avoid a store/load to/from the stack.

Sun, 02 Dec 2018 05:46:50 +0000

[X86] Add custom type legalization for v2i32/v4i16/v8i8->mmx bitcasts to avoid a store/load to/from the stack.Widen the input to a 128 bit vector by padding with undef elements. Then use a movdq2q to convert from xmm register to mmx register.llvm-svn: 348086 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

ec096a1d - [X86] Custom type legalize v2i32/v4i16/v8i8->i64 bitcasts in 64-bit mode similar to what's done when the destination is f64.

Sun, 02 Dec 2018 05:46:48 +0000

[X86] Custom type legalize v2i32/v4i16/v8i8->i64 bitcasts in 64-bit mode similar to what's done when the destination is f64.The generic legalizer will fall back to a stack spill that uses a truncating store. That store will get expanded into a shuffle and non-truncating store on pre-avx512 targets. Once that happens the stack store/load pair will be combined away leaving behind the shuffle and bitcasts. On avx512 targets the truncating store is legal so doesn't get folded away.By custom legalizing it we can avoid this churn and maybe produce better code.llvm-svn: 348085 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

ca38c762 - [TargetLowering] Add vector BITCAST support to SimplifyDemandedVectorElts

Tue, 06 Mar 2018 22:32:01 +0000

[TargetLowering] Add vector BITCAST support to SimplifyDemandedVectorEltsNotably helps cleanup after legalization of vector typesDifferential Revision: https://reviews.llvm.org/D43674llvm-svn: 326838 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

8da142bf - [SelectionDAG] SimplifyDemandedVectorElts - add support for VECTOR_INSERT_ELT

Sat, 17 Feb 2018 21:49:40 +0000

[SelectionDAG] SimplifyDemandedVectorElts - add support for VECTOR_INSERT_ELTDifferential Revision: https://reviews.llvm.org/D43431llvm-svn: 325449 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

25528d6d - [CodeGen] Unify MBB reference format in both MIR and debug output

Mon, 04 Dec 2017 17:18:51 +0000

[CodeGen] Unify MBB reference format in both MIR and debug outputAs part of the unification of the debug format and the MIR format, printMBB references as '%bb.5'.The MIR printer prints the IR name of a MBB only for block definitions.* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'* grep -nr 'BB#' and fixDifferential Revision: https://reviews.llvm.org/D40422llvm-svn: 319665 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

9d7bb0cb - [CodeGen] Print register names in lowercase in both MIR and debug output

Tue, 28 Nov 2017 17:15:09 +0000

[CodeGen] Print register names in lowercase in both MIR and debug outputAs part of the unification of the debug format and the MIR format,always print registers as lowercase.* Only debug printing is affected. It now follows MIR.Differential Revision: https://reviews.llvm.org/D40417llvm-svn: 319187 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

f739d8a2 - [X86][SSE] Regenerated the vec_insert tests.

Fri, 01 Apr 2016 19:42:23 +0000

[X86][SSE] Regenerated the vec_insert tests.llvm-svn: 265179 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

3b6feeaa - [X86][SSE41] Combine vector blends with zero

Wed, 24 Feb 2016 15:14:21 +0000

[X86][SSE41] Combine vector blends with zeroPart 2 of 2This patch add support for combining target shuffles into blends-with-zero.Differential Revision: http://reviews.llvm.org/D17483llvm-svn: 261745 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

dd01f700 - [X86][SSE41] Combine insertion of zero scalars into vector blends with zero

Wed, 24 Feb 2016 14:53:27 +0000

[X86][SSE41] Combine insertion of zero scalars into vector blends with zeroPart 1 of 2This patch attempts to replace the insertion of zero scalars with a vector blend with zero, avoiding the use of the integer insertion instructions (which are particularly slow on many targets).(Part 2 will add support for combining multiple blends-with-zero).Differential Revision: http://reviews.llvm.org/D17483llvm-svn: 261743 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

6e69cbe3 - [X86][MMX] Regenerated vector insertion test.

Sun, 03 Jan 2016 19:17:37 +0000

[X86][MMX] Regenerated vector insertion test.Shows the true horror of what is going on....llvm-svn: 256713 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll

43766b61 - Update tests to use sse4.2 instead of sse42.

Fri, 23 Aug 2013 20:46:35 +0000

Update tests to use sse4.2 instead of sse42.llvm-svn: 189145 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-7.ll