Changes in vec_insert-5.ll

2f448bf5 - [X86] Migrate tests to use opaque pointers (NFC)

Wed, 22 Jun 2022 12:33:12 +0000

[X86] Migrate tests to use opaque pointers (NFC)Test updates were performed using:https://gist.github.com/nikic/98357b71fd67756b0f064c9517b62a34These are only the test updates where the test passed withoutfurther modification (which is almost all of them, as the backendis largely pointer-type agnostic). List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

6c0a2c28 - [x86] enhance mayFoldLoad to check alignment

Wed, 27 Oct 2021 11:53:14 +0000

[x86] enhance mayFoldLoad to check alignmentAs noted in D112464, a pre-AVX target may not be able to fold anunder-aligned vector load into another op, so we shouldn't reportthat as a load folding candidate. I only found one caller wherethis would make a difference -- combineCommutableSHUFP() -- sothat's where I added a test to show the (minor) regression.Differential Revision: https://reviews.llvm.org/D112545 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

4f423e91 - [x86] add test/run for mayLoadFold with alignment; NFC

Tue, 26 Oct 2021 14:44:19 +0000

[x86] add test/run for mayLoadFold with alignment; NFC List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

21d02dc5 - [X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add general shuffle combining support

Wed, 02 Sep 2020 08:24:46 +0000

[X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add general shuffle combining supportThis patch uses partial DemandedElts masks to further simplify target shuffle chains and finally starts making target shuffle combining part of SimplifyDemandedBits/SimplifyDemandedVectorElts.We already manage this for Depth == 0 cases, where combineX86ShuffleChain would early-out if the shuffle combined to the same op, but the patch generalizes this by manipulating the depth handling of combineX86ShufflesRecursively - calling with a new Depth = 0 and reducing the maximum shuffle combine depth accordingly.Differential Revision: https://reviews.llvm.org/D66004 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

1a81b296 - [X86][SSE] combineCommutableSHUFP - permilps(shufps(load(),x)) --> permilps(shufps(x,load()))

Sun, 26 Jan 2020 14:31:26 +0000

[X86][SSE] combineCommutableSHUFP - permilps(shufps(load(),x)) --> permilps(shufps(x,load()))Pull out combineTargetShuffle code added in rG3fd5d1c6e7db into a helper function and extend it to handle shufps(shufps(load(),x),y) and shufps(y,shufps(load(),x)) cases as well. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

8b5f2ab2 - Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."

Wed, 07 Aug 2019 16:24:26 +0000

Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."The assert that caused this to be reverted should be fixed now.Original commit message:This patch changes our defualt legalization behavior for 16, 32, and64 bit vectors with i8/i16/i32/i64 scalar types from promotion towidening. For example, v8i8 will now be widened to v16i8 instead ofpromoted to v8i16. This keeps the elements widths the same and padswith undef elements. We believe this is a better legalization strategy.But it carries some issues due to the fragmented vector ISA. Forexample, i8 shifts and multiplies get widened and then later haveto be promoted/split into vXi16 vectors.This has the potential to cause regressions so we wanted to getit in early in the 10.0 cycle so we have plenty of time toaddress them.Next steps will be to merge tests that explicitly test the commandline option. And then we can remove the option and its associatedcode.llvm-svn: 368183 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

bd0d97e1 - Revert "[X86] Enable -x86-experimental-vector-widening-legalization by default."

Tue, 06 Aug 2019 23:00:43 +0000

Revert "[X86] Enable -x86-experimental-vector-widening-legalization by default."This reverts commit 3de33245d2c992c9e0af60372043540b60f3a810.This commit broke the MSan buildbots. Seehttps://reviews.llvm.org/rL367901 for more information.llvm-svn: 368107 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

3de33245 - [X86] Enable -x86-experimental-vector-widening-legalization by default.

Mon, 05 Aug 2019 18:25:36 +0000

[X86] Enable -x86-experimental-vector-widening-legalization by default.This patch changes our defualt legalization behavior for 16, 32, and64 bit vectors with i8/i16/i32/i64 scalar types from promotion towidening. For example, v8i8 will now be widened to v16i8 instead ofpromoted to v8i16. This keeps the elements widths the same and padswith undef elements. We believe this is a better legalization strategy.But it carries some issues due to the fragmented vector ISA. Forexample, i8 shifts and multiplies get widened and then later haveto be promoted/split into vXi16 vectors.This has the potential to cause regressions so we wanted to getit in early in the 10.0 cycle so we have plenty of time toaddress them.Next steps will be to merge tests that explicitly test the commandline option. And then we can remove the option and its associatedcode.llvm-svn: 367901 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

d33e62c8 - [X86][SSE] Fold scalar_to_vector(i64 anyext(x)) -> bitcast(scalar_to_vector(i32 anyext(x)))

Fri, 15 Mar 2019 19:14:28 +0000

[X86][SSE] Fold scalar_to_vector(i64 anyext(x)) -> bitcast(scalar_to_vector(i32 anyext(x)))Reduce the size of an any-extended i64 scalar_to_vector source to i32 - the any_extend nodes are often introduced by SimplifyDemandedBits.llvm-svn: 356292 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

43e94b15 - Followup on Proposal to move MIR physical register namespace to '$' sigil.

Wed, 31 Jan 2018 22:04:26 +0000

Followup on Proposal to move MIR physical register namespace to '$' sigil.Discussed here:http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.htmlIn preparation for adding support for named vregs we are changing the sigil forphysical registers in MIR to '$' from '%'. This will prevent name clashes ofnamed physical register with named vregs.llvm-svn: 323922 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

a8a83d15 - [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

Thu, 07 Dec 2017 10:40:31 +0000

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Work towards the unification of MIR and debug output by refactoring theinterfaces.For MachineOperand::print, keep a simple version that can be easily calledfrom `dump()`, and a more complex one which will be called from both theMIRPrinter and MachineInstr::print.Add extra checks inside MachineOperand for detached operands (operandswith getParent() == nullptr).https://reviews.llvm.org/D40836* find . $ -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" $ -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+) ([^ ]+)/kill: \1 def \2 \3/g'* find . $ -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" $ -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+) ([^ ]+)/kill: \1 \2 def \3/g'* find . $ -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" $ -type f -print0 | xargs -0 sed -i '' -E 's/kill: def ([^ ]+) ([^ ]+) ([^ ]+)/kill: def \1 \2 def \3/g'* find . $ -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" $ -type f -print0 | xargs -0 sed -i '' -E 's///g'* find . $ -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" $ -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/killed \1/g'* find . $ -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" $ -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/implicit killed \1/g'* find . $ -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" $ -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/dead \1/g'* find . $ -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" $ -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/dead \1/g'* find . $ -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" $ -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/implicit-def dead \1/g'* find . $ -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" $ -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/implicit-def \1/g'* find . $ -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" $ -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/implicit \1/g'* find . $ -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" $ -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/internal \1/g'* find . $ -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" $ -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/undef \1/g'llvm-svn: 320022 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

25528d6d - [CodeGen] Unify MBB reference format in both MIR and debug output

Mon, 04 Dec 2017 17:18:51 +0000

[CodeGen] Unify MBB reference format in both MIR and debug outputAs part of the unification of the debug format and the MIR format, printMBB references as '%bb.5'.The MIR printer prints the IR name of a MBB only for block definitions.* find . $ -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" $ -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber/" << printMBBReference(*\1)/g'* find . $ -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" $ -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber/" << printMBBReference(\1)/g'* find . $ -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" $ -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'* grep -nr 'BB#' and fixDifferential Revision: https://reviews.llvm.org/D40422llvm-svn: 319665 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

9d7bb0cb - [CodeGen] Print register names in lowercase in both MIR and debug output

Tue, 28 Nov 2017 17:15:09 +0000

[CodeGen] Print register names in lowercase in both MIR and debug outputAs part of the unification of the debug format and the MIR format,always print registers as lowercase.* Only debug printing is affected. It now follows MIR.Differential Revision: https://reviews.llvm.org/D40417llvm-svn: 319187 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

d9fb1578 - [X86][SSE2] Fix asm string for movq (Move Quadword) instruction.

Wed, 26 Apr 2017 07:08:44 +0000

[X86][SSE2] Fix asm string for movq (Move Quadword) instruction.Replace "mov{d|q}" with "movq".Differential Revision: https://reviews.llvm.org/D32220llvm-svn: 301386 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

7d168e19 - [X86][SSE] Enable commutation between MOVHLPS and UNPCKHPD

Sat, 06 Aug 2016 18:40:28 +0000

[X86][SSE] Enable commutation between MOVHLPS and UNPCKHPDAssuming SSE2 is available then we can safely commute between these, removing some unnecessary register moves and improving memory folding opportunities.VEX encoded versions don't benefit so I haven't added support to them.llvm-svn: 277930 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

152e7c8b - VirtRegMap: Replace some identity copies with KILL instructions.

Sat, 09 Jul 2016 00:19:07 +0000

VirtRegMap: Replace some identity copies with KILL instructions.An identity COPY like this: %AL = COPY %AL, %EAXhas no semantic effect, but encodes liveness information: Further usersof %EAX only depend on this instruction even though it does not definethe full register.Replace the COPY with a KILL instruction in those cases to maintain thisliveness information. (This reverts a small part of r238588 but thistime adds a comment explaining why a KILL instruction is useful).llvm-svn: 274952 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

f739d8a2 - [X86][SSE] Regenerated the vec_insert tests.

Fri, 01 Apr 2016 19:42:23 +0000

[X86][SSE] Regenerated the vec_insert tests.llvm-svn: 265179 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

7c905063 - Make utils/update_llc_test_checks.py note that the assertions are

Mon, 23 Nov 2015 21:33:58 +0000

Make utils/update_llc_test_checks.py note that the assertions areautogenerated.Also update existing test cases which appear to be generated by it andweren't modified (other than addition of the header) by rerunning it.llvm-svn: 253917 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

c03d93ba - [X86] add an exedepfix entry for movq == movlps == movlpd

Wed, 15 Apr 2015 15:47:51 +0000

[X86] add an exedepfix entry for movq == movlps == movlpdThis is a 1-line patch (with a TODO for AVX because that will affecteven more regression tests) that lets us substitute the appropriate64-bit store for the float/double/int domains.It's not clear to me exactly what the difference is between the 0xD6 (MOVPQI2QImr) and 0x7E (MOVSDto64mr) opcodes, but this is apparently the right choice.Differential Revision: http://reviews.llvm.org/D8691llvm-svn: 235014 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll

ed2ba33b - [DAGCombiner] Combine shuffles of BUILD_VECTOR and SCALAR_TO_VECTOR

Fri, 03 Apr 2015 10:02:21 +0000

[DAGCombiner] Combine shuffles of BUILD_VECTOR and SCALAR_TO_VECTORThis patch attempts to fold the shuffling of 'scalar source' inputs - BUILD_VECTOR and SCALAR_TO_VECTOR nodes - if the shuffle node is the only user. This folds away a lot of unnecessary shuffle nodes, and allows quite a bit of constant folding that was being missed.Differential Revision: http://reviews.llvm.org/D8516llvm-svn: 234004 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/vec_insert-5.ll