en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir#48904e94 [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsingSummary:This catches malformed mir files which specify alignment as log2 instead of pow2.See https://reviews.llvm.org/D65945 for reference,This is patch is part of a series to introduce an Alignment type.See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.htmlSee this patch for the introduction of the type: https://reviews.llvm.org/D64790Reviewers: courbetSubscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D67433llvm-svn: 371608 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir Wed, 11 Sep 2019 11:16:48 +0000 Guillaume Chatelet <gchatelet@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir#acc008cb [globalisel] Remove redundant -global-isel option from tests that use -run-pass. NFCAs Roman Tereshin pointed out in https://reviews.llvm.org/D45541, the-global-isel option is redundant when -run-pass is given. -global-isel sets upthe GlobalISel passes in the pass manager but -run-pass skips that entirely andconfigures it's own pipeline.llvm-svn: 331603 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir Sat, 05 May 2018 21:19:59 +0000 Daniel Sanders <daniel_l_sanders@apple.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir#43e94b15 Followup on Proposal to move MIR physical register namespace to '$' sigil.Discussed here:http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.htmlIn preparation for adding support for named vregs we are changing the sigil forphysical registers in MIR to '$' from '%'. This will prevent name clashes ofnamed physical register with named vregs.llvm-svn: 323922 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir Wed, 31 Jan 2018 22:04:26 +0000 Puyan Lotfi <puyan@puyan.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir#6c452834 MIR: Print the register class or bank in vreg defsThis updates the MIRPrinter to include the regclass when printingvirtual register defs, which is already valid syntax for theparser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64)would now be written as %1:gpr(s64) = COPY %0(s64)While this change alone introduces a bit of redundancy with theregisters block, it allows us to update the tests to be more conciseand understandable and brings us closer to being able to remove theregisters block completely.Note: We generally only print the class in defs, but there is oneexception. If there are uses without any defs whatsoever, we'll printthe class on all uses. I'm not completely convinced this comes up inmeaningful machine IR, but for now the MIRParser and MachineVerifierboth accept that kind of stuff, so we don't want to have a situationwhere we can print something we can't parse.llvm-svn: 316479 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir Tue, 24 Oct 2017 18:04:54 +0000 Justin Bogner <mail@justinbogner.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir#1c29be7e [GlobalISel][X86] Support vector type G_INSERT legalization/selection.Summary:Support vector type G_INSERT legalization/selection.Split from https://reviews.llvm.org/D33665Reviewers: qcolombet, t.p.northover, zvi, guyblankReviewed By: guyblankSubscribers: guyblank, rovka, llvm-commits, kristof.beylsDifferential Revision: https://reviews.llvm.org/D33956llvm-svn: 305989 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir Thu, 22 Jun 2017 09:43:35 +0000 Igor Breger <igor.breger@intel.com>