en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll#2f448bf5 [X86] Migrate tests to use opaque pointers (NFC)Test updates were performed using:https://gist.github.com/nikic/98357b71fd67756b0f064c9517b62a34These are only the test updates where the test passed withoutfurther modification (which is almost all of them, as the backendis largely pointer-type agnostic). List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll Wed, 22 Jun 2022 12:33:12 +0000 Nikita Popov <npopov@redhat.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll#373ce147 [X86][AMX] Replace PXOR instruction with SET0 in AMX pre config.To generate zero value, the PXOR instruction need 3 operands that istied to the same vreg. If is not good in SSA form and with undef valuetwo address instruction pass may convert`%0:vr128 = PXORrr undef %0, undef %0`to `%1:vr128 = PXORrr undef %1:vr128(tied-def 0), undef %0:vr128`.It is not expected.It can be simplified to SET0 instruction which only take 1 destinationoperand. It should be more friendly to two address instruction pass andregister allocation pass.`%0:vr128 = V_SET0`Also add AVX1 code path so that it is consistant to other code.Differential Revision: https://reviews.llvm.org/D124903 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll Wed, 04 May 2022 04:39:45 +0000 Luo, Yuanke <yuanke.luo@intel.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll#a3b52a9d [X86][AMX] Refactor for PostRA ldtilecfg pass.This is a follow up of D99010. We didn't consider the live range of shape registers when hoist ldtilecfg. There maybe risks, e.g. we happen to insert it to an invalid range of some registers and get unexpected error.This patch fixes this problem by storing the value to corresponding stack place of ldtilecfg after all its definition immediately.This patch also fix a problem in previous code: If we don't have a ldtilecfg which dominates all AMX instructions, we cannot initialize shapes for other ldtilecfg.There're still some optimization points left. E.g. eliminate unused mov instructions, break the def-use dependency before RA etc.Reviewed By: LuoYuanke, xiangzhangllvmDifferential Revision: https://reviews.llvm.org/D99966 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll Wed, 14 Apr 2021 01:32:48 +0000 Wang, Pengfei <pengfei.wang@intel.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll#4cbaaf4a [X86][AMX] Hoist ldtilecfgThe previous code calculated the first ldtilecfg by dominating all AMX registers' def. This may result in the ldtilecfg being inserted into a loop.This patch try to calculate the nearest point where all shapes of AMX registers are reachable.Reviewed By: LuoYuankeDifferential Revision: https://reviews.llvm.org/D99010 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll Mon, 12 Apr 2021 14:08:27 +0000 Wang, Pengfei <pengfei.wang@intel.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll#a5d9e0c7 [X86] Fix tile config register spill issue.This is an optimized approach for D94155.Previous code build the model that tile config register is the user ofeach AMX instruction. There is a problem for the tile config registerspill. When across function, the ldtilecfg instruction may be insertedon each AMX instruction which use tile config register. This cause alltile data register clobber.To fix this issue, we remove the model of tile config register. Instead,we analyze the AMX instructions between one call to another. We willinsert ldtilecfg after the first call if we find any AMX instructions.Reviewed By: LuoYuankeDifferential Revision: https://reviews.llvm.org/D95136 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll Sat, 30 Jan 2021 04:00:55 +0000 Wang, Pengfei <pengfei.wang@intel.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll#20013d02 [X86][AMX] Fix tile config register spill issue.Previous code build the model that tile config register is the user ofeach AMX instruction. There is a problem for the tile config registerspill. When across function, the ldtilecfg instruction may be insertedon each AMX instruction which use tile config register. This cause alltile data register clobber.To fix this issue, we remove the model of tile config register. Weanalyze the regmask of call instruction and insert ldtilecfg if there isany tile data register live across the call. Inserting the sttilecfgbefore the call is unneccessary, because the tile config doesn't changeand we can just reload the config.Besides we also need check tile config register interference. Since wedon't model the config register we should check interference from theldtilecfg to each tile data register def. ldtilecfg / \ BB1 BB2 / \ call BB3 / \ %1=tileload %2=tilezeroWe can start from the instruction of each tile def, and backward toldtilecfg. If there is any call instruction, and tile data register isnot preserved, we should insert ldtilecfg after the call instruction.Differential Revision: https://reviews.llvm.org/D94155 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll Tue, 05 Jan 2021 13:41:51 +0000 Luo, Yuanke <yuanke.luo@intel.com>